# HG changeset patch # User Josef Eisl # Date 1448892438 -3600 # Node ID fa5100c27dace747cda084d70cf1c8207266c5a8 # Parent a720fbf1810a62971f72d84638c40e05ed5656ab TraceRA: remove TraceRegisterAllocationFixupPhase. diff -r a720fbf1810a -r fa5100c27dac graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationFixupPhase.java --- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationFixupPhase.java Mon Nov 30 15:01:06 2015 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2015, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - */ -package com.oracle.graal.lir.alloc.trace; - -import java.util.List; - -import jdk.vm.ci.code.TargetDescription; - -import com.oracle.graal.compiler.common.cfg.AbstractBlockBase; -import com.oracle.graal.debug.Debug; -import com.oracle.graal.debug.Indent; -import com.oracle.graal.lir.LIR; -import com.oracle.graal.lir.gen.LIRGenerationResult; -import com.oracle.graal.lir.ssi.SSIUtil; - -/** - * TODO(zapster) document me! - * - */ -public final class TraceRegisterAllocationFixupPhase extends TraceAllocationPhase { - - @Override - protected > void run(TargetDescription target, LIRGenerationResult lirGenRes, List codeEmittingOrder, List linearScanOrder, TraceAllocationContext context) { - LIR lir = lirGenRes.getLIR(); - /* - * Incoming Values are needed for the RegisterVerifier, otherwise SIGMAs/PHIs where the Out - * and In value matches (ie. there is no resolution move) are falsely detected as errors. - */ - for (AbstractBlockBase block : lir.getControlFlowGraph().getBlocks()) { - try (Indent i = Debug.logAndIndent("Fixup Block %s", block)) { - if (block.getPredecessorCount() != 0) { - SSIUtil.removeIncoming(lir, block); - } else { - assert lir.getControlFlowGraph().getStartBlock().equals(block); - } - SSIUtil.removeOutgoing(lir, block); - } - } - } -} diff -r a720fbf1810a -r fa5100c27dac graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java --- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java Mon Nov 30 15:01:06 2015 +0100 +++ b/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java Mon Nov 30 15:07:18 2015 +0100 @@ -46,6 +46,7 @@ import com.oracle.graal.lir.gen.LIRGenerationResult; import com.oracle.graal.lir.gen.LIRGeneratorTool.MoveFactory; import com.oracle.graal.lir.phases.AllocationPhase; +import com.oracle.graal.lir.ssi.SSIUtil; import com.oracle.graal.lir.ssi.SSIVerifier; /** @@ -64,7 +65,6 @@ // @formatter:on } - private static final TraceRegisterAllocationFixupPhase TRACE_REGISTER_ALLOCATION_FIXUP_PHASE = new TraceRegisterAllocationFixupPhase(); private static final TraceGlobalMoveResolutionPhase TRACE_GLOBAL_MOVE_RESOLUTION_PHASE = new TraceGlobalMoveResolutionPhase(); private static final TraceTrivialAllocator TRACE_TRIVIAL_ALLOCATOR = new TraceTrivialAllocator(); @@ -111,7 +111,26 @@ Debug.dump(lir, "After trace allocation"); TRACE_GLOBAL_MOVE_RESOLUTION_PHASE.apply(target, lirGenRes, codeEmittingOrder, linearScanOrder, traceContext); - TRACE_REGISTER_ALLOCATION_FIXUP_PHASE.apply(target, lirGenRes, codeEmittingOrder, linearScanOrder, traceContext); + deconstructSSIForm(lir); + } + + /** + * Remove Phi/Sigma In/Out. + * + * Note: Incoming Values are needed for the RegisterVerifier, otherwise SIGMAs/PHIs where the + * Out and In value matches (ie. there is no resolution move) are falsely detected as errors. + */ + private static void deconstructSSIForm(LIR lir) { + for (AbstractBlockBase block : lir.getControlFlowGraph().getBlocks()) { + try (Indent i = Debug.logAndIndent("Fixup Block %s", block)) { + if (block.getPredecessorCount() != 0) { + SSIUtil.removeIncoming(lir, block); + } else { + assert lir.getControlFlowGraph().getStartBlock().equals(block); + } + SSIUtil.removeOutgoing(lir, block); + } + } } static boolean isTrivialTrace(LIR lir, List> trace) {