Mercurial > hg > graal-compiler
changeset 20814:3accde838126
[SPARC] Fix 32bit division and mulhi (zero/signextend value before op)
author | Stefan Anzinger <stefan.anzinger@oracle.com> |
---|---|
date | Wed, 08 Apr 2015 18:05:23 +0200 |
parents | eb21f2944d7d |
children | 17caeb034a63 |
files | graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java |
diffstat | 1 files changed, 6 insertions(+), 2 deletions(-) [+] |
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--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java Wed Apr 08 15:33:13 2015 +0200 +++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java Wed Apr 08 18:05:23 2015 +0200 @@ -264,9 +264,11 @@ case IMULCC: throw GraalInternalError.unimplemented(); case IDIV: + masm.sra(asRegister(src1), 0, asRegister(src1)); masm.sdivx(asIntReg(src1), constant, asIntReg(dst)); break; case IUDIV: + masm.srl(asRegister(src1), 0, asRegister(src1)); masm.udivx(asIntReg(src1), constant, asIntReg(dst)); break; case IAND: @@ -398,8 +400,8 @@ masm.sdivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)); break; case IUDIV: - masm.signx(asIntReg(src1), asIntReg(src1)); - masm.signx(asIntReg(src2), asIntReg(src2)); + masm.srl(asIntReg(src1), 0, asIntReg(src1)); + masm.srl(asIntReg(src2), 0, asIntReg(src2)); delaySlotLir.emitControlTransfer(crb, masm); exceptionOffset = masm.position(); masm.udivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)); @@ -874,6 +876,8 @@ assert isRegister(x) && isRegister(y) && isRegister(result) && isRegister(scratch); switch (opcode) { case IMUL: + masm.sra(asRegister(x), 0, asRegister(x)); + masm.sra(asRegister(y), 0, asRegister(y)); masm.mulx(asIntReg(x), asIntReg(y), asIntReg(result)); masm.srax(asIntReg(result), 32, asIntReg(result)); break;