7204
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "asm/assembler.inline.hpp"
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27 #include "compiler/disassembler.hpp"
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28 #include "gc_interface/collectedHeap.inline.hpp"
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29 #include "interpreter/interpreter.hpp"
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30 #include "memory/cardTableModRefBS.hpp"
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31 #include "memory/resourceArea.hpp"
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32 #include "prims/methodHandles.hpp"
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33 #include "runtime/biasedLocking.hpp"
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34 #include "runtime/interfaceSupport.hpp"
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35 #include "runtime/objectMonitor.hpp"
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36 #include "runtime/os.hpp"
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37 #include "runtime/sharedRuntime.hpp"
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38 #include "runtime/stubRoutines.hpp"
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39 #ifndef SERIALGC
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40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
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41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
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42 #include "gc_implementation/g1/heapRegion.hpp"
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43 #endif
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44
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45 #ifdef PRODUCT
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46 #define BLOCK_COMMENT(str) /* nothing */
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47 #define STOP(error) stop(error)
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48 #else
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49 #define BLOCK_COMMENT(str) block_comment(str)
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50 #define STOP(error) block_comment(error); stop(error)
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51 #endif
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52
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53 // Convert the raw encoding form into the form expected by the
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54 // constructor for Address.
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55 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
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56 assert(scale == 0, "not supported");
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57 RelocationHolder rspec;
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58 if (disp_reloc != relocInfo::none) {
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59 rspec = Relocation::spec_simple(disp_reloc);
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60 }
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61
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62 Register rindex = as_Register(index);
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63 if (rindex != G0) {
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64 Address madr(as_Register(base), rindex);
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65 madr._rspec = rspec;
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66 return madr;
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67 } else {
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68 Address madr(as_Register(base), disp);
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69 madr._rspec = rspec;
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70 return madr;
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71 }
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72 }
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73
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74 Address Argument::address_in_frame() const {
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75 // Warning: In LP64 mode disp will occupy more than 10 bits, but
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76 // op codes such as ld or ldx, only access disp() to get
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77 // their simm13 argument.
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78 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
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79 if (is_in())
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80 return Address(FP, disp); // In argument.
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81 else
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82 return Address(SP, disp); // Out argument.
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83 }
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84
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85 static const char* argumentNames[][2] = {
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86 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
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87 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
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88 {"A(n>9)","P(n>9)"}
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89 };
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90
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91 const char* Argument::name() const {
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92 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
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93 int num = number();
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94 if (num >= nofArgs) num = nofArgs - 1;
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95 return argumentNames[num][is_in() ? 1 : 0];
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96 }
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97
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98 #ifdef ASSERT
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99 // On RISC, there's no benefit to verifying instruction boundaries.
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100 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
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101 #endif
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102
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103 // Patch instruction inst at offset inst_pos to refer to dest_pos
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104 // and return the resulting instruction.
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105 // We should have pcs, not offsets, but since all is relative, it will work out
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106 // OK.
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107 int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {
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108 int m; // mask for displacement field
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109 int v; // new value for displacement field
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110 const int word_aligned_ones = -4;
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111 switch (inv_op(inst)) {
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112 default: ShouldNotReachHere();
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113 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
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114 case branch_op:
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115 switch (inv_op2(inst)) {
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116 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
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117 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
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118 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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119 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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120 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
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121 case bpr_op2: {
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122 if (is_cbcond(inst)) {
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123 m = wdisp10(word_aligned_ones, 0);
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124 v = wdisp10(dest_pos, inst_pos);
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125 } else {
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126 m = wdisp16(word_aligned_ones, 0);
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127 v = wdisp16(dest_pos, inst_pos);
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128 }
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129 break;
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130 }
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131 default: ShouldNotReachHere();
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132 }
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133 }
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134 return inst & ~m | v;
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135 }
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136
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137 // Return the offset of the branch destionation of instruction inst
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138 // at offset pos.
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139 // Should have pcs, but since all is relative, it works out.
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140 int MacroAssembler::branch_destination(int inst, int pos) {
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141 int r;
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142 switch (inv_op(inst)) {
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143 default: ShouldNotReachHere();
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144 case call_op: r = inv_wdisp(inst, pos, 30); break;
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145 case branch_op:
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146 switch (inv_op2(inst)) {
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147 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
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148 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
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149 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
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150 case br_op2: r = inv_wdisp( inst, pos, 22); break;
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151 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
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152 case bpr_op2: {
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153 if (is_cbcond(inst)) {
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154 r = inv_wdisp10(inst, pos);
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155 } else {
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156 r = inv_wdisp16(inst, pos);
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157 }
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158 break;
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159 }
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160 default: ShouldNotReachHere();
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161 }
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162 }
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163 return r;
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164 }
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165
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166 void MacroAssembler::null_check(Register reg, int offset) {
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167 if (needs_explicit_null_check((intptr_t)offset)) {
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168 // provoke OS NULL exception if reg = NULL by
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169 // accessing M[reg] w/o changing any registers
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170 ld_ptr(reg, 0, G0);
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171 }
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172 else {
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173 // nothing to do, (later) access of M[reg + offset]
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174 // will provoke OS NULL exception if reg = NULL
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175 }
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176 }
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177
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178 // Ring buffer jumps
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179
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180 #ifndef PRODUCT
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181 void MacroAssembler::ret( bool trace ) { if (trace) {
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182 mov(I7, O7); // traceable register
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183 JMP(O7, 2 * BytesPerInstWord);
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184 } else {
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185 jmpl( I7, 2 * BytesPerInstWord, G0 );
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186 }
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187 }
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188
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189 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
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190 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
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191 #endif /* PRODUCT */
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192
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193
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194 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
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195 assert_not_delayed();
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196 // This can only be traceable if r1 & r2 are visible after a window save
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197 if (TraceJumps) {
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198 #ifndef PRODUCT
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199 save_frame(0);
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200 verify_thread();
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201 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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202 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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203 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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204 add(O2, O1, O1);
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205
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206 add(r1->after_save(), r2->after_save(), O2);
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207 set((intptr_t)file, O3);
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208 set(line, O4);
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209 Label L;
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210 // get nearby pc, store jmp target
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211 call(L, relocInfo::none); // No relocation for call to pc+0x8
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212 delayed()->st(O2, O1, 0);
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213 bind(L);
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214
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215 // store nearby pc
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216 st(O7, O1, sizeof(intptr_t));
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217 // store file
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218 st(O3, O1, 2*sizeof(intptr_t));
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219 // store line
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220 st(O4, O1, 3*sizeof(intptr_t));
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221 add(O0, 1, O0);
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222 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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223 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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224 restore();
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225 #endif /* PRODUCT */
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226 }
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227 jmpl(r1, r2, G0);
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228 }
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229 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
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230 assert_not_delayed();
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231 // This can only be traceable if r1 is visible after a window save
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232 if (TraceJumps) {
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233 #ifndef PRODUCT
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234 save_frame(0);
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235 verify_thread();
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236 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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237 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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238 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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239 add(O2, O1, O1);
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240
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241 add(r1->after_save(), offset, O2);
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242 set((intptr_t)file, O3);
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243 set(line, O4);
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244 Label L;
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245 // get nearby pc, store jmp target
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246 call(L, relocInfo::none); // No relocation for call to pc+0x8
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247 delayed()->st(O2, O1, 0);
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248 bind(L);
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249
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250 // store nearby pc
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251 st(O7, O1, sizeof(intptr_t));
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252 // store file
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253 st(O3, O1, 2*sizeof(intptr_t));
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254 // store line
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255 st(O4, O1, 3*sizeof(intptr_t));
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256 add(O0, 1, O0);
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257 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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258 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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259 restore();
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260 #endif /* PRODUCT */
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261 }
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262 jmp(r1, offset);
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263 }
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264
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265 // This code sequence is relocatable to any address, even on LP64.
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266 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
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267 assert_not_delayed();
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268 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
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269 // variable length instruction streams.
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270 patchable_sethi(addrlit, temp);
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271 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
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272 if (TraceJumps) {
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273 #ifndef PRODUCT
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274 // Must do the add here so relocation can find the remainder of the
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275 // value to be relocated.
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276 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
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277 save_frame(0);
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278 verify_thread();
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279 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
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280 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
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281 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
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282 add(O2, O1, O1);
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283
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284 set((intptr_t)file, O3);
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285 set(line, O4);
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286 Label L;
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287
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288 // get nearby pc, store jmp target
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289 call(L, relocInfo::none); // No relocation for call to pc+0x8
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290 delayed()->st(a.base()->after_save(), O1, 0);
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291 bind(L);
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292
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293 // store nearby pc
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294 st(O7, O1, sizeof(intptr_t));
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295 // store file
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296 st(O3, O1, 2*sizeof(intptr_t));
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297 // store line
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298 st(O4, O1, 3*sizeof(intptr_t));
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299 add(O0, 1, O0);
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300 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
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301 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
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302 restore();
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303 jmpl(a.base(), G0, d);
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304 #else
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305 jmpl(a.base(), a.disp(), d);
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306 #endif /* PRODUCT */
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307 } else {
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308 jmpl(a.base(), a.disp(), d);
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309 }
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310 }
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311
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312 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
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313 jumpl(addrlit, temp, G0, offset, file, line);
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314 }
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315
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316
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317 // Conditional breakpoint (for assertion checks in assembly code)
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318 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
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319 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
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320 }
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321
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322 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
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323 void MacroAssembler::breakpoint_trap() {
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324 trap(ST_RESERVED_FOR_USER_0);
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325 }
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326
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327 // flush windows (except current) using flushw instruction if avail.
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328 void MacroAssembler::flush_windows() {
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329 if (VM_Version::v9_instructions_work()) flushw();
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330 else flush_windows_trap();
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331 }
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332
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333 // Write serialization page so VM thread can do a pseudo remote membar
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334 // We use the current thread pointer to calculate a thread specific
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335 // offset to write to within the page. This minimizes bus traffic
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336 // due to cache line collision.
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337 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
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338 srl(thread, os::get_serialize_page_shift_count(), tmp2);
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339 if (Assembler::is_simm13(os::vm_page_size())) {
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340 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
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341 }
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342 else {
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343 set((os::vm_page_size() - sizeof(int)), tmp1);
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344 and3(tmp2, tmp1, tmp2);
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345 }
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346 set(os::get_memory_serialize_page(), tmp1);
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347 st(G0, tmp1, tmp2);
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348 }
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349
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350
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351
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352 void MacroAssembler::enter() {
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353 Unimplemented();
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354 }
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355
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356 void MacroAssembler::leave() {
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357 Unimplemented();
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358 }
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359
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360 void MacroAssembler::mult(Register s1, Register s2, Register d) {
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361 if(VM_Version::v9_instructions_work()) {
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362 mulx (s1, s2, d);
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363 } else {
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364 smul (s1, s2, d);
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365 }
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366 }
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367
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368 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
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369 if(VM_Version::v9_instructions_work()) {
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370 mulx (s1, simm13a, d);
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371 } else {
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372 smul (s1, simm13a, d);
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373 }
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374 }
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375
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376
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377 #ifdef ASSERT
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378 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
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379 const Register s1 = G3_scratch;
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380 const Register s2 = G4_scratch;
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381 Label get_psr_test;
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382 // Get the condition codes the V8 way.
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383 read_ccr_trap(s1);
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384 mov(ccr_save, s2);
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385 // This is a test of V8 which has icc but not xcc
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386 // so mask off the xcc bits
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387 and3(s2, 0xf, s2);
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388 // Compare condition codes from the V8 and V9 ways.
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389 subcc(s2, s1, G0);
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390 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
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391 delayed()->breakpoint_trap();
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392 bind(get_psr_test);
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393 }
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394
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395 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
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396 const Register s1 = G3_scratch;
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397 const Register s2 = G4_scratch;
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398 Label set_psr_test;
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399 // Write out the saved condition codes the V8 way
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400 write_ccr_trap(ccr_save, s1, s2);
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401 // Read back the condition codes using the V9 instruction
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402 rdccr(s1);
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403 mov(ccr_save, s2);
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404 // This is a test of V8 which has icc but not xcc
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405 // so mask off the xcc bits
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406 and3(s2, 0xf, s2);
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407 and3(s1, 0xf, s1);
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408 // Compare the V8 way with the V9 way.
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409 subcc(s2, s1, G0);
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410 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
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411 delayed()->breakpoint_trap();
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412 bind(set_psr_test);
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413 }
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414 #else
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415 #define read_ccr_v8_assert(x)
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416 #define write_ccr_v8_assert(x)
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417 #endif // ASSERT
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418
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419 void MacroAssembler::read_ccr(Register ccr_save) {
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420 if (VM_Version::v9_instructions_work()) {
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421 rdccr(ccr_save);
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422 // Test code sequence used on V8. Do not move above rdccr.
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423 read_ccr_v8_assert(ccr_save);
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424 } else {
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425 read_ccr_trap(ccr_save);
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426 }
|
|
427 }
|
|
428
|
|
429 void MacroAssembler::write_ccr(Register ccr_save) {
|
|
430 if (VM_Version::v9_instructions_work()) {
|
|
431 // Test code sequence used on V8. Do not move below wrccr.
|
|
432 write_ccr_v8_assert(ccr_save);
|
|
433 wrccr(ccr_save);
|
|
434 } else {
|
|
435 const Register temp_reg1 = G3_scratch;
|
|
436 const Register temp_reg2 = G4_scratch;
|
|
437 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
|
|
438 }
|
|
439 }
|
|
440
|
|
441
|
|
442 // Calls to C land
|
|
443
|
|
444 #ifdef ASSERT
|
|
445 // a hook for debugging
|
|
446 static Thread* reinitialize_thread() {
|
|
447 return ThreadLocalStorage::thread();
|
|
448 }
|
|
449 #else
|
|
450 #define reinitialize_thread ThreadLocalStorage::thread
|
|
451 #endif
|
|
452
|
|
453 #ifdef ASSERT
|
|
454 address last_get_thread = NULL;
|
|
455 #endif
|
|
456
|
|
457 // call this when G2_thread is not known to be valid
|
|
458 void MacroAssembler::get_thread() {
|
|
459 save_frame(0); // to avoid clobbering O0
|
|
460 mov(G1, L0); // avoid clobbering G1
|
|
461 mov(G5_method, L1); // avoid clobbering G5
|
|
462 mov(G3, L2); // avoid clobbering G3 also
|
|
463 mov(G4, L5); // avoid clobbering G4
|
|
464 #ifdef ASSERT
|
|
465 AddressLiteral last_get_thread_addrlit(&last_get_thread);
|
|
466 set(last_get_thread_addrlit, L3);
|
|
467 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
|
|
468 st_ptr(L4, L3, 0);
|
|
469 #endif
|
|
470 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
|
|
471 delayed()->nop();
|
|
472 mov(L0, G1);
|
|
473 mov(L1, G5_method);
|
|
474 mov(L2, G3);
|
|
475 mov(L5, G4);
|
|
476 restore(O0, 0, G2_thread);
|
|
477 }
|
|
478
|
|
479 static Thread* verify_thread_subroutine(Thread* gthread_value) {
|
|
480 Thread* correct_value = ThreadLocalStorage::thread();
|
|
481 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
|
|
482 return correct_value;
|
|
483 }
|
|
484
|
|
485 void MacroAssembler::verify_thread() {
|
|
486 if (VerifyThread) {
|
|
487 // NOTE: this chops off the heads of the 64-bit O registers.
|
|
488 #ifdef CC_INTERP
|
|
489 save_frame(0);
|
|
490 #else
|
|
491 // make sure G2_thread contains the right value
|
|
492 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
|
|
493 mov(G1, L1); // avoid clobbering G1
|
|
494 // G2 saved below
|
|
495 mov(G3, L3); // avoid clobbering G3
|
|
496 mov(G4, L4); // avoid clobbering G4
|
|
497 mov(G5_method, L5); // avoid clobbering G5_method
|
|
498 #endif /* CC_INTERP */
|
|
499 #if defined(COMPILER2) && !defined(_LP64)
|
|
500 // Save & restore possible 64-bit Long arguments in G-regs
|
|
501 srlx(G1,32,L0);
|
|
502 srlx(G4,32,L6);
|
|
503 #endif
|
|
504 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
|
|
505 delayed()->mov(G2_thread, O0);
|
|
506
|
|
507 mov(L1, G1); // Restore G1
|
|
508 // G2 restored below
|
|
509 mov(L3, G3); // restore G3
|
|
510 mov(L4, G4); // restore G4
|
|
511 mov(L5, G5_method); // restore G5_method
|
|
512 #if defined(COMPILER2) && !defined(_LP64)
|
|
513 // Save & restore possible 64-bit Long arguments in G-regs
|
|
514 sllx(L0,32,G2); // Move old high G1 bits high in G2
|
|
515 srl(G1, 0,G1); // Clear current high G1 bits
|
|
516 or3 (G1,G2,G1); // Recover 64-bit G1
|
|
517 sllx(L6,32,G2); // Move old high G4 bits high in G2
|
|
518 srl(G4, 0,G4); // Clear current high G4 bits
|
|
519 or3 (G4,G2,G4); // Recover 64-bit G4
|
|
520 #endif
|
|
521 restore(O0, 0, G2_thread);
|
|
522 }
|
|
523 }
|
|
524
|
|
525
|
|
526 void MacroAssembler::save_thread(const Register thread_cache) {
|
|
527 verify_thread();
|
|
528 if (thread_cache->is_valid()) {
|
|
529 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
|
|
530 mov(G2_thread, thread_cache);
|
|
531 }
|
|
532 if (VerifyThread) {
|
|
533 // smash G2_thread, as if the VM were about to anyway
|
|
534 set(0x67676767, G2_thread);
|
|
535 }
|
|
536 }
|
|
537
|
|
538
|
|
539 void MacroAssembler::restore_thread(const Register thread_cache) {
|
|
540 if (thread_cache->is_valid()) {
|
|
541 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
|
|
542 mov(thread_cache, G2_thread);
|
|
543 verify_thread();
|
|
544 } else {
|
|
545 // do it the slow way
|
|
546 get_thread();
|
|
547 }
|
|
548 }
|
|
549
|
|
550
|
|
551 // %%% maybe get rid of [re]set_last_Java_frame
|
|
552 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
|
|
553 assert_not_delayed();
|
|
554 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
|
|
555 JavaFrameAnchor::flags_offset());
|
|
556 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
|
|
557
|
|
558 // Always set last_Java_pc and flags first because once last_Java_sp is visible
|
|
559 // has_last_Java_frame is true and users will look at the rest of the fields.
|
|
560 // (Note: flags should always be zero before we get here so doesn't need to be set.)
|
|
561
|
|
562 #ifdef ASSERT
|
|
563 // Verify that flags was zeroed on return to Java
|
|
564 Label PcOk;
|
|
565 save_frame(0); // to avoid clobbering O0
|
|
566 ld_ptr(pc_addr, L0);
|
|
567 br_null_short(L0, Assembler::pt, PcOk);
|
|
568 STOP("last_Java_pc not zeroed before leaving Java");
|
|
569 bind(PcOk);
|
|
570
|
|
571 // Verify that flags was zeroed on return to Java
|
|
572 Label FlagsOk;
|
|
573 ld(flags, L0);
|
|
574 tst(L0);
|
|
575 br(Assembler::zero, false, Assembler::pt, FlagsOk);
|
|
576 delayed() -> restore();
|
|
577 STOP("flags not zeroed before leaving Java");
|
|
578 bind(FlagsOk);
|
|
579 #endif /* ASSERT */
|
|
580 //
|
|
581 // When returning from calling out from Java mode the frame anchor's last_Java_pc
|
|
582 // will always be set to NULL. It is set here so that if we are doing a call to
|
|
583 // native (not VM) that we capture the known pc and don't have to rely on the
|
|
584 // native call having a standard frame linkage where we can find the pc.
|
|
585
|
|
586 if (last_Java_pc->is_valid()) {
|
|
587 st_ptr(last_Java_pc, pc_addr);
|
|
588 }
|
|
589
|
|
590 #ifdef _LP64
|
|
591 #ifdef ASSERT
|
|
592 // Make sure that we have an odd stack
|
|
593 Label StackOk;
|
|
594 andcc(last_java_sp, 0x01, G0);
|
|
595 br(Assembler::notZero, false, Assembler::pt, StackOk);
|
|
596 delayed()->nop();
|
|
597 STOP("Stack Not Biased in set_last_Java_frame");
|
|
598 bind(StackOk);
|
|
599 #endif // ASSERT
|
|
600 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
|
|
601 add( last_java_sp, STACK_BIAS, G4_scratch );
|
|
602 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
|
|
603 #else
|
|
604 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
|
|
605 #endif // _LP64
|
|
606 }
|
|
607
|
|
608 void MacroAssembler::reset_last_Java_frame(void) {
|
|
609 assert_not_delayed();
|
|
610
|
|
611 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
|
|
612 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
|
|
613 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
|
|
614
|
|
615 #ifdef ASSERT
|
|
616 // check that it WAS previously set
|
|
617 #ifdef CC_INTERP
|
|
618 save_frame(0);
|
|
619 #else
|
|
620 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
|
|
621 #endif /* CC_INTERP */
|
|
622 ld_ptr(sp_addr, L0);
|
|
623 tst(L0);
|
|
624 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
|
|
625 restore();
|
|
626 #endif // ASSERT
|
|
627
|
|
628 st_ptr(G0, sp_addr);
|
|
629 // Always return last_Java_pc to zero
|
|
630 st_ptr(G0, pc_addr);
|
|
631 // Always null flags after return to Java
|
|
632 st(G0, flags);
|
|
633 }
|
|
634
|
|
635
|
|
636 void MacroAssembler::call_VM_base(
|
|
637 Register oop_result,
|
|
638 Register thread_cache,
|
|
639 Register last_java_sp,
|
|
640 address entry_point,
|
|
641 int number_of_arguments,
|
|
642 bool check_exceptions)
|
|
643 {
|
|
644 assert_not_delayed();
|
|
645
|
|
646 // determine last_java_sp register
|
|
647 if (!last_java_sp->is_valid()) {
|
|
648 last_java_sp = SP;
|
|
649 }
|
|
650 // debugging support
|
|
651 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
|
|
652
|
|
653 // 64-bit last_java_sp is biased!
|
|
654 set_last_Java_frame(last_java_sp, noreg);
|
|
655 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
|
|
656 save_thread(thread_cache);
|
|
657 // do the call
|
|
658 call(entry_point, relocInfo::runtime_call_type);
|
|
659 if (!VerifyThread)
|
|
660 delayed()->mov(G2_thread, O0); // pass thread as first argument
|
|
661 else
|
|
662 delayed()->nop(); // (thread already passed)
|
|
663 restore_thread(thread_cache);
|
|
664 reset_last_Java_frame();
|
|
665
|
|
666 // check for pending exceptions. use Gtemp as scratch register.
|
|
667 if (check_exceptions) {
|
|
668 check_and_forward_exception(Gtemp);
|
|
669 }
|
|
670
|
|
671 #ifdef ASSERT
|
|
672 set(badHeapWordVal, G3);
|
|
673 set(badHeapWordVal, G4);
|
|
674 set(badHeapWordVal, G5);
|
|
675 #endif
|
|
676
|
|
677 // get oop result if there is one and reset the value in the thread
|
|
678 if (oop_result->is_valid()) {
|
|
679 get_vm_result(oop_result);
|
|
680 }
|
|
681 }
|
|
682
|
|
683 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
|
|
684 {
|
|
685 Label L;
|
|
686
|
|
687 check_and_handle_popframe(scratch_reg);
|
|
688 check_and_handle_earlyret(scratch_reg);
|
|
689
|
|
690 Address exception_addr(G2_thread, Thread::pending_exception_offset());
|
|
691 ld_ptr(exception_addr, scratch_reg);
|
|
692 br_null_short(scratch_reg, pt, L);
|
|
693 // we use O7 linkage so that forward_exception_entry has the issuing PC
|
|
694 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
|
|
695 delayed()->nop();
|
|
696 bind(L);
|
|
697 }
|
|
698
|
|
699
|
|
700 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
|
|
701 }
|
|
702
|
|
703
|
|
704 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
|
|
705 }
|
|
706
|
|
707
|
|
708 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
|
|
709 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
|
|
710 }
|
|
711
|
|
712
|
|
713 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
|
|
714 // O0 is reserved for the thread
|
|
715 mov(arg_1, O1);
|
|
716 call_VM(oop_result, entry_point, 1, check_exceptions);
|
|
717 }
|
|
718
|
|
719
|
|
720 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
|
|
721 // O0 is reserved for the thread
|
|
722 mov(arg_1, O1);
|
|
723 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
724 call_VM(oop_result, entry_point, 2, check_exceptions);
|
|
725 }
|
|
726
|
|
727
|
|
728 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
|
|
729 // O0 is reserved for the thread
|
|
730 mov(arg_1, O1);
|
|
731 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
732 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
|
|
733 call_VM(oop_result, entry_point, 3, check_exceptions);
|
|
734 }
|
|
735
|
|
736
|
|
737
|
|
738 // Note: The following call_VM overloadings are useful when a "save"
|
|
739 // has already been performed by a stub, and the last Java frame is
|
|
740 // the previous one. In that case, last_java_sp must be passed as FP
|
|
741 // instead of SP.
|
|
742
|
|
743
|
|
744 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
|
|
745 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
|
|
746 }
|
|
747
|
|
748
|
|
749 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
|
|
750 // O0 is reserved for the thread
|
|
751 mov(arg_1, O1);
|
|
752 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
|
|
753 }
|
|
754
|
|
755
|
|
756 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
|
|
757 // O0 is reserved for the thread
|
|
758 mov(arg_1, O1);
|
|
759 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
760 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
|
|
761 }
|
|
762
|
|
763
|
|
764 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
|
|
765 // O0 is reserved for the thread
|
|
766 mov(arg_1, O1);
|
|
767 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
|
|
768 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
|
|
769 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
|
|
770 }
|
|
771
|
|
772
|
|
773
|
|
774 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
|
|
775 assert_not_delayed();
|
|
776 save_thread(thread_cache);
|
|
777 // do the call
|
|
778 call(entry_point, relocInfo::runtime_call_type);
|
|
779 delayed()->nop();
|
|
780 restore_thread(thread_cache);
|
|
781 #ifdef ASSERT
|
|
782 set(badHeapWordVal, G3);
|
|
783 set(badHeapWordVal, G4);
|
|
784 set(badHeapWordVal, G5);
|
|
785 #endif
|
|
786 }
|
|
787
|
|
788
|
|
789 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
|
|
790 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
|
|
791 }
|
|
792
|
|
793
|
|
794 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
|
|
795 mov(arg_1, O0);
|
|
796 call_VM_leaf(thread_cache, entry_point, 1);
|
|
797 }
|
|
798
|
|
799
|
|
800 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
|
|
801 mov(arg_1, O0);
|
|
802 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
|
|
803 call_VM_leaf(thread_cache, entry_point, 2);
|
|
804 }
|
|
805
|
|
806
|
|
807 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
|
|
808 mov(arg_1, O0);
|
|
809 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
|
|
810 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
|
|
811 call_VM_leaf(thread_cache, entry_point, 3);
|
|
812 }
|
|
813
|
|
814
|
|
815 void MacroAssembler::get_vm_result(Register oop_result) {
|
|
816 verify_thread();
|
|
817 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
|
|
818 ld_ptr( vm_result_addr, oop_result);
|
|
819 st_ptr(G0, vm_result_addr);
|
|
820 verify_oop(oop_result);
|
|
821 }
|
|
822
|
|
823
|
|
824 void MacroAssembler::get_vm_result_2(Register metadata_result) {
|
|
825 verify_thread();
|
|
826 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
|
|
827 ld_ptr(vm_result_addr_2, metadata_result);
|
|
828 st_ptr(G0, vm_result_addr_2);
|
|
829 }
|
|
830
|
|
831
|
|
832 // We require that C code which does not return a value in vm_result will
|
|
833 // leave it undisturbed.
|
|
834 void MacroAssembler::set_vm_result(Register oop_result) {
|
|
835 verify_thread();
|
|
836 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
|
|
837 verify_oop(oop_result);
|
|
838
|
|
839 # ifdef ASSERT
|
|
840 // Check that we are not overwriting any other oop.
|
|
841 #ifdef CC_INTERP
|
|
842 save_frame(0);
|
|
843 #else
|
|
844 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
|
|
845 #endif /* CC_INTERP */
|
|
846 ld_ptr(vm_result_addr, L0);
|
|
847 tst(L0);
|
|
848 restore();
|
|
849 breakpoint_trap(notZero, Assembler::ptr_cc);
|
|
850 // }
|
|
851 # endif
|
|
852
|
|
853 st_ptr(oop_result, vm_result_addr);
|
|
854 }
|
|
855
|
|
856
|
|
857 void MacroAssembler::ic_call(address entry, bool emit_delay) {
|
|
858 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
|
|
859 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg);
|
|
860 relocate(rspec);
|
|
861 call(entry, relocInfo::none);
|
|
862 if (emit_delay) {
|
|
863 delayed()->nop();
|
|
864 }
|
|
865 }
|
|
866
|
|
867
|
|
868 void MacroAssembler::card_table_write(jbyte* byte_map_base,
|
|
869 Register tmp, Register obj) {
|
|
870 #ifdef _LP64
|
|
871 srlx(obj, CardTableModRefBS::card_shift, obj);
|
|
872 #else
|
|
873 srl(obj, CardTableModRefBS::card_shift, obj);
|
|
874 #endif
|
|
875 assert(tmp != obj, "need separate temp reg");
|
|
876 set((address) byte_map_base, tmp);
|
|
877 stb(G0, tmp, obj);
|
|
878 }
|
|
879
|
|
880
|
|
881 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
|
|
882 address save_pc;
|
|
883 int shiftcnt;
|
|
884 #ifdef _LP64
|
|
885 # ifdef CHECK_DELAY
|
|
886 assert_not_delayed((char*) "cannot put two instructions in delay slot");
|
|
887 # endif
|
|
888 v9_dep();
|
|
889 save_pc = pc();
|
|
890
|
|
891 int msb32 = (int) (addrlit.value() >> 32);
|
|
892 int lsb32 = (int) (addrlit.value());
|
|
893
|
|
894 if (msb32 == 0 && lsb32 >= 0) {
|
|
895 Assembler::sethi(lsb32, d, addrlit.rspec());
|
|
896 }
|
|
897 else if (msb32 == -1) {
|
|
898 Assembler::sethi(~lsb32, d, addrlit.rspec());
|
|
899 xor3(d, ~low10(~0), d);
|
|
900 }
|
|
901 else {
|
|
902 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
|
|
903 if (msb32 & 0x3ff) // Any bits?
|
|
904 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
|
|
905 if (lsb32 & 0xFFFFFC00) { // done?
|
|
906 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
|
|
907 sllx(d, 12, d); // Make room for next 12 bits
|
|
908 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
|
|
909 shiftcnt = 0; // We already shifted
|
|
910 }
|
|
911 else
|
|
912 shiftcnt = 12;
|
|
913 if ((lsb32 >> 10) & 0x3ff) {
|
|
914 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
|
|
915 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
|
|
916 shiftcnt = 0;
|
|
917 }
|
|
918 else
|
|
919 shiftcnt = 10;
|
|
920 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
|
|
921 }
|
|
922 else
|
|
923 sllx(d, 32, d);
|
|
924 }
|
|
925 // Pad out the instruction sequence so it can be patched later.
|
|
926 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
|
|
927 addrlit.rtype() != relocInfo::runtime_call_type)) {
|
|
928 while (pc() < (save_pc + (7 * BytesPerInstWord)))
|
|
929 nop();
|
|
930 }
|
|
931 #else
|
|
932 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
|
|
933 #endif
|
|
934 }
|
|
935
|
|
936
|
|
937 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
|
|
938 internal_sethi(addrlit, d, false);
|
|
939 }
|
|
940
|
|
941
|
|
942 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
|
|
943 internal_sethi(addrlit, d, true);
|
|
944 }
|
|
945
|
|
946
|
|
947 int MacroAssembler::insts_for_sethi(address a, bool worst_case) {
|
|
948 #ifdef _LP64
|
|
949 if (worst_case) return 7;
|
|
950 intptr_t iaddr = (intptr_t) a;
|
|
951 int msb32 = (int) (iaddr >> 32);
|
|
952 int lsb32 = (int) (iaddr);
|
|
953 int count;
|
|
954 if (msb32 == 0 && lsb32 >= 0)
|
|
955 count = 1;
|
|
956 else if (msb32 == -1)
|
|
957 count = 2;
|
|
958 else {
|
|
959 count = 2;
|
|
960 if (msb32 & 0x3ff)
|
|
961 count++;
|
|
962 if (lsb32 & 0xFFFFFC00 ) {
|
|
963 if ((lsb32 >> 20) & 0xfff) count += 2;
|
|
964 if ((lsb32 >> 10) & 0x3ff) count += 2;
|
|
965 }
|
|
966 }
|
|
967 return count;
|
|
968 #else
|
|
969 return 1;
|
|
970 #endif
|
|
971 }
|
|
972
|
|
973 int MacroAssembler::worst_case_insts_for_set() {
|
|
974 return insts_for_sethi(NULL, true) + 1;
|
|
975 }
|
|
976
|
|
977
|
|
978 // Keep in sync with MacroAssembler::insts_for_internal_set
|
|
979 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
|
|
980 intptr_t value = addrlit.value();
|
|
981
|
|
982 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
|
|
983 // can optimize
|
|
984 if (-4096 <= value && value <= 4095) {
|
|
985 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
|
|
986 return;
|
|
987 }
|
|
988 if (inv_hi22(hi22(value)) == value) {
|
|
989 sethi(addrlit, d);
|
|
990 return;
|
|
991 }
|
|
992 }
|
|
993 assert_not_delayed((char*) "cannot put two instructions in delay slot");
|
|
994 internal_sethi(addrlit, d, ForceRelocatable);
|
|
995 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
|
|
996 add(d, addrlit.low10(), d, addrlit.rspec());
|
|
997 }
|
|
998 }
|
|
999
|
|
1000 // Keep in sync with MacroAssembler::internal_set
|
|
1001 int MacroAssembler::insts_for_internal_set(intptr_t value) {
|
|
1002 // can optimize
|
|
1003 if (-4096 <= value && value <= 4095) {
|
|
1004 return 1;
|
|
1005 }
|
|
1006 if (inv_hi22(hi22(value)) == value) {
|
|
1007 return insts_for_sethi((address) value);
|
|
1008 }
|
|
1009 int count = insts_for_sethi((address) value);
|
|
1010 AddressLiteral al(value);
|
|
1011 if (al.low10() != 0) {
|
|
1012 count++;
|
|
1013 }
|
|
1014 return count;
|
|
1015 }
|
|
1016
|
|
1017 void MacroAssembler::set(const AddressLiteral& al, Register d) {
|
|
1018 internal_set(al, d, false);
|
|
1019 }
|
|
1020
|
|
1021 void MacroAssembler::set(intptr_t value, Register d) {
|
|
1022 AddressLiteral al(value);
|
|
1023 internal_set(al, d, false);
|
|
1024 }
|
|
1025
|
|
1026 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
|
|
1027 AddressLiteral al(addr, rspec);
|
|
1028 internal_set(al, d, false);
|
|
1029 }
|
|
1030
|
|
1031 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
|
|
1032 internal_set(al, d, true);
|
|
1033 }
|
|
1034
|
|
1035 void MacroAssembler::patchable_set(intptr_t value, Register d) {
|
|
1036 AddressLiteral al(value);
|
|
1037 internal_set(al, d, true);
|
|
1038 }
|
|
1039
|
|
1040
|
|
1041 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
|
|
1042 assert_not_delayed();
|
|
1043 v9_dep();
|
|
1044
|
|
1045 int hi = (int)(value >> 32);
|
|
1046 int lo = (int)(value & ~0);
|
|
1047 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
|
|
1048 if (Assembler::is_simm13(lo) && value == lo) {
|
|
1049 or3(G0, lo, d);
|
|
1050 } else if (hi == 0) {
|
|
1051 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
|
|
1052 if (low10(lo) != 0)
|
|
1053 or3(d, low10(lo), d);
|
|
1054 }
|
|
1055 else if (hi == -1) {
|
|
1056 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
|
|
1057 xor3(d, low10(lo) ^ ~low10(~0), d);
|
|
1058 }
|
|
1059 else if (lo == 0) {
|
|
1060 if (Assembler::is_simm13(hi)) {
|
|
1061 or3(G0, hi, d);
|
|
1062 } else {
|
|
1063 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
|
|
1064 if (low10(hi) != 0)
|
|
1065 or3(d, low10(hi), d);
|
|
1066 }
|
|
1067 sllx(d, 32, d);
|
|
1068 }
|
|
1069 else {
|
|
1070 Assembler::sethi(hi, tmp);
|
|
1071 Assembler::sethi(lo, d); // macro assembler version sign-extends
|
|
1072 if (low10(hi) != 0)
|
|
1073 or3 (tmp, low10(hi), tmp);
|
|
1074 if (low10(lo) != 0)
|
|
1075 or3 ( d, low10(lo), d);
|
|
1076 sllx(tmp, 32, tmp);
|
|
1077 or3 (d, tmp, d);
|
|
1078 }
|
|
1079 }
|
|
1080
|
|
1081 int MacroAssembler::insts_for_set64(jlong value) {
|
|
1082 v9_dep();
|
|
1083
|
|
1084 int hi = (int) (value >> 32);
|
|
1085 int lo = (int) (value & ~0);
|
|
1086 int count = 0;
|
|
1087
|
|
1088 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
|
|
1089 if (Assembler::is_simm13(lo) && value == lo) {
|
|
1090 count++;
|
|
1091 } else if (hi == 0) {
|
|
1092 count++;
|
|
1093 if (low10(lo) != 0)
|
|
1094 count++;
|
|
1095 }
|
|
1096 else if (hi == -1) {
|
|
1097 count += 2;
|
|
1098 }
|
|
1099 else if (lo == 0) {
|
|
1100 if (Assembler::is_simm13(hi)) {
|
|
1101 count++;
|
|
1102 } else {
|
|
1103 count++;
|
|
1104 if (low10(hi) != 0)
|
|
1105 count++;
|
|
1106 }
|
|
1107 count++;
|
|
1108 }
|
|
1109 else {
|
|
1110 count += 2;
|
|
1111 if (low10(hi) != 0)
|
|
1112 count++;
|
|
1113 if (low10(lo) != 0)
|
|
1114 count++;
|
|
1115 count += 2;
|
|
1116 }
|
|
1117 return count;
|
|
1118 }
|
|
1119
|
|
1120 // compute size in bytes of sparc frame, given
|
|
1121 // number of extraWords
|
|
1122 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
|
|
1123
|
|
1124 int nWords = frame::memory_parameter_word_sp_offset;
|
|
1125
|
|
1126 nWords += extraWords;
|
|
1127
|
|
1128 if (nWords & 1) ++nWords; // round up to double-word
|
|
1129
|
|
1130 return nWords * BytesPerWord;
|
|
1131 }
|
|
1132
|
|
1133
|
|
1134 // save_frame: given number of "extra" words in frame,
|
|
1135 // issue approp. save instruction (p 200, v8 manual)
|
|
1136
|
|
1137 void MacroAssembler::save_frame(int extraWords) {
|
|
1138 int delta = -total_frame_size_in_bytes(extraWords);
|
|
1139 if (is_simm13(delta)) {
|
|
1140 save(SP, delta, SP);
|
|
1141 } else {
|
|
1142 set(delta, G3_scratch);
|
|
1143 save(SP, G3_scratch, SP);
|
|
1144 }
|
|
1145 }
|
|
1146
|
|
1147
|
|
1148 void MacroAssembler::save_frame_c1(int size_in_bytes) {
|
|
1149 if (is_simm13(-size_in_bytes)) {
|
|
1150 save(SP, -size_in_bytes, SP);
|
|
1151 } else {
|
|
1152 set(-size_in_bytes, G3_scratch);
|
|
1153 save(SP, G3_scratch, SP);
|
|
1154 }
|
|
1155 }
|
|
1156
|
|
1157
|
|
1158 void MacroAssembler::save_frame_and_mov(int extraWords,
|
|
1159 Register s1, Register d1,
|
|
1160 Register s2, Register d2) {
|
|
1161 assert_not_delayed();
|
|
1162
|
|
1163 // The trick here is to use precisely the same memory word
|
|
1164 // that trap handlers also use to save the register.
|
|
1165 // This word cannot be used for any other purpose, but
|
|
1166 // it works fine to save the register's value, whether or not
|
|
1167 // an interrupt flushes register windows at any given moment!
|
|
1168 Address s1_addr;
|
|
1169 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
|
|
1170 s1_addr = s1->address_in_saved_window();
|
|
1171 st_ptr(s1, s1_addr);
|
|
1172 }
|
|
1173
|
|
1174 Address s2_addr;
|
|
1175 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
|
|
1176 s2_addr = s2->address_in_saved_window();
|
|
1177 st_ptr(s2, s2_addr);
|
|
1178 }
|
|
1179
|
|
1180 save_frame(extraWords);
|
|
1181
|
|
1182 if (s1_addr.base() == SP) {
|
|
1183 ld_ptr(s1_addr.after_save(), d1);
|
|
1184 } else if (s1->is_valid()) {
|
|
1185 mov(s1->after_save(), d1);
|
|
1186 }
|
|
1187
|
|
1188 if (s2_addr.base() == SP) {
|
|
1189 ld_ptr(s2_addr.after_save(), d2);
|
|
1190 } else if (s2->is_valid()) {
|
|
1191 mov(s2->after_save(), d2);
|
|
1192 }
|
|
1193 }
|
|
1194
|
|
1195
|
|
1196 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
|
|
1197 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
|
|
1198 int index = oop_recorder()->allocate_metadata_index(obj);
|
|
1199 RelocationHolder rspec = metadata_Relocation::spec(index);
|
|
1200 return AddressLiteral((address)obj, rspec);
|
|
1201 }
|
|
1202
|
|
1203 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
|
|
1204 assert(oop_recorder() != NULL, "this assembler needs a Recorder");
|
|
1205 int index = oop_recorder()->find_index(obj);
|
|
1206 RelocationHolder rspec = metadata_Relocation::spec(index);
|
|
1207 return AddressLiteral((address)obj, rspec);
|
|
1208 }
|
|
1209
|
|
1210
|
|
1211 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
|
|
1212 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1213 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop");
|
|
1214 int oop_index = oop_recorder()->find_index(obj);
|
|
1215 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
|
|
1216 }
|
|
1217
|
|
1218 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
|
|
1219 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1220 int oop_index = oop_recorder()->find_index(obj);
|
|
1221 RelocationHolder rspec = oop_Relocation::spec(oop_index);
|
|
1222
|
|
1223 assert_not_delayed();
|
|
1224 // Relocation with special format (see relocInfo_sparc.hpp).
|
|
1225 relocate(rspec, 1);
|
|
1226 // Assembler::sethi(0x3fffff, d);
|
|
1227 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
|
|
1228 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
|
|
1229 add(d, 0x3ff, d);
|
|
1230
|
|
1231 }
|
|
1232
|
|
1233 void MacroAssembler::set_narrow_klass(Klass* k, Register d) {
|
|
1234 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
|
1235 int klass_index = oop_recorder()->find_index(k);
|
|
1236 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
|
|
1237 narrowOop encoded_k = oopDesc::encode_klass(k);
|
|
1238
|
|
1239 assert_not_delayed();
|
|
1240 // Relocation with special format (see relocInfo_sparc.hpp).
|
|
1241 relocate(rspec, 1);
|
|
1242 // Assembler::sethi(encoded_k, d);
|
|
1243 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) );
|
|
1244 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
|
|
1245 add(d, low10(encoded_k), d);
|
|
1246
|
|
1247 }
|
|
1248
|
|
1249 void MacroAssembler::align(int modulus) {
|
|
1250 while (offset() % modulus != 0) nop();
|
|
1251 }
|
|
1252
|
|
1253
|
|
1254 void MacroAssembler::safepoint() {
|
|
1255 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
|
|
1256 }
|
|
1257
|
|
1258
|
|
1259 void RegistersForDebugging::print(outputStream* s) {
|
|
1260 FlagSetting fs(Debugging, true);
|
|
1261 int j;
|
|
1262 for (j = 0; j < 8; ++j) {
|
|
1263 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); }
|
|
1264 else { s->print( "fp = " ); os::print_location(s, i[j]); }
|
|
1265 }
|
|
1266 s->cr();
|
|
1267
|
|
1268 for (j = 0; j < 8; ++j) {
|
|
1269 s->print("l%d = ", j); os::print_location(s, l[j]);
|
|
1270 }
|
|
1271 s->cr();
|
|
1272
|
|
1273 for (j = 0; j < 8; ++j) {
|
|
1274 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); }
|
|
1275 else { s->print( "sp = " ); os::print_location(s, o[j]); }
|
|
1276 }
|
|
1277 s->cr();
|
|
1278
|
|
1279 for (j = 0; j < 8; ++j) {
|
|
1280 s->print("g%d = ", j); os::print_location(s, g[j]);
|
|
1281 }
|
|
1282 s->cr();
|
|
1283
|
|
1284 // print out floats with compression
|
|
1285 for (j = 0; j < 32; ) {
|
|
1286 jfloat val = f[j];
|
|
1287 int last = j;
|
|
1288 for ( ; last+1 < 32; ++last ) {
|
|
1289 char b1[1024], b2[1024];
|
|
1290 sprintf(b1, "%f", val);
|
|
1291 sprintf(b2, "%f", f[last+1]);
|
|
1292 if (strcmp(b1, b2))
|
|
1293 break;
|
|
1294 }
|
|
1295 s->print("f%d", j);
|
|
1296 if ( j != last ) s->print(" - f%d", last);
|
|
1297 s->print(" = %f", val);
|
|
1298 s->fill_to(25);
|
|
1299 s->print_cr(" (0x%x)", val);
|
|
1300 j = last + 1;
|
|
1301 }
|
|
1302 s->cr();
|
|
1303
|
|
1304 // and doubles (evens only)
|
|
1305 for (j = 0; j < 32; ) {
|
|
1306 jdouble val = d[j];
|
|
1307 int last = j;
|
|
1308 for ( ; last+1 < 32; ++last ) {
|
|
1309 char b1[1024], b2[1024];
|
|
1310 sprintf(b1, "%f", val);
|
|
1311 sprintf(b2, "%f", d[last+1]);
|
|
1312 if (strcmp(b1, b2))
|
|
1313 break;
|
|
1314 }
|
|
1315 s->print("d%d", 2 * j);
|
|
1316 if ( j != last ) s->print(" - d%d", last);
|
|
1317 s->print(" = %f", val);
|
|
1318 s->fill_to(30);
|
|
1319 s->print("(0x%x)", *(int*)&val);
|
|
1320 s->fill_to(42);
|
|
1321 s->print_cr("(0x%x)", *(1 + (int*)&val));
|
|
1322 j = last + 1;
|
|
1323 }
|
|
1324 s->cr();
|
|
1325 }
|
|
1326
|
|
1327 void RegistersForDebugging::save_registers(MacroAssembler* a) {
|
|
1328 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
|
|
1329 a->flush_windows();
|
|
1330 int i;
|
|
1331 for (i = 0; i < 8; ++i) {
|
|
1332 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
|
|
1333 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
|
|
1334 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
|
|
1335 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
|
|
1336 }
|
|
1337 for (i = 0; i < 32; ++i) {
|
|
1338 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
|
|
1339 }
|
|
1340 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
|
|
1341 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
|
|
1342 }
|
|
1343 }
|
|
1344
|
|
1345 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
|
|
1346 for (int i = 1; i < 8; ++i) {
|
|
1347 a->ld_ptr(r, g_offset(i), as_gRegister(i));
|
|
1348 }
|
|
1349 for (int j = 0; j < 32; ++j) {
|
|
1350 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
|
|
1351 }
|
|
1352 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
|
|
1353 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
|
|
1354 }
|
|
1355 }
|
|
1356
|
|
1357
|
|
1358 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
|
|
1359 void MacroAssembler::push_fTOS() {
|
|
1360 // %%%%%% need to implement this
|
|
1361 }
|
|
1362
|
|
1363 // pops double TOS element from CPU stack and pushes on FPU stack
|
|
1364 void MacroAssembler::pop_fTOS() {
|
|
1365 // %%%%%% need to implement this
|
|
1366 }
|
|
1367
|
|
1368 void MacroAssembler::empty_FPU_stack() {
|
|
1369 // %%%%%% need to implement this
|
|
1370 }
|
|
1371
|
|
1372 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
|
|
1373 // plausibility check for oops
|
|
1374 if (!VerifyOops) return;
|
|
1375
|
|
1376 if (reg == G0) return; // always NULL, which is always an oop
|
|
1377
|
|
1378 BLOCK_COMMENT("verify_oop {");
|
|
1379 char buffer[64];
|
|
1380 #ifdef COMPILER1
|
|
1381 if (CommentedAssembly) {
|
|
1382 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
|
|
1383 block_comment(buffer);
|
|
1384 }
|
|
1385 #endif
|
|
1386
|
|
1387 int len = strlen(file) + strlen(msg) + 1 + 4;
|
|
1388 sprintf(buffer, "%d", line);
|
|
1389 len += strlen(buffer);
|
|
1390 sprintf(buffer, " at offset %d ", offset());
|
|
1391 len += strlen(buffer);
|
|
1392 char * real_msg = new char[len];
|
|
1393 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
|
|
1394
|
|
1395 // Call indirectly to solve generation ordering problem
|
|
1396 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
|
|
1397
|
|
1398 // Make some space on stack above the current register window.
|
|
1399 // Enough to hold 8 64-bit registers.
|
|
1400 add(SP,-8*8,SP);
|
|
1401
|
|
1402 // Save some 64-bit registers; a normal 'save' chops the heads off
|
|
1403 // of 64-bit longs in the 32-bit build.
|
|
1404 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
|
|
1405 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
|
|
1406 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
|
|
1407 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
|
|
1408
|
|
1409 // Size of set() should stay the same
|
|
1410 patchable_set((intptr_t)real_msg, O1);
|
|
1411 // Load address to call to into O7
|
|
1412 load_ptr_contents(a, O7);
|
|
1413 // Register call to verify_oop_subroutine
|
|
1414 callr(O7, G0);
|
|
1415 delayed()->nop();
|
|
1416 // recover frame size
|
|
1417 add(SP, 8*8,SP);
|
|
1418 BLOCK_COMMENT("} verify_oop");
|
|
1419 }
|
|
1420
|
|
1421 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
|
|
1422 // plausibility check for oops
|
|
1423 if (!VerifyOops) return;
|
|
1424
|
|
1425 char buffer[64];
|
|
1426 sprintf(buffer, "%d", line);
|
|
1427 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
|
|
1428 sprintf(buffer, " at SP+%d ", addr.disp());
|
|
1429 len += strlen(buffer);
|
|
1430 char * real_msg = new char[len];
|
|
1431 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
|
|
1432
|
|
1433 // Call indirectly to solve generation ordering problem
|
|
1434 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
|
|
1435
|
|
1436 // Make some space on stack above the current register window.
|
|
1437 // Enough to hold 8 64-bit registers.
|
|
1438 add(SP,-8*8,SP);
|
|
1439
|
|
1440 // Save some 64-bit registers; a normal 'save' chops the heads off
|
|
1441 // of 64-bit longs in the 32-bit build.
|
|
1442 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
|
|
1443 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
|
|
1444 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
|
|
1445 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
|
|
1446
|
|
1447 // Size of set() should stay the same
|
|
1448 patchable_set((intptr_t)real_msg, O1);
|
|
1449 // Load address to call to into O7
|
|
1450 load_ptr_contents(a, O7);
|
|
1451 // Register call to verify_oop_subroutine
|
|
1452 callr(O7, G0);
|
|
1453 delayed()->nop();
|
|
1454 // recover frame size
|
|
1455 add(SP, 8*8,SP);
|
|
1456 }
|
|
1457
|
|
1458 // side-door communication with signalHandler in os_solaris.cpp
|
|
1459 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
|
|
1460
|
|
1461 // This macro is expanded just once; it creates shared code. Contract:
|
|
1462 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
|
|
1463 // registers, including flags. May not use a register 'save', as this blows
|
|
1464 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
|
|
1465 // call.
|
|
1466 void MacroAssembler::verify_oop_subroutine() {
|
|
1467 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
|
|
1468
|
|
1469 // Leaf call; no frame.
|
|
1470 Label succeed, fail, null_or_fail;
|
|
1471
|
|
1472 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
|
|
1473 // O0 is now the oop to be checked. O7 is the return address.
|
|
1474 Register O0_obj = O0;
|
|
1475
|
|
1476 // Save some more registers for temps.
|
|
1477 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
|
|
1478 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
|
|
1479 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
|
|
1480 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
|
|
1481
|
|
1482 // Save flags
|
|
1483 Register O5_save_flags = O5;
|
|
1484 rdccr( O5_save_flags );
|
|
1485
|
|
1486 { // count number of verifies
|
|
1487 Register O2_adr = O2;
|
|
1488 Register O3_accum = O3;
|
|
1489 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
|
|
1490 }
|
|
1491
|
|
1492 Register O2_mask = O2;
|
|
1493 Register O3_bits = O3;
|
|
1494 Register O4_temp = O4;
|
|
1495
|
|
1496 // mark lower end of faulting range
|
|
1497 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
|
|
1498 _verify_oop_implicit_branch[0] = pc();
|
|
1499
|
|
1500 // We can't check the mark oop because it could be in the process of
|
|
1501 // locking or unlocking while this is running.
|
|
1502 set(Universe::verify_oop_mask (), O2_mask);
|
|
1503 set(Universe::verify_oop_bits (), O3_bits);
|
|
1504
|
|
1505 // assert((obj & oop_mask) == oop_bits);
|
|
1506 and3(O0_obj, O2_mask, O4_temp);
|
|
1507 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail);
|
|
1508
|
|
1509 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
|
|
1510 // the null_or_fail case is useless; must test for null separately
|
|
1511 br_null_short(O0_obj, pn, succeed);
|
|
1512 }
|
|
1513
|
|
1514 // Check the Klass* of this object for being in the right area of memory.
|
|
1515 // Cannot do the load in the delay above slot in case O0 is null
|
|
1516 load_klass(O0_obj, O0_obj);
|
|
1517 // assert((klass != NULL)
|
|
1518 br_null_short(O0_obj, pn, fail);
|
|
1519 // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers
|
|
1520
|
|
1521 wrccr( O5_save_flags ); // Restore CCR's
|
|
1522
|
|
1523 // mark upper end of faulting range
|
|
1524 _verify_oop_implicit_branch[1] = pc();
|
|
1525
|
|
1526 //-----------------------
|
|
1527 // all tests pass
|
|
1528 bind(succeed);
|
|
1529
|
|
1530 // Restore prior 64-bit registers
|
|
1531 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
|
|
1532 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
|
|
1533 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
|
|
1534 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
|
|
1535 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
|
|
1536 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
|
|
1537
|
|
1538 retl(); // Leaf return; restore prior O7 in delay slot
|
|
1539 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
|
|
1540
|
|
1541 //-----------------------
|
|
1542 bind(null_or_fail); // nulls are less common but OK
|
|
1543 br_null(O0_obj, false, pt, succeed);
|
|
1544 delayed()->wrccr( O5_save_flags ); // Restore CCR's
|
|
1545
|
|
1546 //-----------------------
|
|
1547 // report failure:
|
|
1548 bind(fail);
|
|
1549 _verify_oop_implicit_branch[2] = pc();
|
|
1550
|
|
1551 wrccr( O5_save_flags ); // Restore CCR's
|
|
1552
|
|
1553 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1554
|
|
1555 // stop_subroutine expects message pointer in I1.
|
|
1556 mov(I1, O1);
|
|
1557
|
|
1558 // Restore prior 64-bit registers
|
|
1559 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
|
|
1560 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
|
|
1561 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
|
|
1562 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
|
|
1563 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
|
|
1564 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
|
|
1565
|
|
1566 // factor long stop-sequence into subroutine to save space
|
|
1567 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
|
|
1568
|
|
1569 // call indirectly to solve generation ordering problem
|
|
1570 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
|
|
1571 load_ptr_contents(al, O5);
|
|
1572 jmpl(O5, 0, O7);
|
|
1573 delayed()->nop();
|
|
1574 }
|
|
1575
|
|
1576
|
|
1577 void MacroAssembler::stop(const char* msg) {
|
|
1578 // save frame first to get O7 for return address
|
|
1579 // add one word to size in case struct is odd number of words long
|
|
1580 // It must be doubleword-aligned for storing doubles into it.
|
|
1581
|
|
1582 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1583
|
|
1584 // stop_subroutine expects message pointer in I1.
|
|
1585 // Size of set() should stay the same
|
|
1586 patchable_set((intptr_t)msg, O1);
|
|
1587
|
|
1588 // factor long stop-sequence into subroutine to save space
|
|
1589 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
|
|
1590
|
|
1591 // call indirectly to solve generation ordering problem
|
|
1592 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
|
|
1593 load_ptr_contents(a, O5);
|
|
1594 jmpl(O5, 0, O7);
|
|
1595 delayed()->nop();
|
|
1596
|
|
1597 breakpoint_trap(); // make stop actually stop rather than writing
|
|
1598 // unnoticeable results in the output files.
|
|
1599
|
|
1600 // restore(); done in callee to save space!
|
|
1601 }
|
|
1602
|
|
1603
|
|
1604 void MacroAssembler::warn(const char* msg) {
|
|
1605 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
|
|
1606 RegistersForDebugging::save_registers(this);
|
|
1607 mov(O0, L0);
|
|
1608 // Size of set() should stay the same
|
|
1609 patchable_set((intptr_t)msg, O0);
|
|
1610 call( CAST_FROM_FN_PTR(address, warning) );
|
|
1611 delayed()->nop();
|
|
1612 // ret();
|
|
1613 // delayed()->restore();
|
|
1614 RegistersForDebugging::restore_registers(this, L0);
|
|
1615 restore();
|
|
1616 }
|
|
1617
|
|
1618
|
|
1619 void MacroAssembler::untested(const char* what) {
|
|
1620 // We must be able to turn interactive prompting off
|
|
1621 // in order to run automated test scripts on the VM
|
|
1622 // Use the flag ShowMessageBoxOnError
|
|
1623
|
|
1624 char* b = new char[1024];
|
|
1625 sprintf(b, "untested: %s", what);
|
|
1626
|
|
1627 if (ShowMessageBoxOnError) { STOP(b); }
|
|
1628 else { warn(b); }
|
|
1629 }
|
|
1630
|
|
1631
|
|
1632 void MacroAssembler::stop_subroutine() {
|
|
1633 RegistersForDebugging::save_registers(this);
|
|
1634
|
|
1635 // for the sake of the debugger, stick a PC on the current frame
|
|
1636 // (this assumes that the caller has performed an extra "save")
|
|
1637 mov(I7, L7);
|
|
1638 add(O7, -7 * BytesPerInt, I7);
|
|
1639
|
|
1640 save_frame(); // one more save to free up another O7 register
|
|
1641 mov(I0, O1); // addr of reg save area
|
|
1642
|
|
1643 // We expect pointer to message in I1. Caller must set it up in O1
|
|
1644 mov(I1, O0); // get msg
|
|
1645 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
|
|
1646 delayed()->nop();
|
|
1647
|
|
1648 restore();
|
|
1649
|
|
1650 RegistersForDebugging::restore_registers(this, O0);
|
|
1651
|
|
1652 save_frame(0);
|
|
1653 call(CAST_FROM_FN_PTR(address,breakpoint));
|
|
1654 delayed()->nop();
|
|
1655 restore();
|
|
1656
|
|
1657 mov(L7, I7);
|
|
1658 retl();
|
|
1659 delayed()->restore(); // see stop above
|
|
1660 }
|
|
1661
|
|
1662
|
|
1663 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
|
|
1664 if ( ShowMessageBoxOnError ) {
|
|
1665 JavaThread* thread = JavaThread::current();
|
|
1666 JavaThreadState saved_state = thread->thread_state();
|
|
1667 thread->set_thread_state(_thread_in_vm);
|
|
1668 {
|
|
1669 // In order to get locks work, we need to fake a in_VM state
|
|
1670 ttyLocker ttyl;
|
|
1671 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
|
|
1672 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
|
|
1673 BytecodeCounter::print();
|
|
1674 }
|
|
1675 if (os::message_box(msg, "Execution stopped, print registers?"))
|
|
1676 regs->print(::tty);
|
|
1677 }
|
|
1678 BREAKPOINT;
|
|
1679 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
|
|
1680 }
|
|
1681 else {
|
|
1682 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
|
|
1683 }
|
|
1684 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
|
|
1685 }
|
|
1686
|
|
1687
|
|
1688 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
|
|
1689 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
|
|
1690 Label no_extras;
|
|
1691 br( negative, true, pt, no_extras ); // if neg, clear reg
|
|
1692 delayed()->set(0, Rresult); // annuled, so only if taken
|
|
1693 bind( no_extras );
|
|
1694 }
|
|
1695
|
|
1696
|
|
1697 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
|
|
1698 #ifdef _LP64
|
|
1699 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
|
|
1700 #else
|
|
1701 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
|
|
1702 #endif
|
|
1703 bclr(1, Rresult);
|
|
1704 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
|
|
1705 }
|
|
1706
|
|
1707
|
|
1708 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
|
|
1709 calc_frame_size(Rextra_words, Rresult);
|
|
1710 neg(Rresult);
|
|
1711 save(SP, Rresult, SP);
|
|
1712 }
|
|
1713
|
|
1714
|
|
1715 // ---------------------------------------------------------
|
|
1716 Assembler::RCondition cond2rcond(Assembler::Condition c) {
|
|
1717 switch (c) {
|
|
1718 /*case zero: */
|
|
1719 case Assembler::equal: return Assembler::rc_z;
|
|
1720 case Assembler::lessEqual: return Assembler::rc_lez;
|
|
1721 case Assembler::less: return Assembler::rc_lz;
|
|
1722 /*case notZero:*/
|
|
1723 case Assembler::notEqual: return Assembler::rc_nz;
|
|
1724 case Assembler::greater: return Assembler::rc_gz;
|
|
1725 case Assembler::greaterEqual: return Assembler::rc_gez;
|
|
1726 }
|
|
1727 ShouldNotReachHere();
|
|
1728 return Assembler::rc_z;
|
|
1729 }
|
|
1730
|
|
1731 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
|
|
1732 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) {
|
|
1733 tst(s1);
|
|
1734 br (c, a, p, L);
|
|
1735 }
|
|
1736
|
|
1737 // Compares a pointer register with zero and branches on null.
|
|
1738 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
|
|
1739 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
|
|
1740 assert_not_delayed();
|
|
1741 #ifdef _LP64
|
|
1742 bpr( rc_z, a, p, s1, L );
|
|
1743 #else
|
|
1744 tst(s1);
|
|
1745 br ( zero, a, p, L );
|
|
1746 #endif
|
|
1747 }
|
|
1748
|
|
1749 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
|
|
1750 assert_not_delayed();
|
|
1751 #ifdef _LP64
|
|
1752 bpr( rc_nz, a, p, s1, L );
|
|
1753 #else
|
|
1754 tst(s1);
|
|
1755 br ( notZero, a, p, L );
|
|
1756 #endif
|
|
1757 }
|
|
1758
|
|
1759 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
|
|
1760
|
|
1761 // Compare integer (32 bit) values (icc only).
|
|
1762 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c,
|
|
1763 Predict p, Label& L) {
|
|
1764 assert_not_delayed();
|
|
1765 if (use_cbcond(L)) {
|
|
1766 Assembler::cbcond(c, icc, s1, s2, L);
|
|
1767 } else {
|
|
1768 cmp(s1, s2);
|
|
1769 br(c, false, p, L);
|
|
1770 delayed()->nop();
|
|
1771 }
|
|
1772 }
|
|
1773
|
|
1774 // Compare integer (32 bit) values (icc only).
|
|
1775 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c,
|
|
1776 Predict p, Label& L) {
|
|
1777 assert_not_delayed();
|
|
1778 if (is_simm(simm13a,5) && use_cbcond(L)) {
|
|
1779 Assembler::cbcond(c, icc, s1, simm13a, L);
|
|
1780 } else {
|
|
1781 cmp(s1, simm13a);
|
|
1782 br(c, false, p, L);
|
|
1783 delayed()->nop();
|
|
1784 }
|
|
1785 }
|
|
1786
|
|
1787 // Branch that tests xcc in LP64 and icc in !LP64
|
|
1788 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c,
|
|
1789 Predict p, Label& L) {
|
|
1790 assert_not_delayed();
|
|
1791 if (use_cbcond(L)) {
|
|
1792 Assembler::cbcond(c, ptr_cc, s1, s2, L);
|
|
1793 } else {
|
|
1794 cmp(s1, s2);
|
|
1795 brx(c, false, p, L);
|
|
1796 delayed()->nop();
|
|
1797 }
|
|
1798 }
|
|
1799
|
|
1800 // Branch that tests xcc in LP64 and icc in !LP64
|
|
1801 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c,
|
|
1802 Predict p, Label& L) {
|
|
1803 assert_not_delayed();
|
|
1804 if (is_simm(simm13a,5) && use_cbcond(L)) {
|
|
1805 Assembler::cbcond(c, ptr_cc, s1, simm13a, L);
|
|
1806 } else {
|
|
1807 cmp(s1, simm13a);
|
|
1808 brx(c, false, p, L);
|
|
1809 delayed()->nop();
|
|
1810 }
|
|
1811 }
|
|
1812
|
|
1813 // Short branch version for compares a pointer with zero.
|
|
1814
|
|
1815 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) {
|
|
1816 assert_not_delayed();
|
|
1817 if (use_cbcond(L)) {
|
|
1818 Assembler::cbcond(zero, ptr_cc, s1, 0, L);
|
|
1819 return;
|
|
1820 }
|
|
1821 br_null(s1, false, p, L);
|
|
1822 delayed()->nop();
|
|
1823 }
|
|
1824
|
|
1825 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) {
|
|
1826 assert_not_delayed();
|
|
1827 if (use_cbcond(L)) {
|
|
1828 Assembler::cbcond(notZero, ptr_cc, s1, 0, L);
|
|
1829 return;
|
|
1830 }
|
|
1831 br_notnull(s1, false, p, L);
|
|
1832 delayed()->nop();
|
|
1833 }
|
|
1834
|
|
1835 // Unconditional short branch
|
|
1836 void MacroAssembler::ba_short(Label& L) {
|
|
1837 if (use_cbcond(L)) {
|
|
1838 Assembler::cbcond(equal, icc, G0, G0, L);
|
|
1839 return;
|
|
1840 }
|
|
1841 br(always, false, pt, L);
|
|
1842 delayed()->nop();
|
|
1843 }
|
|
1844
|
|
1845 // instruction sequences factored across compiler & interpreter
|
|
1846
|
|
1847
|
|
1848 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
|
|
1849 Register Rb_hi, Register Rb_low,
|
|
1850 Register Rresult) {
|
|
1851
|
|
1852 Label check_low_parts, done;
|
|
1853
|
|
1854 cmp(Ra_hi, Rb_hi ); // compare hi parts
|
|
1855 br(equal, true, pt, check_low_parts);
|
|
1856 delayed()->cmp(Ra_low, Rb_low); // test low parts
|
|
1857
|
|
1858 // And, with an unsigned comparison, it does not matter if the numbers
|
|
1859 // are negative or not.
|
|
1860 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
|
|
1861 // The second one is bigger (unsignedly).
|
|
1862
|
|
1863 // Other notes: The first move in each triplet can be unconditional
|
|
1864 // (and therefore probably prefetchable).
|
|
1865 // And the equals case for the high part does not need testing,
|
|
1866 // since that triplet is reached only after finding the high halves differ.
|
|
1867
|
|
1868 if (VM_Version::v9_instructions_work()) {
|
|
1869 mov(-1, Rresult);
|
|
1870 ba(done); delayed()-> movcc(greater, false, icc, 1, Rresult);
|
|
1871 } else {
|
|
1872 br(less, true, pt, done); delayed()-> set(-1, Rresult);
|
|
1873 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
|
|
1874 }
|
|
1875
|
|
1876 bind( check_low_parts );
|
|
1877
|
|
1878 if (VM_Version::v9_instructions_work()) {
|
|
1879 mov( -1, Rresult);
|
|
1880 movcc(equal, false, icc, 0, Rresult);
|
|
1881 movcc(greaterUnsigned, false, icc, 1, Rresult);
|
|
1882 } else {
|
|
1883 set(-1, Rresult);
|
|
1884 br(equal, true, pt, done); delayed()->set( 0, Rresult);
|
|
1885 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
|
|
1886 }
|
|
1887 bind( done );
|
|
1888 }
|
|
1889
|
|
1890 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
|
|
1891 subcc( G0, Rlow, Rlow );
|
|
1892 subc( G0, Rhi, Rhi );
|
|
1893 }
|
|
1894
|
|
1895 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
|
|
1896 Register Rcount,
|
|
1897 Register Rout_high, Register Rout_low,
|
|
1898 Register Rtemp ) {
|
|
1899
|
|
1900
|
|
1901 Register Ralt_count = Rtemp;
|
|
1902 Register Rxfer_bits = Rtemp;
|
|
1903
|
|
1904 assert( Ralt_count != Rin_high
|
|
1905 && Ralt_count != Rin_low
|
|
1906 && Ralt_count != Rcount
|
|
1907 && Rxfer_bits != Rin_low
|
|
1908 && Rxfer_bits != Rin_high
|
|
1909 && Rxfer_bits != Rcount
|
|
1910 && Rxfer_bits != Rout_low
|
|
1911 && Rout_low != Rin_high,
|
|
1912 "register alias checks");
|
|
1913
|
|
1914 Label big_shift, done;
|
|
1915
|
|
1916 // This code can be optimized to use the 64 bit shifts in V9.
|
|
1917 // Here we use the 32 bit shifts.
|
|
1918
|
|
1919 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
1920 subcc(Rcount, 31, Ralt_count);
|
|
1921 br(greater, true, pn, big_shift);
|
|
1922 delayed()->dec(Ralt_count);
|
|
1923
|
|
1924 // shift < 32 bits, Ralt_count = Rcount-31
|
|
1925
|
|
1926 // We get the transfer bits by shifting right by 32-count the low
|
|
1927 // register. This is done by shifting right by 31-count and then by one
|
|
1928 // more to take care of the special (rare) case where count is zero
|
|
1929 // (shifting by 32 would not work).
|
|
1930
|
|
1931 neg(Ralt_count);
|
|
1932
|
|
1933 // The order of the next two instructions is critical in the case where
|
|
1934 // Rin and Rout are the same and should not be reversed.
|
|
1935
|
|
1936 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count
|
|
1937 if (Rcount != Rout_low) {
|
|
1938 sll(Rin_low, Rcount, Rout_low); // low half
|
|
1939 }
|
|
1940 sll(Rin_high, Rcount, Rout_high);
|
|
1941 if (Rcount == Rout_low) {
|
|
1942 sll(Rin_low, Rcount, Rout_low); // low half
|
|
1943 }
|
|
1944 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
|
|
1945 ba(done);
|
|
1946 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
|
|
1947
|
|
1948 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
1949 bind(big_shift);
|
|
1950 sll(Rin_low, Ralt_count, Rout_high );
|
|
1951 clr(Rout_low);
|
|
1952
|
|
1953 bind(done);
|
|
1954 }
|
|
1955
|
|
1956
|
|
1957 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
|
|
1958 Register Rcount,
|
|
1959 Register Rout_high, Register Rout_low,
|
|
1960 Register Rtemp ) {
|
|
1961
|
|
1962 Register Ralt_count = Rtemp;
|
|
1963 Register Rxfer_bits = Rtemp;
|
|
1964
|
|
1965 assert( Ralt_count != Rin_high
|
|
1966 && Ralt_count != Rin_low
|
|
1967 && Ralt_count != Rcount
|
|
1968 && Rxfer_bits != Rin_low
|
|
1969 && Rxfer_bits != Rin_high
|
|
1970 && Rxfer_bits != Rcount
|
|
1971 && Rxfer_bits != Rout_high
|
|
1972 && Rout_high != Rin_low,
|
|
1973 "register alias checks");
|
|
1974
|
|
1975 Label big_shift, done;
|
|
1976
|
|
1977 // This code can be optimized to use the 64 bit shifts in V9.
|
|
1978 // Here we use the 32 bit shifts.
|
|
1979
|
|
1980 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
1981 subcc(Rcount, 31, Ralt_count);
|
|
1982 br(greater, true, pn, big_shift);
|
|
1983 delayed()->dec(Ralt_count);
|
|
1984
|
|
1985 // shift < 32 bits, Ralt_count = Rcount-31
|
|
1986
|
|
1987 // We get the transfer bits by shifting left by 32-count the high
|
|
1988 // register. This is done by shifting left by 31-count and then by one
|
|
1989 // more to take care of the special (rare) case where count is zero
|
|
1990 // (shifting by 32 would not work).
|
|
1991
|
|
1992 neg(Ralt_count);
|
|
1993 if (Rcount != Rout_low) {
|
|
1994 srl(Rin_low, Rcount, Rout_low);
|
|
1995 }
|
|
1996
|
|
1997 // The order of the next two instructions is critical in the case where
|
|
1998 // Rin and Rout are the same and should not be reversed.
|
|
1999
|
|
2000 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
|
|
2001 sra(Rin_high, Rcount, Rout_high ); // high half
|
|
2002 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
|
|
2003 if (Rcount == Rout_low) {
|
|
2004 srl(Rin_low, Rcount, Rout_low);
|
|
2005 }
|
|
2006 ba(done);
|
|
2007 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
|
|
2008
|
|
2009 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
2010 bind(big_shift);
|
|
2011
|
|
2012 sra(Rin_high, Ralt_count, Rout_low);
|
|
2013 sra(Rin_high, 31, Rout_high); // sign into hi
|
|
2014
|
|
2015 bind( done );
|
|
2016 }
|
|
2017
|
|
2018
|
|
2019
|
|
2020 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
|
|
2021 Register Rcount,
|
|
2022 Register Rout_high, Register Rout_low,
|
|
2023 Register Rtemp ) {
|
|
2024
|
|
2025 Register Ralt_count = Rtemp;
|
|
2026 Register Rxfer_bits = Rtemp;
|
|
2027
|
|
2028 assert( Ralt_count != Rin_high
|
|
2029 && Ralt_count != Rin_low
|
|
2030 && Ralt_count != Rcount
|
|
2031 && Rxfer_bits != Rin_low
|
|
2032 && Rxfer_bits != Rin_high
|
|
2033 && Rxfer_bits != Rcount
|
|
2034 && Rxfer_bits != Rout_high
|
|
2035 && Rout_high != Rin_low,
|
|
2036 "register alias checks");
|
|
2037
|
|
2038 Label big_shift, done;
|
|
2039
|
|
2040 // This code can be optimized to use the 64 bit shifts in V9.
|
|
2041 // Here we use the 32 bit shifts.
|
|
2042
|
|
2043 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
|
|
2044 subcc(Rcount, 31, Ralt_count);
|
|
2045 br(greater, true, pn, big_shift);
|
|
2046 delayed()->dec(Ralt_count);
|
|
2047
|
|
2048 // shift < 32 bits, Ralt_count = Rcount-31
|
|
2049
|
|
2050 // We get the transfer bits by shifting left by 32-count the high
|
|
2051 // register. This is done by shifting left by 31-count and then by one
|
|
2052 // more to take care of the special (rare) case where count is zero
|
|
2053 // (shifting by 32 would not work).
|
|
2054
|
|
2055 neg(Ralt_count);
|
|
2056 if (Rcount != Rout_low) {
|
|
2057 srl(Rin_low, Rcount, Rout_low);
|
|
2058 }
|
|
2059
|
|
2060 // The order of the next two instructions is critical in the case where
|
|
2061 // Rin and Rout are the same and should not be reversed.
|
|
2062
|
|
2063 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count
|
|
2064 srl(Rin_high, Rcount, Rout_high ); // high half
|
|
2065 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more
|
|
2066 if (Rcount == Rout_low) {
|
|
2067 srl(Rin_low, Rcount, Rout_low);
|
|
2068 }
|
|
2069 ba(done);
|
|
2070 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high
|
|
2071
|
|
2072 // shift >= 32 bits, Ralt_count = Rcount-32
|
|
2073 bind(big_shift);
|
|
2074
|
|
2075 srl(Rin_high, Ralt_count, Rout_low);
|
|
2076 clr(Rout_high);
|
|
2077
|
|
2078 bind( done );
|
|
2079 }
|
|
2080
|
|
2081 #ifdef _LP64
|
|
2082 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
|
|
2083 cmp(Ra, Rb);
|
|
2084 mov(-1, Rresult);
|
|
2085 movcc(equal, false, xcc, 0, Rresult);
|
|
2086 movcc(greater, false, xcc, 1, Rresult);
|
|
2087 }
|
|
2088 #endif
|
|
2089
|
|
2090
|
|
2091 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) {
|
|
2092 switch (size_in_bytes) {
|
|
2093 case 8: ld_long(src, dst); break;
|
|
2094 case 4: ld( src, dst); break;
|
|
2095 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break;
|
|
2096 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break;
|
|
2097 default: ShouldNotReachHere();
|
|
2098 }
|
|
2099 }
|
|
2100
|
|
2101 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
|
|
2102 switch (size_in_bytes) {
|
|
2103 case 8: st_long(src, dst); break;
|
|
2104 case 4: st( src, dst); break;
|
|
2105 case 2: sth( src, dst); break;
|
|
2106 case 1: stb( src, dst); break;
|
|
2107 default: ShouldNotReachHere();
|
|
2108 }
|
|
2109 }
|
|
2110
|
|
2111
|
|
2112 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
|
|
2113 FloatRegister Fa, FloatRegister Fb,
|
|
2114 Register Rresult) {
|
|
2115
|
|
2116 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
|
|
2117
|
|
2118 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
|
|
2119 Condition eq = f_equal;
|
|
2120 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
|
|
2121
|
|
2122 if (VM_Version::v9_instructions_work()) {
|
|
2123
|
|
2124 mov(-1, Rresult);
|
|
2125 movcc(eq, true, fcc0, 0, Rresult);
|
|
2126 movcc(gt, true, fcc0, 1, Rresult);
|
|
2127
|
|
2128 } else {
|
|
2129 Label done;
|
|
2130
|
|
2131 set( -1, Rresult );
|
|
2132 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
|
|
2133 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
|
|
2134 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
|
|
2135
|
|
2136 bind (done);
|
|
2137 }
|
|
2138 }
|
|
2139
|
|
2140
|
|
2141 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2142 {
|
|
2143 if (VM_Version::v9_instructions_work()) {
|
|
2144 Assembler::fneg(w, s, d);
|
|
2145 } else {
|
|
2146 if (w == FloatRegisterImpl::S) {
|
|
2147 Assembler::fneg(w, s, d);
|
|
2148 } else if (w == FloatRegisterImpl::D) {
|
|
2149 // number() does a sanity check on the alignment.
|
|
2150 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2151 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2152
|
|
2153 Assembler::fneg(FloatRegisterImpl::S, s, d);
|
|
2154 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2155 } else {
|
|
2156 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2157
|
|
2158 // number() does a sanity check on the alignment.
|
|
2159 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2160 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2161
|
|
2162 Assembler::fneg(FloatRegisterImpl::S, s, d);
|
|
2163 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2164 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2165 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2166 }
|
|
2167 }
|
|
2168 }
|
|
2169
|
|
2170 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2171 {
|
|
2172 if (VM_Version::v9_instructions_work()) {
|
|
2173 Assembler::fmov(w, s, d);
|
|
2174 } else {
|
|
2175 if (w == FloatRegisterImpl::S) {
|
|
2176 Assembler::fmov(w, s, d);
|
|
2177 } else if (w == FloatRegisterImpl::D) {
|
|
2178 // number() does a sanity check on the alignment.
|
|
2179 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2180 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2181
|
|
2182 Assembler::fmov(FloatRegisterImpl::S, s, d);
|
|
2183 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2184 } else {
|
|
2185 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2186
|
|
2187 // number() does a sanity check on the alignment.
|
|
2188 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2189 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2190
|
|
2191 Assembler::fmov(FloatRegisterImpl::S, s, d);
|
|
2192 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2193 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2194 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2195 }
|
|
2196 }
|
|
2197 }
|
|
2198
|
|
2199 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
|
|
2200 {
|
|
2201 if (VM_Version::v9_instructions_work()) {
|
|
2202 Assembler::fabs(w, s, d);
|
|
2203 } else {
|
|
2204 if (w == FloatRegisterImpl::S) {
|
|
2205 Assembler::fabs(w, s, d);
|
|
2206 } else if (w == FloatRegisterImpl::D) {
|
|
2207 // number() does a sanity check on the alignment.
|
|
2208 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
|
|
2209 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
|
|
2210
|
|
2211 Assembler::fabs(FloatRegisterImpl::S, s, d);
|
|
2212 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2213 } else {
|
|
2214 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
|
|
2215
|
|
2216 // number() does a sanity check on the alignment.
|
|
2217 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
|
|
2218 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
|
|
2219
|
|
2220 Assembler::fabs(FloatRegisterImpl::S, s, d);
|
|
2221 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
|
|
2222 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
|
|
2223 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
|
|
2224 }
|
|
2225 }
|
|
2226 }
|
|
2227
|
|
2228 void MacroAssembler::save_all_globals_into_locals() {
|
|
2229 mov(G1,L1);
|
|
2230 mov(G2,L2);
|
|
2231 mov(G3,L3);
|
|
2232 mov(G4,L4);
|
|
2233 mov(G5,L5);
|
|
2234 mov(G6,L6);
|
|
2235 mov(G7,L7);
|
|
2236 }
|
|
2237
|
|
2238 void MacroAssembler::restore_globals_from_locals() {
|
|
2239 mov(L1,G1);
|
|
2240 mov(L2,G2);
|
|
2241 mov(L3,G3);
|
|
2242 mov(L4,G4);
|
|
2243 mov(L5,G5);
|
|
2244 mov(L6,G6);
|
|
2245 mov(L7,G7);
|
|
2246 }
|
|
2247
|
|
2248 // Use for 64 bit operation.
|
|
2249 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
|
|
2250 {
|
|
2251 // store ptr_reg as the new top value
|
|
2252 #ifdef _LP64
|
|
2253 casx(top_ptr_reg, top_reg, ptr_reg);
|
|
2254 #else
|
|
2255 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
|
|
2256 #endif // _LP64
|
|
2257 }
|
|
2258
|
|
2259 // [RGV] This routine does not handle 64 bit operations.
|
|
2260 // use casx_under_lock() or casx directly!!!
|
|
2261 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
|
|
2262 {
|
|
2263 // store ptr_reg as the new top value
|
|
2264 if (VM_Version::v9_instructions_work()) {
|
|
2265 cas(top_ptr_reg, top_reg, ptr_reg);
|
|
2266 } else {
|
|
2267
|
|
2268 // If the register is not an out nor global, it is not visible
|
|
2269 // after the save. Allocate a register for it, save its
|
|
2270 // value in the register save area (the save may not flush
|
|
2271 // registers to the save area).
|
|
2272
|
|
2273 Register top_ptr_reg_after_save;
|
|
2274 Register top_reg_after_save;
|
|
2275 Register ptr_reg_after_save;
|
|
2276
|
|
2277 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
|
|
2278 top_ptr_reg_after_save = top_ptr_reg->after_save();
|
|
2279 } else {
|
|
2280 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
|
|
2281 top_ptr_reg_after_save = L0;
|
|
2282 st(top_ptr_reg, reg_save_addr);
|
|
2283 }
|
|
2284
|
|
2285 if (top_reg->is_out() || top_reg->is_global()) {
|
|
2286 top_reg_after_save = top_reg->after_save();
|
|
2287 } else {
|
|
2288 Address reg_save_addr = top_reg->address_in_saved_window();
|
|
2289 top_reg_after_save = L1;
|
|
2290 st(top_reg, reg_save_addr);
|
|
2291 }
|
|
2292
|
|
2293 if (ptr_reg->is_out() || ptr_reg->is_global()) {
|
|
2294 ptr_reg_after_save = ptr_reg->after_save();
|
|
2295 } else {
|
|
2296 Address reg_save_addr = ptr_reg->address_in_saved_window();
|
|
2297 ptr_reg_after_save = L2;
|
|
2298 st(ptr_reg, reg_save_addr);
|
|
2299 }
|
|
2300
|
|
2301 const Register& lock_reg = L3;
|
|
2302 const Register& lock_ptr_reg = L4;
|
|
2303 const Register& value_reg = L5;
|
|
2304 const Register& yield_reg = L6;
|
|
2305 const Register& yieldall_reg = L7;
|
|
2306
|
|
2307 save_frame();
|
|
2308
|
|
2309 if (top_ptr_reg_after_save == L0) {
|
|
2310 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
|
|
2311 }
|
|
2312
|
|
2313 if (top_reg_after_save == L1) {
|
|
2314 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
|
|
2315 }
|
|
2316
|
|
2317 if (ptr_reg_after_save == L2) {
|
|
2318 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
|
|
2319 }
|
|
2320
|
|
2321 Label(retry_get_lock);
|
|
2322 Label(not_same);
|
|
2323 Label(dont_yield);
|
|
2324
|
|
2325 assert(lock_addr, "lock_address should be non null for v8");
|
|
2326 set((intptr_t)lock_addr, lock_ptr_reg);
|
|
2327 // Initialize yield counter
|
|
2328 mov(G0,yield_reg);
|
|
2329 mov(G0, yieldall_reg);
|
|
2330 set(StubRoutines::Sparc::locked, lock_reg);
|
|
2331
|
|
2332 bind(retry_get_lock);
|
|
2333 cmp_and_br_short(yield_reg, V8AtomicOperationUnderLockSpinCount, Assembler::less, Assembler::pt, dont_yield);
|
|
2334
|
|
2335 if(use_call_vm) {
|
|
2336 Untested("Need to verify global reg consistancy");
|
|
2337 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
|
|
2338 } else {
|
|
2339 // Save the regs and make space for a C call
|
|
2340 save(SP, -96, SP);
|
|
2341 save_all_globals_into_locals();
|
|
2342 call(CAST_FROM_FN_PTR(address,os::yield_all));
|
|
2343 delayed()->mov(yieldall_reg, O0);
|
|
2344 restore_globals_from_locals();
|
|
2345 restore();
|
|
2346 }
|
|
2347
|
|
2348 // reset the counter
|
|
2349 mov(G0,yield_reg);
|
|
2350 add(yieldall_reg, 1, yieldall_reg);
|
|
2351
|
|
2352 bind(dont_yield);
|
|
2353 // try to get lock
|
|
2354 Assembler::swap(lock_ptr_reg, 0, lock_reg);
|
|
2355
|
|
2356 // did we get the lock?
|
|
2357 cmp(lock_reg, StubRoutines::Sparc::unlocked);
|
|
2358 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
|
|
2359 delayed()->add(yield_reg,1,yield_reg);
|
|
2360
|
|
2361 // yes, got lock. do we have the same top?
|
|
2362 ld(top_ptr_reg_after_save, 0, value_reg);
|
|
2363 cmp_and_br_short(value_reg, top_reg_after_save, Assembler::notEqual, Assembler::pn, not_same);
|
|
2364
|
|
2365 // yes, same top.
|
|
2366 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
|
|
2367 membar(Assembler::StoreStore);
|
|
2368
|
|
2369 bind(not_same);
|
|
2370 mov(value_reg, ptr_reg_after_save);
|
|
2371 st(lock_reg, lock_ptr_reg, 0); // unlock
|
|
2372
|
|
2373 restore();
|
|
2374 }
|
|
2375 }
|
|
2376
|
|
2377 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
|
|
2378 Register tmp,
|
|
2379 int offset) {
|
|
2380 intptr_t value = *delayed_value_addr;
|
|
2381 if (value != 0)
|
|
2382 return RegisterOrConstant(value + offset);
|
|
2383
|
|
2384 // load indirectly to solve generation ordering problem
|
|
2385 AddressLiteral a(delayed_value_addr);
|
|
2386 load_ptr_contents(a, tmp);
|
|
2387
|
|
2388 #ifdef ASSERT
|
|
2389 tst(tmp);
|
|
2390 breakpoint_trap(zero, xcc);
|
|
2391 #endif
|
|
2392
|
|
2393 if (offset != 0)
|
|
2394 add(tmp, offset, tmp);
|
|
2395
|
|
2396 return RegisterOrConstant(tmp);
|
|
2397 }
|
|
2398
|
|
2399
|
|
2400 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2401 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2402 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2403 (s2.is_register() && s2.as_register() == G0)) {
|
|
2404 // Do nothing, just move value.
|
|
2405 if (s1.is_register()) {
|
|
2406 if (d.is_constant()) d = temp;
|
|
2407 mov(s1.as_register(), d.as_register());
|
|
2408 return d;
|
|
2409 } else {
|
|
2410 return s1;
|
|
2411 }
|
|
2412 }
|
|
2413
|
|
2414 if (s1.is_register()) {
|
|
2415 assert_different_registers(s1.as_register(), temp);
|
|
2416 if (d.is_constant()) d = temp;
|
|
2417 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2418 return d;
|
|
2419 } else {
|
|
2420 if (s2.is_register()) {
|
|
2421 assert_different_registers(s2.as_register(), temp);
|
|
2422 if (d.is_constant()) d = temp;
|
|
2423 set(s1.as_constant(), temp);
|
|
2424 andn(temp, s2.as_register(), d.as_register());
|
|
2425 return d;
|
|
2426 } else {
|
|
2427 intptr_t res = s1.as_constant() & ~s2.as_constant();
|
|
2428 return res;
|
|
2429 }
|
|
2430 }
|
|
2431 }
|
|
2432
|
|
2433 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2434 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2435 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2436 (s2.is_register() && s2.as_register() == G0)) {
|
|
2437 // Do nothing, just move value.
|
|
2438 if (s1.is_register()) {
|
|
2439 if (d.is_constant()) d = temp;
|
|
2440 mov(s1.as_register(), d.as_register());
|
|
2441 return d;
|
|
2442 } else {
|
|
2443 return s1;
|
|
2444 }
|
|
2445 }
|
|
2446
|
|
2447 if (s1.is_register()) {
|
|
2448 assert_different_registers(s1.as_register(), temp);
|
|
2449 if (d.is_constant()) d = temp;
|
|
2450 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2451 return d;
|
|
2452 } else {
|
|
2453 if (s2.is_register()) {
|
|
2454 assert_different_registers(s2.as_register(), temp);
|
|
2455 if (d.is_constant()) d = temp;
|
|
2456 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register());
|
|
2457 return d;
|
|
2458 } else {
|
|
2459 intptr_t res = s1.as_constant() + s2.as_constant();
|
|
2460 return res;
|
|
2461 }
|
|
2462 }
|
|
2463 }
|
|
2464
|
|
2465 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) {
|
|
2466 assert(d.register_or_noreg() != G0, "lost side effect");
|
|
2467 if (!is_simm13(s2.constant_or_zero()))
|
|
2468 s2 = (s2.as_constant() & 0xFF);
|
|
2469 if ((s2.is_constant() && s2.as_constant() == 0) ||
|
|
2470 (s2.is_register() && s2.as_register() == G0)) {
|
|
2471 // Do nothing, just move value.
|
|
2472 if (s1.is_register()) {
|
|
2473 if (d.is_constant()) d = temp;
|
|
2474 mov(s1.as_register(), d.as_register());
|
|
2475 return d;
|
|
2476 } else {
|
|
2477 return s1;
|
|
2478 }
|
|
2479 }
|
|
2480
|
|
2481 if (s1.is_register()) {
|
|
2482 assert_different_registers(s1.as_register(), temp);
|
|
2483 if (d.is_constant()) d = temp;
|
|
2484 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register());
|
|
2485 return d;
|
|
2486 } else {
|
|
2487 if (s2.is_register()) {
|
|
2488 assert_different_registers(s2.as_register(), temp);
|
|
2489 if (d.is_constant()) d = temp;
|
|
2490 set(s1.as_constant(), temp);
|
|
2491 sll_ptr(temp, s2.as_register(), d.as_register());
|
|
2492 return d;
|
|
2493 } else {
|
|
2494 intptr_t res = s1.as_constant() << s2.as_constant();
|
|
2495 return res;
|
|
2496 }
|
|
2497 }
|
|
2498 }
|
|
2499
|
|
2500
|
|
2501 // Look up the method for a megamorphic invokeinterface call.
|
|
2502 // The target method is determined by <intf_klass, itable_index>.
|
|
2503 // The receiver klass is in recv_klass.
|
|
2504 // On success, the result will be in method_result, and execution falls through.
|
|
2505 // On failure, execution transfers to the given label.
|
|
2506 void MacroAssembler::lookup_interface_method(Register recv_klass,
|
|
2507 Register intf_klass,
|
|
2508 RegisterOrConstant itable_index,
|
|
2509 Register method_result,
|
|
2510 Register scan_temp,
|
|
2511 Register sethi_temp,
|
|
2512 Label& L_no_such_interface) {
|
|
2513 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
|
|
2514 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
|
|
2515 "caller must use same register for non-constant itable index as for method");
|
|
2516
|
|
2517 Label L_no_such_interface_restore;
|
|
2518 bool did_save = false;
|
|
2519 if (scan_temp == noreg || sethi_temp == noreg) {
|
|
2520 Register recv_2 = recv_klass->is_global() ? recv_klass : L0;
|
|
2521 Register intf_2 = intf_klass->is_global() ? intf_klass : L1;
|
|
2522 assert(method_result->is_global(), "must be able to return value");
|
|
2523 scan_temp = L2;
|
|
2524 sethi_temp = L3;
|
|
2525 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2);
|
|
2526 recv_klass = recv_2;
|
|
2527 intf_klass = intf_2;
|
|
2528 did_save = true;
|
|
2529 }
|
|
2530
|
|
2531 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
|
|
2532 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
|
|
2533 int scan_step = itableOffsetEntry::size() * wordSize;
|
|
2534 int vte_size = vtableEntry::size() * wordSize;
|
|
2535
|
|
2536 lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp);
|
|
2537 // %%% We should store the aligned, prescaled offset in the klassoop.
|
|
2538 // Then the next several instructions would fold away.
|
|
2539
|
|
2540 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
|
|
2541 int itb_offset = vtable_base;
|
|
2542 if (round_to_unit != 0) {
|
|
2543 // hoist first instruction of round_to(scan_temp, BytesPerLong):
|
|
2544 itb_offset += round_to_unit - wordSize;
|
|
2545 }
|
|
2546 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
|
|
2547 sll(scan_temp, itb_scale, scan_temp);
|
|
2548 add(scan_temp, itb_offset, scan_temp);
|
|
2549 if (round_to_unit != 0) {
|
|
2550 // Round up to align_object_offset boundary
|
|
2551 // see code for InstanceKlass::start_of_itable!
|
|
2552 // Was: round_to(scan_temp, BytesPerLong);
|
|
2553 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
|
|
2554 and3(scan_temp, -round_to_unit, scan_temp);
|
|
2555 }
|
|
2556 add(recv_klass, scan_temp, scan_temp);
|
|
2557
|
|
2558 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
|
|
2559 RegisterOrConstant itable_offset = itable_index;
|
|
2560 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset);
|
|
2561 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset);
|
|
2562 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass);
|
|
2563
|
|
2564 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
|
|
2565 // if (scan->interface() == intf) {
|
|
2566 // result = (klass + scan->offset() + itable_index);
|
|
2567 // }
|
|
2568 // }
|
|
2569 Label L_search, L_found_method;
|
|
2570
|
|
2571 for (int peel = 1; peel >= 0; peel--) {
|
|
2572 // %%%% Could load both offset and interface in one ldx, if they were
|
|
2573 // in the opposite order. This would save a load.
|
|
2574 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
|
|
2575
|
|
2576 // Check that this entry is non-null. A null entry means that
|
|
2577 // the receiver class doesn't implement the interface, and wasn't the
|
|
2578 // same as when the caller was compiled.
|
|
2579 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface);
|
|
2580 delayed()->cmp(method_result, intf_klass);
|
|
2581
|
|
2582 if (peel) {
|
|
2583 brx(Assembler::equal, false, Assembler::pt, L_found_method);
|
|
2584 } else {
|
|
2585 brx(Assembler::notEqual, false, Assembler::pn, L_search);
|
|
2586 // (invert the test to fall through to found_method...)
|
|
2587 }
|
|
2588 delayed()->add(scan_temp, scan_step, scan_temp);
|
|
2589
|
|
2590 if (!peel) break;
|
|
2591
|
|
2592 bind(L_search);
|
|
2593 }
|
|
2594
|
|
2595 bind(L_found_method);
|
|
2596
|
|
2597 // Got a hit.
|
|
2598 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
|
|
2599 // scan_temp[-scan_step] points to the vtable offset we need
|
|
2600 ito_offset -= scan_step;
|
|
2601 lduw(scan_temp, ito_offset, scan_temp);
|
|
2602 ld_ptr(recv_klass, scan_temp, method_result);
|
|
2603
|
|
2604 if (did_save) {
|
|
2605 Label L_done;
|
|
2606 ba(L_done);
|
|
2607 delayed()->restore();
|
|
2608
|
|
2609 bind(L_no_such_interface_restore);
|
|
2610 ba(L_no_such_interface);
|
|
2611 delayed()->restore();
|
|
2612
|
|
2613 bind(L_done);
|
|
2614 }
|
|
2615 }
|
|
2616
|
|
2617
|
|
2618 // virtual method calling
|
|
2619 void MacroAssembler::lookup_virtual_method(Register recv_klass,
|
|
2620 RegisterOrConstant vtable_index,
|
|
2621 Register method_result) {
|
|
2622 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
|
|
2623 Register sethi_temp = method_result;
|
|
2624 const int base = (InstanceKlass::vtable_start_offset() * wordSize +
|
|
2625 // method pointer offset within the vtable entry:
|
|
2626 vtableEntry::method_offset_in_bytes());
|
|
2627 RegisterOrConstant vtable_offset = vtable_index;
|
|
2628 // Each of the following three lines potentially generates an instruction.
|
|
2629 // But the total number of address formation instructions will always be
|
|
2630 // at most two, and will often be zero. In any case, it will be optimal.
|
|
2631 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x).
|
|
2632 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t).
|
|
2633 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset);
|
|
2634 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp);
|
|
2635 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp));
|
|
2636 ld_ptr(vtable_entry_addr, method_result);
|
|
2637 }
|
|
2638
|
|
2639
|
|
2640 void MacroAssembler::check_klass_subtype(Register sub_klass,
|
|
2641 Register super_klass,
|
|
2642 Register temp_reg,
|
|
2643 Register temp2_reg,
|
|
2644 Label& L_success) {
|
|
2645 Register sub_2 = sub_klass;
|
|
2646 Register sup_2 = super_klass;
|
|
2647 if (!sub_2->is_global()) sub_2 = L0;
|
|
2648 if (!sup_2->is_global()) sup_2 = L1;
|
|
2649 bool did_save = false;
|
|
2650 if (temp_reg == noreg || temp2_reg == noreg) {
|
|
2651 temp_reg = L2;
|
|
2652 temp2_reg = L3;
|
|
2653 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
|
|
2654 sub_klass = sub_2;
|
|
2655 super_klass = sup_2;
|
|
2656 did_save = true;
|
|
2657 }
|
|
2658 Label L_failure, L_pop_to_failure, L_pop_to_success;
|
|
2659 check_klass_subtype_fast_path(sub_klass, super_klass,
|
|
2660 temp_reg, temp2_reg,
|
|
2661 (did_save ? &L_pop_to_success : &L_success),
|
|
2662 (did_save ? &L_pop_to_failure : &L_failure), NULL);
|
|
2663
|
|
2664 if (!did_save)
|
|
2665 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
|
|
2666 check_klass_subtype_slow_path(sub_2, sup_2,
|
|
2667 L2, L3, L4, L5,
|
|
2668 NULL, &L_pop_to_failure);
|
|
2669
|
|
2670 // on success:
|
|
2671 bind(L_pop_to_success);
|
|
2672 restore();
|
|
2673 ba_short(L_success);
|
|
2674
|
|
2675 // on failure:
|
|
2676 bind(L_pop_to_failure);
|
|
2677 restore();
|
|
2678 bind(L_failure);
|
|
2679 }
|
|
2680
|
|
2681
|
|
2682 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
|
|
2683 Register super_klass,
|
|
2684 Register temp_reg,
|
|
2685 Register temp2_reg,
|
|
2686 Label* L_success,
|
|
2687 Label* L_failure,
|
|
2688 Label* L_slow_path,
|
|
2689 RegisterOrConstant super_check_offset) {
|
|
2690 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
|
|
2691 int sco_offset = in_bytes(Klass::super_check_offset_offset());
|
|
2692
|
|
2693 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
|
|
2694 bool need_slow_path = (must_load_sco ||
|
|
2695 super_check_offset.constant_or_zero() == sco_offset);
|
|
2696
|
|
2697 assert_different_registers(sub_klass, super_klass, temp_reg);
|
|
2698 if (super_check_offset.is_register()) {
|
|
2699 assert_different_registers(sub_klass, super_klass, temp_reg,
|
|
2700 super_check_offset.as_register());
|
|
2701 } else if (must_load_sco) {
|
|
2702 assert(temp2_reg != noreg, "supply either a temp or a register offset");
|
|
2703 }
|
|
2704
|
|
2705 Label L_fallthrough;
|
|
2706 int label_nulls = 0;
|
|
2707 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
|
|
2708 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
|
|
2709 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
|
|
2710 assert(label_nulls <= 1 ||
|
|
2711 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
|
|
2712 "at most one NULL in the batch, usually");
|
|
2713
|
|
2714 // If the pointers are equal, we are done (e.g., String[] elements).
|
|
2715 // This self-check enables sharing of secondary supertype arrays among
|
|
2716 // non-primary types such as array-of-interface. Otherwise, each such
|
|
2717 // type would need its own customized SSA.
|
|
2718 // We move this check to the front of the fast path because many
|
|
2719 // type checks are in fact trivially successful in this manner,
|
|
2720 // so we get a nicely predicted branch right at the start of the check.
|
|
2721 cmp(super_klass, sub_klass);
|
|
2722 brx(Assembler::equal, false, Assembler::pn, *L_success);
|
|
2723 delayed()->nop();
|
|
2724
|
|
2725 // Check the supertype display:
|
|
2726 if (must_load_sco) {
|
|
2727 // The super check offset is always positive...
|
|
2728 lduw(super_klass, sco_offset, temp2_reg);
|
|
2729 super_check_offset = RegisterOrConstant(temp2_reg);
|
|
2730 // super_check_offset is register.
|
|
2731 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register());
|
|
2732 }
|
|
2733 ld_ptr(sub_klass, super_check_offset, temp_reg);
|
|
2734 cmp(super_klass, temp_reg);
|
|
2735
|
|
2736 // This check has worked decisively for primary supers.
|
|
2737 // Secondary supers are sought in the super_cache ('super_cache_addr').
|
|
2738 // (Secondary supers are interfaces and very deeply nested subtypes.)
|
|
2739 // This works in the same check above because of a tricky aliasing
|
|
2740 // between the super_cache and the primary super display elements.
|
|
2741 // (The 'super_check_addr' can address either, as the case requires.)
|
|
2742 // Note that the cache is updated below if it does not help us find
|
|
2743 // what we need immediately.
|
|
2744 // So if it was a primary super, we can just fail immediately.
|
|
2745 // Otherwise, it's the slow path for us (no success at this point).
|
|
2746
|
|
2747 // Hacked ba(), which may only be used just before L_fallthrough.
|
|
2748 #define FINAL_JUMP(label) \
|
|
2749 if (&(label) != &L_fallthrough) { \
|
|
2750 ba(label); delayed()->nop(); \
|
|
2751 }
|
|
2752
|
|
2753 if (super_check_offset.is_register()) {
|
|
2754 brx(Assembler::equal, false, Assembler::pn, *L_success);
|
|
2755 delayed()->cmp(super_check_offset.as_register(), sc_offset);
|
|
2756
|
|
2757 if (L_failure == &L_fallthrough) {
|
|
2758 brx(Assembler::equal, false, Assembler::pt, *L_slow_path);
|
|
2759 delayed()->nop();
|
|
2760 } else {
|
|
2761 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
|
|
2762 delayed()->nop();
|
|
2763 FINAL_JUMP(*L_slow_path);
|
|
2764 }
|
|
2765 } else if (super_check_offset.as_constant() == sc_offset) {
|
|
2766 // Need a slow path; fast failure is impossible.
|
|
2767 if (L_slow_path == &L_fallthrough) {
|
|
2768 brx(Assembler::equal, false, Assembler::pt, *L_success);
|
|
2769 delayed()->nop();
|
|
2770 } else {
|
|
2771 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
|
|
2772 delayed()->nop();
|
|
2773 FINAL_JUMP(*L_success);
|
|
2774 }
|
|
2775 } else {
|
|
2776 // No slow path; it's a fast decision.
|
|
2777 if (L_failure == &L_fallthrough) {
|
|
2778 brx(Assembler::equal, false, Assembler::pt, *L_success);
|
|
2779 delayed()->nop();
|
|
2780 } else {
|
|
2781 brx(Assembler::notEqual, false, Assembler::pn, *L_failure);
|
|
2782 delayed()->nop();
|
|
2783 FINAL_JUMP(*L_success);
|
|
2784 }
|
|
2785 }
|
|
2786
|
|
2787 bind(L_fallthrough);
|
|
2788
|
|
2789 #undef FINAL_JUMP
|
|
2790 }
|
|
2791
|
|
2792
|
|
2793 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
|
|
2794 Register super_klass,
|
|
2795 Register count_temp,
|
|
2796 Register scan_temp,
|
|
2797 Register scratch_reg,
|
|
2798 Register coop_reg,
|
|
2799 Label* L_success,
|
|
2800 Label* L_failure) {
|
|
2801 assert_different_registers(sub_klass, super_klass,
|
|
2802 count_temp, scan_temp, scratch_reg, coop_reg);
|
|
2803
|
|
2804 Label L_fallthrough, L_loop;
|
|
2805 int label_nulls = 0;
|
|
2806 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
|
|
2807 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
|
|
2808 assert(label_nulls <= 1, "at most one NULL in the batch");
|
|
2809
|
|
2810 // a couple of useful fields in sub_klass:
|
|
2811 int ss_offset = in_bytes(Klass::secondary_supers_offset());
|
|
2812 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
|
|
2813
|
|
2814 // Do a linear scan of the secondary super-klass chain.
|
|
2815 // This code is rarely used, so simplicity is a virtue here.
|
|
2816
|
|
2817 #ifndef PRODUCT
|
|
2818 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
|
|
2819 inc_counter((address) pst_counter, count_temp, scan_temp);
|
|
2820 #endif
|
|
2821
|
|
2822 // We will consult the secondary-super array.
|
|
2823 ld_ptr(sub_klass, ss_offset, scan_temp);
|
|
2824
|
|
2825 Register search_key = super_klass;
|
|
2826
|
|
2827 // Load the array length. (Positive movl does right thing on LP64.)
|
|
2828 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp);
|
|
2829
|
|
2830 // Check for empty secondary super list
|
|
2831 tst(count_temp);
|
|
2832
|
|
2833 // In the array of super classes elements are pointer sized.
|
|
2834 int element_size = wordSize;
|
|
2835
|
|
2836 // Top of search loop
|
|
2837 bind(L_loop);
|
|
2838 br(Assembler::equal, false, Assembler::pn, *L_failure);
|
|
2839 delayed()->add(scan_temp, element_size, scan_temp);
|
|
2840
|
|
2841 // Skip the array header in all array accesses.
|
|
2842 int elem_offset = Array<Klass*>::base_offset_in_bytes();
|
|
2843 elem_offset -= element_size; // the scan pointer was pre-incremented also
|
|
2844
|
|
2845 // Load next super to check
|
|
2846 ld_ptr( scan_temp, elem_offset, scratch_reg );
|
|
2847
|
|
2848 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
|
|
2849 cmp(scratch_reg, search_key);
|
|
2850
|
|
2851 // A miss means we are NOT a subtype and need to keep looping
|
|
2852 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
|
|
2853 delayed()->deccc(count_temp); // decrement trip counter in delay slot
|
|
2854
|
|
2855 // Success. Cache the super we found and proceed in triumph.
|
|
2856 st_ptr(super_klass, sub_klass, sc_offset);
|
|
2857
|
|
2858 if (L_success != &L_fallthrough) {
|
|
2859 ba(*L_success);
|
|
2860 delayed()->nop();
|
|
2861 }
|
|
2862
|
|
2863 bind(L_fallthrough);
|
|
2864 }
|
|
2865
|
|
2866
|
|
2867 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
|
|
2868 Register temp_reg,
|
|
2869 int extra_slot_offset) {
|
|
2870 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
|
|
2871 int stackElementSize = Interpreter::stackElementSize;
|
|
2872 int offset = extra_slot_offset * stackElementSize;
|
|
2873 if (arg_slot.is_constant()) {
|
|
2874 offset += arg_slot.as_constant() * stackElementSize;
|
|
2875 return offset;
|
|
2876 } else {
|
|
2877 assert(temp_reg != noreg, "must specify");
|
|
2878 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg);
|
|
2879 if (offset != 0)
|
|
2880 add(temp_reg, offset, temp_reg);
|
|
2881 return temp_reg;
|
|
2882 }
|
|
2883 }
|
|
2884
|
|
2885
|
|
2886 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
|
|
2887 Register temp_reg,
|
|
2888 int extra_slot_offset) {
|
|
2889 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset));
|
|
2890 }
|
|
2891
|
|
2892
|
|
2893 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
|
|
2894 Register temp_reg,
|
|
2895 Label& done, Label* slow_case,
|
|
2896 BiasedLockingCounters* counters) {
|
|
2897 assert(UseBiasedLocking, "why call this otherwise?");
|
|
2898
|
|
2899 if (PrintBiasedLockingStatistics) {
|
|
2900 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
|
|
2901 if (counters == NULL)
|
|
2902 counters = BiasedLocking::counters();
|
|
2903 }
|
|
2904
|
|
2905 Label cas_label;
|
|
2906
|
|
2907 // Biased locking
|
|
2908 // See whether the lock is currently biased toward our thread and
|
|
2909 // whether the epoch is still valid
|
|
2910 // Note that the runtime guarantees sufficient alignment of JavaThread
|
|
2911 // pointers to allow age to be placed into low bits
|
|
2912 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
|
|
2913 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
2914 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label);
|
|
2915
|
|
2916 load_klass(obj_reg, temp_reg);
|
|
2917 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
2918 or3(G2_thread, temp_reg, temp_reg);
|
|
2919 xor3(mark_reg, temp_reg, temp_reg);
|
|
2920 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
|
|
2921 if (counters != NULL) {
|
|
2922 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
2923 // Reload mark_reg as we may need it later
|
|
2924 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
|
|
2925 }
|
|
2926 brx(Assembler::equal, true, Assembler::pt, done);
|
|
2927 delayed()->nop();
|
|
2928
|
|
2929 Label try_revoke_bias;
|
|
2930 Label try_rebias;
|
|
2931 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
|
|
2932 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
2933
|
|
2934 // At this point we know that the header has the bias pattern and
|
|
2935 // that we are not the bias owner in the current epoch. We need to
|
|
2936 // figure out more details about the state of the header in order to
|
|
2937 // know what operations can be legally performed on the object's
|
|
2938 // header.
|
|
2939
|
|
2940 // If the low three bits in the xor result aren't clear, that means
|
|
2941 // the prototype header is no longer biased and we have to revoke
|
|
2942 // the bias on this object.
|
|
2943 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
2944 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
|
|
2945
|
|
2946 // Biasing is still enabled for this data type. See whether the
|
|
2947 // epoch of the current bias is still valid, meaning that the epoch
|
|
2948 // bits of the mark word are equal to the epoch bits of the
|
|
2949 // prototype header. (Note that the prototype header's epoch bits
|
|
2950 // only change at a safepoint.) If not, attempt to rebias the object
|
|
2951 // toward the current thread. Note that we must be absolutely sure
|
|
2952 // that the current epoch is invalid in order to do this because
|
|
2953 // otherwise the manipulations it performs on the mark word are
|
|
2954 // illegal.
|
|
2955 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
|
|
2956 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
|
|
2957
|
|
2958 // The epoch of the current bias is still valid but we know nothing
|
|
2959 // about the owner; it might be set or it might be clear. Try to
|
|
2960 // acquire the bias of the object using an atomic operation. If this
|
|
2961 // fails we will go in to the runtime to revoke the object's bias.
|
|
2962 // Note that we first construct the presumed unbiased header so we
|
|
2963 // don't accidentally blow away another thread's valid bias.
|
|
2964 delayed()->and3(mark_reg,
|
|
2965 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
|
|
2966 mark_reg);
|
|
2967 or3(G2_thread, mark_reg, temp_reg);
|
|
2968 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
2969 // If the biasing toward our thread failed, this means that
|
|
2970 // another thread succeeded in biasing it toward itself and we
|
|
2971 // need to revoke that bias. The revocation will occur in the
|
|
2972 // interpreter runtime in the slow case.
|
|
2973 cmp(mark_reg, temp_reg);
|
|
2974 if (counters != NULL) {
|
|
2975 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
2976 }
|
|
2977 if (slow_case != NULL) {
|
|
2978 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
|
|
2979 delayed()->nop();
|
|
2980 }
|
|
2981 ba_short(done);
|
|
2982
|
|
2983 bind(try_rebias);
|
|
2984 // At this point we know the epoch has expired, meaning that the
|
|
2985 // current "bias owner", if any, is actually invalid. Under these
|
|
2986 // circumstances _only_, we are allowed to use the current header's
|
|
2987 // value as the comparison value when doing the cas to acquire the
|
|
2988 // bias in the current epoch. In other words, we allow transfer of
|
|
2989 // the bias from one thread to another directly in this situation.
|
|
2990 //
|
|
2991 // FIXME: due to a lack of registers we currently blow away the age
|
|
2992 // bits in this situation. Should attempt to preserve them.
|
|
2993 load_klass(obj_reg, temp_reg);
|
|
2994 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
2995 or3(G2_thread, temp_reg, temp_reg);
|
|
2996 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
2997 // If the biasing toward our thread failed, this means that
|
|
2998 // another thread succeeded in biasing it toward itself and we
|
|
2999 // need to revoke that bias. The revocation will occur in the
|
|
3000 // interpreter runtime in the slow case.
|
|
3001 cmp(mark_reg, temp_reg);
|
|
3002 if (counters != NULL) {
|
|
3003 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
3004 }
|
|
3005 if (slow_case != NULL) {
|
|
3006 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
|
|
3007 delayed()->nop();
|
|
3008 }
|
|
3009 ba_short(done);
|
|
3010
|
|
3011 bind(try_revoke_bias);
|
|
3012 // The prototype mark in the klass doesn't have the bias bit set any
|
|
3013 // more, indicating that objects of this data type are not supposed
|
|
3014 // to be biased any more. We are going to try to reset the mark of
|
|
3015 // this object to the prototype value and fall through to the
|
|
3016 // CAS-based locking scheme. Note that if our CAS fails, it means
|
|
3017 // that another thread raced us for the privilege of revoking the
|
|
3018 // bias of this particular object, so it's okay to continue in the
|
|
3019 // normal locking code.
|
|
3020 //
|
|
3021 // FIXME: due to a lack of registers we currently blow away the age
|
|
3022 // bits in this situation. Should attempt to preserve them.
|
|
3023 load_klass(obj_reg, temp_reg);
|
|
3024 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg);
|
|
3025 casn(mark_addr.base(), mark_reg, temp_reg);
|
|
3026 // Fall through to the normal CAS-based lock, because no matter what
|
|
3027 // the result of the above CAS, some thread must have succeeded in
|
|
3028 // removing the bias bit from the object's header.
|
|
3029 if (counters != NULL) {
|
|
3030 cmp(mark_reg, temp_reg);
|
|
3031 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
|
|
3032 }
|
|
3033
|
|
3034 bind(cas_label);
|
|
3035 }
|
|
3036
|
|
3037 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
|
|
3038 bool allow_delay_slot_filling) {
|
|
3039 // Check for biased locking unlock case, which is a no-op
|
|
3040 // Note: we do not have to check the thread ID for two reasons.
|
|
3041 // First, the interpreter checks for IllegalMonitorStateException at
|
|
3042 // a higher level. Second, if the bias was revoked while we held the
|
|
3043 // lock, the object could not be rebiased toward another thread, so
|
|
3044 // the bias bit would be clear.
|
|
3045 ld_ptr(mark_addr, temp_reg);
|
|
3046 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
|
|
3047 cmp(temp_reg, markOopDesc::biased_lock_pattern);
|
|
3048 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
|
|
3049 delayed();
|
|
3050 if (!allow_delay_slot_filling) {
|
|
3051 nop();
|
|
3052 }
|
|
3053 }
|
|
3054
|
|
3055
|
|
3056 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
|
|
3057 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
|
|
3058
|
|
3059 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
|
|
3060 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3061 }
|
|
3062
|
|
3063
|
|
3064
|
|
3065 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
|
|
3066 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
|
|
3067 // The code could be tightened up considerably.
|
|
3068 //
|
|
3069 // box->dhw disposition - post-conditions at DONE_LABEL.
|
|
3070 // - Successful inflated lock: box->dhw != 0.
|
|
3071 // Any non-zero value suffices.
|
|
3072 // Consider G2_thread, rsp, boxReg, or unused_mark()
|
|
3073 // - Successful Stack-lock: box->dhw == mark.
|
|
3074 // box->dhw must contain the displaced mark word value
|
|
3075 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
|
|
3076 // The slow-path fast_enter() and slow_enter() operators
|
|
3077 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
|
|
3078 // - Biased: box->dhw is undefined
|
|
3079 //
|
|
3080 // SPARC refworkload performance - specifically jetstream and scimark - are
|
|
3081 // extremely sensitive to the size of the code emitted by compiler_lock_object
|
|
3082 // and compiler_unlock_object. Critically, the key factor is code size, not path
|
|
3083 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
|
|
3084 // effect).
|
|
3085
|
|
3086
|
|
3087 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
|
|
3088 Register Rbox, Register Rscratch,
|
|
3089 BiasedLockingCounters* counters,
|
|
3090 bool try_bias) {
|
|
3091 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
|
|
3092
|
|
3093 verify_oop(Roop);
|
|
3094 Label done ;
|
|
3095
|
|
3096 if (counters != NULL) {
|
|
3097 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
|
|
3098 }
|
|
3099
|
|
3100 if (EmitSync & 1) {
|
|
3101 mov(3, Rscratch);
|
|
3102 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3103 cmp(SP, G0);
|
|
3104 return ;
|
|
3105 }
|
|
3106
|
|
3107 if (EmitSync & 2) {
|
|
3108
|
|
3109 // Fetch object's markword
|
|
3110 ld_ptr(mark_addr, Rmark);
|
|
3111
|
|
3112 if (try_bias) {
|
|
3113 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3114 }
|
|
3115
|
|
3116 // Save Rbox in Rscratch to be used for the cas operation
|
|
3117 mov(Rbox, Rscratch);
|
|
3118
|
|
3119 // set Rmark to markOop | markOopDesc::unlocked_value
|
|
3120 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3121
|
|
3122 // Initialize the box. (Must happen before we update the object mark!)
|
|
3123 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3124
|
|
3125 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
|
|
3126 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3127 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
|
|
3128 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3129
|
|
3130 // if compare/exchange succeeded we found an unlocked object and we now have locked it
|
|
3131 // hence we are done
|
|
3132 cmp(Rmark, Rscratch);
|
|
3133 #ifdef _LP64
|
|
3134 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3135 #endif
|
|
3136 brx(Assembler::equal, false, Assembler::pt, done);
|
|
3137 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
|
|
3138
|
|
3139 // we did not find an unlocked object so see if this is a recursive case
|
|
3140 // sub(Rscratch, SP, Rscratch);
|
|
3141 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3142 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3143 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3144 bind (done);
|
|
3145 return ;
|
|
3146 }
|
|
3147
|
|
3148 Label Egress ;
|
|
3149
|
|
3150 if (EmitSync & 256) {
|
|
3151 Label IsInflated ;
|
|
3152
|
|
3153 ld_ptr(mark_addr, Rmark); // fetch obj->mark
|
|
3154 // Triage: biased, stack-locked, neutral, inflated
|
|
3155 if (try_bias) {
|
|
3156 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3157 // Invariant: if control reaches this point in the emitted stream
|
|
3158 // then Rmark has not been modified.
|
|
3159 }
|
|
3160
|
|
3161 // Store mark into displaced mark field in the on-stack basic-lock "box"
|
|
3162 // Critically, this must happen before the CAS
|
|
3163 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
|
|
3164 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3165 andcc(Rmark, 2, G0);
|
|
3166 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
|
|
3167 delayed()->
|
|
3168
|
|
3169 // Try stack-lock acquisition.
|
|
3170 // Beware: the 1st instruction is in a delay slot
|
|
3171 mov(Rbox, Rscratch);
|
|
3172 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3173 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3174 casn(mark_addr.base(), Rmark, Rscratch);
|
|
3175 cmp(Rmark, Rscratch);
|
|
3176 brx(Assembler::equal, false, Assembler::pt, done);
|
|
3177 delayed()->sub(Rscratch, SP, Rscratch);
|
|
3178
|
|
3179 // Stack-lock attempt failed - check for recursive stack-lock.
|
|
3180 // See the comments below about how we might remove this case.
|
|
3181 #ifdef _LP64
|
|
3182 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3183 #endif
|
|
3184 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3185 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3186 br(Assembler::always, false, Assembler::pt, done);
|
|
3187 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3188
|
|
3189 bind(IsInflated);
|
|
3190 if (EmitSync & 64) {
|
|
3191 // If m->owner != null goto IsLocked
|
|
3192 // Pessimistic form: Test-and-CAS vs CAS
|
|
3193 // The optimistic form avoids RTS->RTO cache line upgrades.
|
|
3194 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3195 andcc(Rscratch, Rscratch, G0);
|
|
3196 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3197 delayed()->nop();
|
|
3198 // m->owner == null : it's unlocked.
|
|
3199 }
|
|
3200
|
|
3201 // Try to CAS m->owner from null to Self
|
|
3202 // Invariant: if we acquire the lock then _recursions should be 0.
|
|
3203 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3204 mov(G2_thread, Rscratch);
|
|
3205 casn(Rmark, G0, Rscratch);
|
|
3206 cmp(Rscratch, G0);
|
|
3207 // Intentional fall-through into done
|
|
3208 } else {
|
|
3209 // Aggressively avoid the Store-before-CAS penalty
|
|
3210 // Defer the store into box->dhw until after the CAS
|
|
3211 Label IsInflated, Recursive ;
|
|
3212
|
|
3213 // Anticipate CAS -- Avoid RTS->RTO upgrade
|
|
3214 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
|
|
3215
|
|
3216 ld_ptr(mark_addr, Rmark); // fetch obj->mark
|
|
3217 // Triage: biased, stack-locked, neutral, inflated
|
|
3218
|
|
3219 if (try_bias) {
|
|
3220 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
|
|
3221 // Invariant: if control reaches this point in the emitted stream
|
|
3222 // then Rmark has not been modified.
|
|
3223 }
|
|
3224 andcc(Rmark, 2, G0);
|
|
3225 brx(Assembler::notZero, false, Assembler::pn, IsInflated);
|
|
3226 delayed()-> // Beware - dangling delay-slot
|
|
3227
|
|
3228 // Try stack-lock acquisition.
|
|
3229 // Transiently install BUSY (0) encoding in the mark word.
|
|
3230 // if the CAS of 0 into the mark was successful then we execute:
|
|
3231 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
|
|
3232 // ST obj->mark = box -- overwrite transient 0 value
|
|
3233 // This presumes TSO, of course.
|
|
3234
|
|
3235 mov(0, Rscratch);
|
|
3236 or3(Rmark, markOopDesc::unlocked_value, Rmark);
|
|
3237 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3238 casn(mark_addr.base(), Rmark, Rscratch);
|
|
3239 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads);
|
|
3240 cmp(Rscratch, Rmark);
|
|
3241 brx(Assembler::notZero, false, Assembler::pn, Recursive);
|
|
3242 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3243 if (counters != NULL) {
|
|
3244 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
|
|
3245 }
|
|
3246 ba(done);
|
|
3247 delayed()->st_ptr(Rbox, mark_addr);
|
|
3248
|
|
3249 bind(Recursive);
|
|
3250 // Stack-lock attempt failed - check for recursive stack-lock.
|
|
3251 // Tests show that we can remove the recursive case with no impact
|
|
3252 // on refworkload 0.83. If we need to reduce the size of the code
|
|
3253 // emitted by compiler_lock_object() the recursive case is perfect
|
|
3254 // candidate.
|
|
3255 //
|
|
3256 // A more extreme idea is to always inflate on stack-lock recursion.
|
|
3257 // This lets us eliminate the recursive checks in compiler_lock_object
|
|
3258 // and compiler_unlock_object and the (box->dhw == 0) encoding.
|
|
3259 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
|
|
3260 // and showed a performance *increase*. In the same experiment I eliminated
|
|
3261 // the fast-path stack-lock code from the interpreter and always passed
|
|
3262 // control to the "slow" operators in synchronizer.cpp.
|
|
3263
|
|
3264 // RScratch contains the fetched obj->mark value from the failed CASN.
|
|
3265 #ifdef _LP64
|
|
3266 sub(Rscratch, STACK_BIAS, Rscratch);
|
|
3267 #endif
|
|
3268 sub(Rscratch, SP, Rscratch);
|
|
3269 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
|
|
3270 andcc(Rscratch, 0xfffff003, Rscratch);
|
|
3271 if (counters != NULL) {
|
|
3272 // Accounting needs the Rscratch register
|
|
3273 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3274 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
|
|
3275 ba_short(done);
|
|
3276 } else {
|
|
3277 ba(done);
|
|
3278 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3279 }
|
|
3280
|
|
3281 bind (IsInflated);
|
|
3282 if (EmitSync & 64) {
|
|
3283 // If m->owner != null goto IsLocked
|
|
3284 // Test-and-CAS vs CAS
|
|
3285 // Pessimistic form avoids futile (doomed) CAS attempts
|
|
3286 // The optimistic form avoids RTS->RTO cache line upgrades.
|
|
3287 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3288 andcc(Rscratch, Rscratch, G0);
|
|
3289 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3290 delayed()->nop();
|
|
3291 // m->owner == null : it's unlocked.
|
|
3292 }
|
|
3293
|
|
3294 // Try to CAS m->owner from null to Self
|
|
3295 // Invariant: if we acquire the lock then _recursions should be 0.
|
|
3296 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3297 mov(G2_thread, Rscratch);
|
|
3298 casn(Rmark, G0, Rscratch);
|
|
3299 cmp(Rscratch, G0);
|
|
3300 // ST box->displaced_header = NonZero.
|
|
3301 // Any non-zero value suffices:
|
|
3302 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
|
|
3303 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
|
|
3304 // Intentional fall-through into done
|
|
3305 }
|
|
3306
|
|
3307 bind (done);
|
|
3308 }
|
|
3309
|
|
3310 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
|
|
3311 Register Rbox, Register Rscratch,
|
|
3312 bool try_bias) {
|
|
3313 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
|
|
3314
|
|
3315 Label done ;
|
|
3316
|
|
3317 if (EmitSync & 4) {
|
|
3318 cmp(SP, G0);
|
|
3319 return ;
|
|
3320 }
|
|
3321
|
|
3322 if (EmitSync & 8) {
|
|
3323 if (try_bias) {
|
|
3324 biased_locking_exit(mark_addr, Rscratch, done);
|
|
3325 }
|
|
3326
|
|
3327 // Test first if it is a fast recursive unlock
|
|
3328 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
|
|
3329 br_null_short(Rmark, Assembler::pt, done);
|
|
3330
|
|
3331 // Check if it is still a light weight lock, this is is true if we see
|
|
3332 // the stack address of the basicLock in the markOop of the object
|
|
3333 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
|
|
3334 casx_under_lock(mark_addr.base(), Rbox, Rmark,
|
|
3335 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3336 ba(done);
|
|
3337 delayed()->cmp(Rbox, Rmark);
|
|
3338 bind(done);
|
|
3339 return ;
|
|
3340 }
|
|
3341
|
|
3342 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
|
|
3343 // is too large performance rolls abruptly off a cliff.
|
|
3344 // This could be related to inlining policies, code cache management, or
|
|
3345 // I$ effects.
|
|
3346 Label LStacked ;
|
|
3347
|
|
3348 if (try_bias) {
|
|
3349 // TODO: eliminate redundant LDs of obj->mark
|
|
3350 biased_locking_exit(mark_addr, Rscratch, done);
|
|
3351 }
|
|
3352
|
|
3353 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark);
|
|
3354 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
|
|
3355 andcc(Rscratch, Rscratch, G0);
|
|
3356 brx(Assembler::zero, false, Assembler::pn, done);
|
|
3357 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS
|
|
3358 andcc(Rmark, 2, G0);
|
|
3359 brx(Assembler::zero, false, Assembler::pt, LStacked);
|
|
3360 delayed()->nop();
|
|
3361
|
|
3362 // It's inflated
|
|
3363 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
|
|
3364 // the ST of 0 into _owner which releases the lock. This prevents loads
|
|
3365 // and stores within the critical section from reordering (floating)
|
|
3366 // past the store that releases the lock. But TSO is a strong memory model
|
|
3367 // and that particular flavor of barrier is a noop, so we can safely elide it.
|
|
3368 // Note that we use 1-0 locking by default for the inflated case. We
|
|
3369 // close the resultant (and rare) race by having contented threads in
|
|
3370 // monitorenter periodically poll _owner.
|
|
3371 ld_ptr(Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
|
|
3372 ld_ptr(Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
|
|
3373 xor3(Rscratch, G2_thread, Rscratch);
|
|
3374 orcc(Rbox, Rscratch, Rbox);
|
|
3375 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3376 delayed()->
|
|
3377 ld_ptr(Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
|
|
3378 ld_ptr(Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
|
|
3379 orcc(Rbox, Rscratch, G0);
|
|
3380 if (EmitSync & 65536) {
|
|
3381 Label LSucc ;
|
|
3382 brx(Assembler::notZero, false, Assembler::pn, LSucc);
|
|
3383 delayed()->nop();
|
|
3384 ba(done);
|
|
3385 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3386
|
|
3387 bind(LSucc);
|
|
3388 st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3389 if (os::is_MP()) { membar (StoreLoad); }
|
|
3390 ld_ptr(Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
|
|
3391 andcc(Rscratch, Rscratch, G0);
|
|
3392 brx(Assembler::notZero, false, Assembler::pt, done);
|
|
3393 delayed()->andcc(G0, G0, G0);
|
|
3394 add(Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark);
|
|
3395 mov(G2_thread, Rscratch);
|
|
3396 casn(Rmark, G0, Rscratch);
|
|
3397 // invert icc.zf and goto done
|
|
3398 br_notnull(Rscratch, false, Assembler::pt, done);
|
|
3399 delayed()->cmp(G0, G0);
|
|
3400 ba(done);
|
|
3401 delayed()->cmp(G0, 1);
|
|
3402 } else {
|
|
3403 brx(Assembler::notZero, false, Assembler::pn, done);
|
|
3404 delayed()->nop();
|
|
3405 ba(done);
|
|
3406 delayed()->st_ptr(G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
|
|
3407 }
|
|
3408
|
|
3409 bind (LStacked);
|
|
3410 // Consider: we could replace the expensive CAS in the exit
|
|
3411 // path with a simple ST of the displaced mark value fetched from
|
|
3412 // the on-stack basiclock box. That admits a race where a thread T2
|
|
3413 // in the slow lock path -- inflating with monitor M -- could race a
|
|
3414 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
|
|
3415 // More precisely T1 in the stack-lock unlock path could "stomp" the
|
|
3416 // inflated mark value M installed by T2, resulting in an orphan
|
|
3417 // object monitor M and T2 becoming stranded. We can remedy that situation
|
|
3418 // by having T2 periodically poll the object's mark word using timed wait
|
|
3419 // operations. If T2 discovers that a stomp has occurred it vacates
|
|
3420 // the monitor M and wakes any other threads stranded on the now-orphan M.
|
|
3421 // In addition the monitor scavenger, which performs deflation,
|
|
3422 // would also need to check for orpan monitors and stranded threads.
|
|
3423 //
|
|
3424 // Finally, inflation is also used when T2 needs to assign a hashCode
|
|
3425 // to O and O is stack-locked by T1. The "stomp" race could cause
|
|
3426 // an assigned hashCode value to be lost. We can avoid that condition
|
|
3427 // and provide the necessary hashCode stability invariants by ensuring
|
|
3428 // that hashCode generation is idempotent between copying GCs.
|
|
3429 // For example we could compute the hashCode of an object O as
|
|
3430 // O's heap address XOR some high quality RNG value that is refreshed
|
|
3431 // at GC-time. The monitor scavenger would install the hashCode
|
|
3432 // found in any orphan monitors. Again, the mechanism admits a
|
|
3433 // lost-update "stomp" WAW race but detects and recovers as needed.
|
|
3434 //
|
|
3435 // A prototype implementation showed excellent results, although
|
|
3436 // the scavenger and timeout code was rather involved.
|
|
3437
|
|
3438 casn(mark_addr.base(), Rbox, Rscratch);
|
|
3439 cmp(Rbox, Rscratch);
|
|
3440 // Intentional fall through into done ...
|
|
3441
|
|
3442 bind(done);
|
|
3443 }
|
|
3444
|
|
3445
|
|
3446
|
|
3447 void MacroAssembler::print_CPU_state() {
|
|
3448 // %%%%% need to implement this
|
|
3449 }
|
|
3450
|
|
3451 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
|
|
3452 // %%%%% need to implement this
|
|
3453 }
|
|
3454
|
|
3455 void MacroAssembler::push_IU_state() {
|
|
3456 // %%%%% need to implement this
|
|
3457 }
|
|
3458
|
|
3459
|
|
3460 void MacroAssembler::pop_IU_state() {
|
|
3461 // %%%%% need to implement this
|
|
3462 }
|
|
3463
|
|
3464
|
|
3465 void MacroAssembler::push_FPU_state() {
|
|
3466 // %%%%% need to implement this
|
|
3467 }
|
|
3468
|
|
3469
|
|
3470 void MacroAssembler::pop_FPU_state() {
|
|
3471 // %%%%% need to implement this
|
|
3472 }
|
|
3473
|
|
3474
|
|
3475 void MacroAssembler::push_CPU_state() {
|
|
3476 // %%%%% need to implement this
|
|
3477 }
|
|
3478
|
|
3479
|
|
3480 void MacroAssembler::pop_CPU_state() {
|
|
3481 // %%%%% need to implement this
|
|
3482 }
|
|
3483
|
|
3484
|
|
3485
|
|
3486 void MacroAssembler::verify_tlab() {
|
|
3487 #ifdef ASSERT
|
|
3488 if (UseTLAB && VerifyOops) {
|
|
3489 Label next, next2, ok;
|
|
3490 Register t1 = L0;
|
|
3491 Register t2 = L1;
|
|
3492 Register t3 = L2;
|
|
3493
|
|
3494 save_frame(0);
|
|
3495 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
|
|
3496 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
|
|
3497 or3(t1, t2, t3);
|
|
3498 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next);
|
|
3499 STOP("assert(top >= start)");
|
|
3500 should_not_reach_here();
|
|
3501
|
|
3502 bind(next);
|
|
3503 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
|
|
3504 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
|
|
3505 or3(t3, t2, t3);
|
|
3506 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2);
|
|
3507 STOP("assert(top <= end)");
|
|
3508 should_not_reach_here();
|
|
3509
|
|
3510 bind(next2);
|
|
3511 and3(t3, MinObjAlignmentInBytesMask, t3);
|
|
3512 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok);
|
|
3513 STOP("assert(aligned)");
|
|
3514 should_not_reach_here();
|
|
3515
|
|
3516 bind(ok);
|
|
3517 restore();
|
|
3518 }
|
|
3519 #endif
|
|
3520 }
|
|
3521
|
|
3522
|
|
3523 void MacroAssembler::eden_allocate(
|
|
3524 Register obj, // result: pointer to object after successful allocation
|
|
3525 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
3526 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
3527 Register t1, // temp register
|
|
3528 Register t2, // temp register
|
|
3529 Label& slow_case // continuation point if fast allocation fails
|
|
3530 ){
|
|
3531 // make sure arguments make sense
|
|
3532 assert_different_registers(obj, var_size_in_bytes, t1, t2);
|
|
3533 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
|
|
3534 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
|
|
3535
|
|
3536 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
|
|
3537 // No allocation in the shared eden.
|
|
3538 ba_short(slow_case);
|
|
3539 } else {
|
|
3540 // get eden boundaries
|
|
3541 // note: we need both top & top_addr!
|
|
3542 const Register top_addr = t1;
|
|
3543 const Register end = t2;
|
|
3544
|
|
3545 CollectedHeap* ch = Universe::heap();
|
|
3546 set((intx)ch->top_addr(), top_addr);
|
|
3547 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
|
|
3548 ld_ptr(top_addr, delta, end);
|
|
3549 ld_ptr(top_addr, 0, obj);
|
|
3550
|
|
3551 // try to allocate
|
|
3552 Label retry;
|
|
3553 bind(retry);
|
|
3554 #ifdef ASSERT
|
|
3555 // make sure eden top is properly aligned
|
|
3556 {
|
|
3557 Label L;
|
|
3558 btst(MinObjAlignmentInBytesMask, obj);
|
|
3559 br(Assembler::zero, false, Assembler::pt, L);
|
|
3560 delayed()->nop();
|
|
3561 STOP("eden top is not properly aligned");
|
|
3562 bind(L);
|
|
3563 }
|
|
3564 #endif // ASSERT
|
|
3565 const Register free = end;
|
|
3566 sub(end, obj, free); // compute amount of free space
|
|
3567 if (var_size_in_bytes->is_valid()) {
|
|
3568 // size is unknown at compile time
|
|
3569 cmp(free, var_size_in_bytes);
|
|
3570 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
|
|
3571 delayed()->add(obj, var_size_in_bytes, end);
|
|
3572 } else {
|
|
3573 // size is known at compile time
|
|
3574 cmp(free, con_size_in_bytes);
|
|
3575 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
|
|
3576 delayed()->add(obj, con_size_in_bytes, end);
|
|
3577 }
|
|
3578 // Compare obj with the value at top_addr; if still equal, swap the value of
|
|
3579 // end with the value at top_addr. If not equal, read the value at top_addr
|
|
3580 // into end.
|
|
3581 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
|
|
3582 // if someone beat us on the allocation, try again, otherwise continue
|
|
3583 cmp(obj, end);
|
|
3584 brx(Assembler::notEqual, false, Assembler::pn, retry);
|
|
3585 delayed()->mov(end, obj); // nop if successfull since obj == end
|
|
3586
|
|
3587 #ifdef ASSERT
|
|
3588 // make sure eden top is properly aligned
|
|
3589 {
|
|
3590 Label L;
|
|
3591 const Register top_addr = t1;
|
|
3592
|
|
3593 set((intx)ch->top_addr(), top_addr);
|
|
3594 ld_ptr(top_addr, 0, top_addr);
|
|
3595 btst(MinObjAlignmentInBytesMask, top_addr);
|
|
3596 br(Assembler::zero, false, Assembler::pt, L);
|
|
3597 delayed()->nop();
|
|
3598 STOP("eden top is not properly aligned");
|
|
3599 bind(L);
|
|
3600 }
|
|
3601 #endif // ASSERT
|
|
3602 }
|
|
3603 }
|
|
3604
|
|
3605
|
|
3606 void MacroAssembler::tlab_allocate(
|
|
3607 Register obj, // result: pointer to object after successful allocation
|
|
3608 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
3609 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
3610 Register t1, // temp register
|
|
3611 Label& slow_case // continuation point if fast allocation fails
|
|
3612 ){
|
|
3613 // make sure arguments make sense
|
|
3614 assert_different_registers(obj, var_size_in_bytes, t1);
|
|
3615 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
|
|
3616 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
|
|
3617
|
|
3618 const Register free = t1;
|
|
3619
|
|
3620 verify_tlab();
|
|
3621
|
|
3622 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
|
|
3623
|
|
3624 // calculate amount of free space
|
|
3625 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
|
|
3626 sub(free, obj, free);
|
|
3627
|
|
3628 Label done;
|
|
3629 if (var_size_in_bytes == noreg) {
|
|
3630 cmp(free, con_size_in_bytes);
|
|
3631 } else {
|
|
3632 cmp(free, var_size_in_bytes);
|
|
3633 }
|
|
3634 br(Assembler::less, false, Assembler::pn, slow_case);
|
|
3635 // calculate the new top pointer
|
|
3636 if (var_size_in_bytes == noreg) {
|
|
3637 delayed()->add(obj, con_size_in_bytes, free);
|
|
3638 } else {
|
|
3639 delayed()->add(obj, var_size_in_bytes, free);
|
|
3640 }
|
|
3641
|
|
3642 bind(done);
|
|
3643
|
|
3644 #ifdef ASSERT
|
|
3645 // make sure new free pointer is properly aligned
|
|
3646 {
|
|
3647 Label L;
|
|
3648 btst(MinObjAlignmentInBytesMask, free);
|
|
3649 br(Assembler::zero, false, Assembler::pt, L);
|
|
3650 delayed()->nop();
|
|
3651 STOP("updated TLAB free is not properly aligned");
|
|
3652 bind(L);
|
|
3653 }
|
|
3654 #endif // ASSERT
|
|
3655
|
|
3656 // update the tlab top pointer
|
|
3657 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
|
|
3658 verify_tlab();
|
|
3659 }
|
|
3660
|
|
3661
|
|
3662 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
|
|
3663 Register top = O0;
|
|
3664 Register t1 = G1;
|
|
3665 Register t2 = G3;
|
|
3666 Register t3 = O1;
|
|
3667 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
|
|
3668 Label do_refill, discard_tlab;
|
|
3669
|
|
3670 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
|
|
3671 // No allocation in the shared eden.
|
|
3672 ba_short(slow_case);
|
|
3673 }
|
|
3674
|
|
3675 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
|
|
3676 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
|
|
3677 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
|
|
3678
|
|
3679 // calculate amount of free space
|
|
3680 sub(t1, top, t1);
|
|
3681 srl_ptr(t1, LogHeapWordSize, t1);
|
|
3682
|
|
3683 // Retain tlab and allocate object in shared space if
|
|
3684 // the amount free in the tlab is too large to discard.
|
|
3685 cmp(t1, t2);
|
|
3686 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
|
|
3687
|
|
3688 // increment waste limit to prevent getting stuck on this slow path
|
|
3689 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
|
|
3690 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
|
|
3691 if (TLABStats) {
|
|
3692 // increment number of slow_allocations
|
|
3693 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
|
|
3694 add(t2, 1, t2);
|
|
3695 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
|
|
3696 }
|
|
3697 ba_short(try_eden);
|
|
3698
|
|
3699 bind(discard_tlab);
|
|
3700 if (TLABStats) {
|
|
3701 // increment number of refills
|
|
3702 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
|
|
3703 add(t2, 1, t2);
|
|
3704 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
|
|
3705 // accumulate wastage
|
|
3706 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
|
|
3707 add(t2, t1, t2);
|
|
3708 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
|
|
3709 }
|
|
3710
|
|
3711 // if tlab is currently allocated (top or end != null) then
|
|
3712 // fill [top, end + alignment_reserve) with array object
|
|
3713 br_null_short(top, Assembler::pn, do_refill);
|
|
3714
|
|
3715 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
|
|
3716 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
|
|
3717 // set klass to intArrayKlass
|
|
3718 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
|
|
3719 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
|
|
3720 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
|
|
3721 st(t1, top, arrayOopDesc::length_offset_in_bytes());
|
|
3722 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
|
|
3723 ld_ptr(t2, 0, t2);
|
|
3724 // store klass last. concurrent gcs assumes klass length is valid if
|
|
3725 // klass field is not null.
|
|
3726 store_klass(t2, top);
|
|
3727 verify_oop(top);
|
|
3728
|
|
3729 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1);
|
|
3730 sub(top, t1, t1); // size of tlab's allocated portion
|
|
3731 incr_allocated_bytes(t1, t2, t3);
|
|
3732
|
|
3733 // refill the tlab with an eden allocation
|
|
3734 bind(do_refill);
|
|
3735 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
|
|
3736 sll_ptr(t1, LogHeapWordSize, t1);
|
|
3737 // allocate new tlab, address returned in top
|
|
3738 eden_allocate(top, t1, 0, t2, t3, slow_case);
|
|
3739
|
|
3740 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
|
|
3741 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
|
|
3742 #ifdef ASSERT
|
|
3743 // check that tlab_size (t1) is still valid
|
|
3744 {
|
|
3745 Label ok;
|
|
3746 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
|
|
3747 sll_ptr(t2, LogHeapWordSize, t2);
|
|
3748 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok);
|
|
3749 STOP("assert(t1 == tlab_size)");
|
|
3750 should_not_reach_here();
|
|
3751
|
|
3752 bind(ok);
|
|
3753 }
|
|
3754 #endif // ASSERT
|
|
3755 add(top, t1, top); // t1 is tlab_size
|
|
3756 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
|
|
3757 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
|
|
3758 verify_tlab();
|
|
3759 ba_short(retry);
|
|
3760 }
|
|
3761
|
|
3762 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes,
|
|
3763 Register t1, Register t2) {
|
|
3764 // Bump total bytes allocated by this thread
|
|
3765 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch
|
|
3766 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2);
|
|
3767 // v8 support has gone the way of the dodo
|
|
3768 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1);
|
|
3769 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1);
|
|
3770 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset()));
|
|
3771 }
|
|
3772
|
|
3773 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
|
|
3774 switch (cond) {
|
|
3775 // Note some conditions are synonyms for others
|
|
3776 case Assembler::never: return Assembler::always;
|
|
3777 case Assembler::zero: return Assembler::notZero;
|
|
3778 case Assembler::lessEqual: return Assembler::greater;
|
|
3779 case Assembler::less: return Assembler::greaterEqual;
|
|
3780 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
|
|
3781 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
|
|
3782 case Assembler::negative: return Assembler::positive;
|
|
3783 case Assembler::overflowSet: return Assembler::overflowClear;
|
|
3784 case Assembler::always: return Assembler::never;
|
|
3785 case Assembler::notZero: return Assembler::zero;
|
|
3786 case Assembler::greater: return Assembler::lessEqual;
|
|
3787 case Assembler::greaterEqual: return Assembler::less;
|
|
3788 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
|
|
3789 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
|
|
3790 case Assembler::positive: return Assembler::negative;
|
|
3791 case Assembler::overflowClear: return Assembler::overflowSet;
|
|
3792 }
|
|
3793
|
|
3794 ShouldNotReachHere(); return Assembler::overflowClear;
|
|
3795 }
|
|
3796
|
|
3797 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
|
|
3798 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
|
|
3799 Condition negated_cond = negate_condition(cond);
|
|
3800 Label L;
|
|
3801 brx(negated_cond, false, Assembler::pt, L);
|
|
3802 delayed()->nop();
|
|
3803 inc_counter(counter_ptr, Rtmp1, Rtmp2);
|
|
3804 bind(L);
|
|
3805 }
|
|
3806
|
|
3807 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
|
|
3808 AddressLiteral addrlit(counter_addr);
|
|
3809 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
|
|
3810 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
|
|
3811 ld(addr, Rtmp2);
|
|
3812 inc(Rtmp2);
|
|
3813 st(Rtmp2, addr);
|
|
3814 }
|
|
3815
|
|
3816 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
|
|
3817 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
|
|
3818 }
|
|
3819
|
|
3820 SkipIfEqual::SkipIfEqual(
|
|
3821 MacroAssembler* masm, Register temp, const bool* flag_addr,
|
|
3822 Assembler::Condition condition) {
|
|
3823 _masm = masm;
|
|
3824 AddressLiteral flag(flag_addr);
|
|
3825 _masm->sethi(flag, temp);
|
|
3826 _masm->ldub(temp, flag.low10(), temp);
|
|
3827 _masm->tst(temp);
|
|
3828 _masm->br(condition, false, Assembler::pt, _label);
|
|
3829 _masm->delayed()->nop();
|
|
3830 }
|
|
3831
|
|
3832 SkipIfEqual::~SkipIfEqual() {
|
|
3833 _masm->bind(_label);
|
|
3834 }
|
|
3835
|
|
3836
|
|
3837 // Writes to stack successive pages until offset reached to check for
|
|
3838 // stack overflow + shadow pages. This clobbers tsp and scratch.
|
|
3839 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
|
|
3840 Register Rscratch) {
|
|
3841 // Use stack pointer in temp stack pointer
|
|
3842 mov(SP, Rtsp);
|
|
3843
|
|
3844 // Bang stack for total size given plus stack shadow page size.
|
|
3845 // Bang one page at a time because a large size can overflow yellow and
|
|
3846 // red zones (the bang will fail but stack overflow handling can't tell that
|
|
3847 // it was a stack overflow bang vs a regular segv).
|
|
3848 int offset = os::vm_page_size();
|
|
3849 Register Roffset = Rscratch;
|
|
3850
|
|
3851 Label loop;
|
|
3852 bind(loop);
|
|
3853 set((-offset)+STACK_BIAS, Rscratch);
|
|
3854 st(G0, Rtsp, Rscratch);
|
|
3855 set(offset, Roffset);
|
|
3856 sub(Rsize, Roffset, Rsize);
|
|
3857 cmp(Rsize, G0);
|
|
3858 br(Assembler::greater, false, Assembler::pn, loop);
|
|
3859 delayed()->sub(Rtsp, Roffset, Rtsp);
|
|
3860
|
|
3861 // Bang down shadow pages too.
|
|
3862 // The -1 because we already subtracted 1 page.
|
|
3863 for (int i = 0; i< StackShadowPages-1; i++) {
|
|
3864 set((-i*offset)+STACK_BIAS, Rscratch);
|
|
3865 st(G0, Rtsp, Rscratch);
|
|
3866 }
|
|
3867 }
|
|
3868
|
|
3869 ///////////////////////////////////////////////////////////////////////////////////
|
|
3870 #ifndef SERIALGC
|
|
3871
|
|
3872 static address satb_log_enqueue_with_frame = NULL;
|
|
3873 static u_char* satb_log_enqueue_with_frame_end = NULL;
|
|
3874
|
|
3875 static address satb_log_enqueue_frameless = NULL;
|
|
3876 static u_char* satb_log_enqueue_frameless_end = NULL;
|
|
3877
|
|
3878 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
|
|
3879
|
|
3880 static void generate_satb_log_enqueue(bool with_frame) {
|
|
3881 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
|
|
3882 CodeBuffer buf(bb);
|
|
3883 MacroAssembler masm(&buf);
|
|
3884
|
|
3885 #define __ masm.
|
|
3886
|
|
3887 address start = __ pc();
|
|
3888 Register pre_val;
|
|
3889
|
|
3890 Label refill, restart;
|
|
3891 if (with_frame) {
|
|
3892 __ save_frame(0);
|
|
3893 pre_val = I0; // Was O0 before the save.
|
|
3894 } else {
|
|
3895 pre_val = O0;
|
|
3896 }
|
|
3897
|
|
3898 int satb_q_index_byte_offset =
|
|
3899 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
3900 PtrQueue::byte_offset_of_index());
|
|
3901
|
|
3902 int satb_q_buf_byte_offset =
|
|
3903 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
3904 PtrQueue::byte_offset_of_buf());
|
|
3905
|
|
3906 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
|
|
3907 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
|
|
3908 "check sizes in assembly below");
|
|
3909
|
|
3910 __ bind(restart);
|
|
3911
|
|
3912 // Load the index into the SATB buffer. PtrQueue::_index is a size_t
|
|
3913 // so ld_ptr is appropriate.
|
|
3914 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
|
|
3915
|
|
3916 // index == 0?
|
|
3917 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
|
|
3918
|
|
3919 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
|
|
3920 __ sub(L0, oopSize, L0);
|
|
3921
|
|
3922 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0
|
|
3923 if (!with_frame) {
|
|
3924 // Use return-from-leaf
|
|
3925 __ retl();
|
|
3926 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
|
|
3927 } else {
|
|
3928 // Not delayed.
|
|
3929 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset);
|
|
3930 }
|
|
3931 if (with_frame) {
|
|
3932 __ ret();
|
|
3933 __ delayed()->restore();
|
|
3934 }
|
|
3935 __ bind(refill);
|
|
3936
|
|
3937 address handle_zero =
|
|
3938 CAST_FROM_FN_PTR(address,
|
|
3939 &SATBMarkQueueSet::handle_zero_index_for_thread);
|
|
3940 // This should be rare enough that we can afford to save all the
|
|
3941 // scratch registers that the calling context might be using.
|
|
3942 __ mov(G1_scratch, L0);
|
|
3943 __ mov(G3_scratch, L1);
|
|
3944 __ mov(G4, L2);
|
|
3945 // We need the value of O0 above (for the write into the buffer), so we
|
|
3946 // save and restore it.
|
|
3947 __ mov(O0, L3);
|
|
3948 // Since the call will overwrite O7, we save and restore that, as well.
|
|
3949 __ mov(O7, L4);
|
|
3950 __ call_VM_leaf(L5, handle_zero, G2_thread);
|
|
3951 __ mov(L0, G1_scratch);
|
|
3952 __ mov(L1, G3_scratch);
|
|
3953 __ mov(L2, G4);
|
|
3954 __ mov(L3, O0);
|
|
3955 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
|
|
3956 __ delayed()->mov(L4, O7);
|
|
3957
|
|
3958 if (with_frame) {
|
|
3959 satb_log_enqueue_with_frame = start;
|
|
3960 satb_log_enqueue_with_frame_end = __ pc();
|
|
3961 } else {
|
|
3962 satb_log_enqueue_frameless = start;
|
|
3963 satb_log_enqueue_frameless_end = __ pc();
|
|
3964 }
|
|
3965
|
|
3966 #undef __
|
|
3967 }
|
|
3968
|
|
3969 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
|
|
3970 if (with_frame) {
|
|
3971 if (satb_log_enqueue_with_frame == 0) {
|
|
3972 generate_satb_log_enqueue(with_frame);
|
|
3973 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
|
|
3974 if (G1SATBPrintStubs) {
|
|
3975 tty->print_cr("Generated with-frame satb enqueue:");
|
|
3976 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
|
|
3977 satb_log_enqueue_with_frame_end,
|
|
3978 tty);
|
|
3979 }
|
|
3980 }
|
|
3981 } else {
|
|
3982 if (satb_log_enqueue_frameless == 0) {
|
|
3983 generate_satb_log_enqueue(with_frame);
|
|
3984 assert(satb_log_enqueue_frameless != 0, "postcondition.");
|
|
3985 if (G1SATBPrintStubs) {
|
|
3986 tty->print_cr("Generated frameless satb enqueue:");
|
|
3987 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
|
|
3988 satb_log_enqueue_frameless_end,
|
|
3989 tty);
|
|
3990 }
|
|
3991 }
|
|
3992 }
|
|
3993 }
|
|
3994
|
|
3995 void MacroAssembler::g1_write_barrier_pre(Register obj,
|
|
3996 Register index,
|
|
3997 int offset,
|
|
3998 Register pre_val,
|
|
3999 Register tmp,
|
|
4000 bool preserve_o_regs) {
|
|
4001 Label filtered;
|
|
4002
|
|
4003 if (obj == noreg) {
|
|
4004 // We are not loading the previous value so make
|
|
4005 // sure that we don't trash the value in pre_val
|
|
4006 // with the code below.
|
|
4007 assert_different_registers(pre_val, tmp);
|
|
4008 } else {
|
|
4009 // We will be loading the previous value
|
|
4010 // in this code so...
|
|
4011 assert(offset == 0 || index == noreg, "choose one");
|
|
4012 assert(pre_val == noreg, "check this code");
|
|
4013 }
|
|
4014
|
|
4015 // Is marking active?
|
|
4016 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
|
|
4017 ld(G2,
|
|
4018 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
4019 PtrQueue::byte_offset_of_active()),
|
|
4020 tmp);
|
|
4021 } else {
|
|
4022 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
|
|
4023 "Assumption");
|
|
4024 ldsb(G2,
|
|
4025 in_bytes(JavaThread::satb_mark_queue_offset() +
|
|
4026 PtrQueue::byte_offset_of_active()),
|
|
4027 tmp);
|
|
4028 }
|
|
4029
|
|
4030 // Is marking active?
|
|
4031 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4032
|
|
4033 // Do we need to load the previous value?
|
|
4034 if (obj != noreg) {
|
|
4035 // Load the previous value...
|
|
4036 if (index == noreg) {
|
|
4037 if (Assembler::is_simm13(offset)) {
|
|
4038 load_heap_oop(obj, offset, tmp);
|
|
4039 } else {
|
|
4040 set(offset, tmp);
|
|
4041 load_heap_oop(obj, tmp, tmp);
|
|
4042 }
|
|
4043 } else {
|
|
4044 load_heap_oop(obj, index, tmp);
|
|
4045 }
|
|
4046 // Previous value has been loaded into tmp
|
|
4047 pre_val = tmp;
|
|
4048 }
|
|
4049
|
|
4050 assert(pre_val != noreg, "must have a real register");
|
|
4051
|
|
4052 // Is the previous value null?
|
|
4053 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4054
|
|
4055 // OK, it's not filtered, so we'll need to call enqueue. In the normal
|
|
4056 // case, pre_val will be a scratch G-reg, but there are some cases in
|
|
4057 // which it's an O-reg. In the first case, do a normal call. In the
|
|
4058 // latter, do a save here and call the frameless version.
|
|
4059
|
|
4060 guarantee(pre_val->is_global() || pre_val->is_out(),
|
|
4061 "Or we need to think harder.");
|
|
4062
|
|
4063 if (pre_val->is_global() && !preserve_o_regs) {
|
|
4064 generate_satb_log_enqueue_if_necessary(true); // with frame
|
|
4065
|
|
4066 call(satb_log_enqueue_with_frame);
|
|
4067 delayed()->mov(pre_val, O0);
|
|
4068 } else {
|
|
4069 generate_satb_log_enqueue_if_necessary(false); // frameless
|
|
4070
|
|
4071 save_frame(0);
|
|
4072 call(satb_log_enqueue_frameless);
|
|
4073 delayed()->mov(pre_val->after_save(), O0);
|
|
4074 restore();
|
|
4075 }
|
|
4076
|
|
4077 bind(filtered);
|
|
4078 }
|
|
4079
|
|
4080 static address dirty_card_log_enqueue = 0;
|
|
4081 static u_char* dirty_card_log_enqueue_end = 0;
|
|
4082
|
|
4083 // This gets to assume that o0 contains the object address.
|
|
4084 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
|
|
4085 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
|
|
4086 CodeBuffer buf(bb);
|
|
4087 MacroAssembler masm(&buf);
|
|
4088 #define __ masm.
|
|
4089 address start = __ pc();
|
|
4090
|
|
4091 Label not_already_dirty, restart, refill;
|
|
4092
|
|
4093 #ifdef _LP64
|
|
4094 __ srlx(O0, CardTableModRefBS::card_shift, O0);
|
|
4095 #else
|
|
4096 __ srl(O0, CardTableModRefBS::card_shift, O0);
|
|
4097 #endif
|
|
4098 AddressLiteral addrlit(byte_map_base);
|
|
4099 __ set(addrlit, O1); // O1 := <card table base>
|
|
4100 __ ldub(O0, O1, O2); // O2 := [O0 + O1]
|
|
4101
|
|
4102 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code");
|
|
4103 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty);
|
|
4104
|
|
4105 // We didn't take the branch, so we're already dirty: return.
|
|
4106 // Use return-from-leaf
|
|
4107 __ retl();
|
|
4108 __ delayed()->nop();
|
|
4109
|
|
4110 // Not dirty.
|
|
4111 __ bind(not_already_dirty);
|
|
4112
|
|
4113 // Get O0 + O1 into a reg by itself
|
|
4114 __ add(O0, O1, O3);
|
|
4115
|
|
4116 // First, dirty it.
|
|
4117 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
|
|
4118
|
|
4119 int dirty_card_q_index_byte_offset =
|
|
4120 in_bytes(JavaThread::dirty_card_queue_offset() +
|
|
4121 PtrQueue::byte_offset_of_index());
|
|
4122 int dirty_card_q_buf_byte_offset =
|
|
4123 in_bytes(JavaThread::dirty_card_queue_offset() +
|
|
4124 PtrQueue::byte_offset_of_buf());
|
|
4125 __ bind(restart);
|
|
4126
|
|
4127 // Load the index into the update buffer. PtrQueue::_index is
|
|
4128 // a size_t so ld_ptr is appropriate here.
|
|
4129 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
|
|
4130
|
|
4131 // index == 0?
|
|
4132 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill);
|
|
4133
|
|
4134 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
|
|
4135 __ sub(L0, oopSize, L0);
|
|
4136
|
|
4137 __ st_ptr(O3, L1, L0); // [_buf + index] := I0
|
|
4138 // Use return-from-leaf
|
|
4139 __ retl();
|
|
4140 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
|
|
4141
|
|
4142 __ bind(refill);
|
|
4143 address handle_zero =
|
|
4144 CAST_FROM_FN_PTR(address,
|
|
4145 &DirtyCardQueueSet::handle_zero_index_for_thread);
|
|
4146 // This should be rare enough that we can afford to save all the
|
|
4147 // scratch registers that the calling context might be using.
|
|
4148 __ mov(G1_scratch, L3);
|
|
4149 __ mov(G3_scratch, L5);
|
|
4150 // We need the value of O3 above (for the write into the buffer), so we
|
|
4151 // save and restore it.
|
|
4152 __ mov(O3, L6);
|
|
4153 // Since the call will overwrite O7, we save and restore that, as well.
|
|
4154 __ mov(O7, L4);
|
|
4155
|
|
4156 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
|
|
4157 __ mov(L3, G1_scratch);
|
|
4158 __ mov(L5, G3_scratch);
|
|
4159 __ mov(L6, O3);
|
|
4160 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart);
|
|
4161 __ delayed()->mov(L4, O7);
|
|
4162
|
|
4163 dirty_card_log_enqueue = start;
|
|
4164 dirty_card_log_enqueue_end = __ pc();
|
|
4165 // XXX Should have a guarantee here about not going off the end!
|
|
4166 // Does it already do so? Do an experiment...
|
|
4167
|
|
4168 #undef __
|
|
4169
|
|
4170 }
|
|
4171
|
|
4172 static inline void
|
|
4173 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
|
|
4174 if (dirty_card_log_enqueue == 0) {
|
|
4175 generate_dirty_card_log_enqueue(byte_map_base);
|
|
4176 assert(dirty_card_log_enqueue != 0, "postcondition.");
|
|
4177 if (G1SATBPrintStubs) {
|
|
4178 tty->print_cr("Generated dirty_card enqueue:");
|
|
4179 Disassembler::decode((u_char*)dirty_card_log_enqueue,
|
|
4180 dirty_card_log_enqueue_end,
|
|
4181 tty);
|
|
4182 }
|
|
4183 }
|
|
4184 }
|
|
4185
|
|
4186
|
|
4187 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
|
|
4188
|
|
4189 Label filtered;
|
|
4190 MacroAssembler* post_filter_masm = this;
|
|
4191
|
|
4192 if (new_val == G0) return;
|
|
4193
|
|
4194 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
|
|
4195 assert(bs->kind() == BarrierSet::G1SATBCT ||
|
|
4196 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
|
|
4197
|
|
4198 if (G1RSBarrierRegionFilter) {
|
|
4199 xor3(store_addr, new_val, tmp);
|
|
4200 #ifdef _LP64
|
|
4201 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
|
|
4202 #else
|
|
4203 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
|
|
4204 #endif
|
|
4205
|
|
4206 // XXX Should I predict this taken or not? Does it matter?
|
|
4207 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered);
|
|
4208 }
|
|
4209
|
|
4210 // If the "store_addr" register is an "in" or "local" register, move it to
|
|
4211 // a scratch reg so we can pass it as an argument.
|
|
4212 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
|
|
4213 // Pick a scratch register different from "tmp".
|
|
4214 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
|
|
4215 // Make sure we use up the delay slot!
|
|
4216 if (use_scr) {
|
|
4217 post_filter_masm->mov(store_addr, scr);
|
|
4218 } else {
|
|
4219 post_filter_masm->nop();
|
|
4220 }
|
|
4221 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
|
|
4222 save_frame(0);
|
|
4223 call(dirty_card_log_enqueue);
|
|
4224 if (use_scr) {
|
|
4225 delayed()->mov(scr, O0);
|
|
4226 } else {
|
|
4227 delayed()->mov(store_addr->after_save(), O0);
|
|
4228 }
|
|
4229 restore();
|
|
4230
|
|
4231 bind(filtered);
|
|
4232 }
|
|
4233
|
|
4234 #endif // SERIALGC
|
|
4235 ///////////////////////////////////////////////////////////////////////////////////
|
|
4236
|
|
4237 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
|
|
4238 // If we're writing constant NULL, we can skip the write barrier.
|
|
4239 if (new_val == G0) return;
|
|
4240 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
|
|
4241 assert(bs->kind() == BarrierSet::CardTableModRef ||
|
|
4242 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
|
|
4243 card_table_write(bs->byte_map_base, tmp, store_addr);
|
|
4244 }
|
|
4245
|
|
4246 void MacroAssembler::load_klass(Register src_oop, Register klass) {
|
|
4247 // The number of bytes in this code is used by
|
|
4248 // MachCallDynamicJavaNode::ret_addr_offset()
|
|
4249 // if this changes, change that.
|
|
4250 if (UseCompressedKlassPointers) {
|
|
4251 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
|
|
4252 decode_klass_not_null(klass);
|
|
4253 } else {
|
|
4254 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
|
|
4255 }
|
|
4256 }
|
|
4257
|
|
4258 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
|
|
4259 if (UseCompressedKlassPointers) {
|
|
4260 assert(dst_oop != klass, "not enough registers");
|
|
4261 encode_klass_not_null(klass);
|
|
4262 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
|
|
4263 } else {
|
|
4264 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
|
|
4265 }
|
|
4266 }
|
|
4267
|
|
4268 void MacroAssembler::store_klass_gap(Register s, Register d) {
|
|
4269 if (UseCompressedKlassPointers) {
|
|
4270 assert(s != d, "not enough registers");
|
|
4271 st(s, d, oopDesc::klass_gap_offset_in_bytes());
|
|
4272 }
|
|
4273 }
|
|
4274
|
|
4275 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
|
|
4276 if (UseCompressedOops) {
|
|
4277 lduw(s, d);
|
|
4278 decode_heap_oop(d);
|
|
4279 } else {
|
|
4280 ld_ptr(s, d);
|
|
4281 }
|
|
4282 }
|
|
4283
|
|
4284 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
|
|
4285 if (UseCompressedOops) {
|
|
4286 lduw(s1, s2, d);
|
|
4287 decode_heap_oop(d, d);
|
|
4288 } else {
|
|
4289 ld_ptr(s1, s2, d);
|
|
4290 }
|
|
4291 }
|
|
4292
|
|
4293 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
|
|
4294 if (UseCompressedOops) {
|
|
4295 lduw(s1, simm13a, d);
|
|
4296 decode_heap_oop(d, d);
|
|
4297 } else {
|
|
4298 ld_ptr(s1, simm13a, d);
|
|
4299 }
|
|
4300 }
|
|
4301
|
|
4302 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) {
|
|
4303 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d);
|
|
4304 else load_heap_oop(s1, s2.as_register(), d);
|
|
4305 }
|
|
4306
|
|
4307 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
|
|
4308 if (UseCompressedOops) {
|
|
4309 assert(s1 != d && s2 != d, "not enough registers");
|
|
4310 encode_heap_oop(d);
|
|
4311 st(d, s1, s2);
|
|
4312 } else {
|
|
4313 st_ptr(d, s1, s2);
|
|
4314 }
|
|
4315 }
|
|
4316
|
|
4317 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
|
|
4318 if (UseCompressedOops) {
|
|
4319 assert(s1 != d, "not enough registers");
|
|
4320 encode_heap_oop(d);
|
|
4321 st(d, s1, simm13a);
|
|
4322 } else {
|
|
4323 st_ptr(d, s1, simm13a);
|
|
4324 }
|
|
4325 }
|
|
4326
|
|
4327 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
|
|
4328 if (UseCompressedOops) {
|
|
4329 assert(a.base() != d, "not enough registers");
|
|
4330 encode_heap_oop(d);
|
|
4331 st(d, a, offset);
|
|
4332 } else {
|
|
4333 st_ptr(d, a, offset);
|
|
4334 }
|
|
4335 }
|
|
4336
|
|
4337
|
|
4338 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
|
|
4339 assert (UseCompressedOops, "must be compressed");
|
|
4340 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4341 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4342 verify_oop(src);
|
|
4343 if (Universe::narrow_oop_base() == NULL) {
|
|
4344 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4345 return;
|
|
4346 }
|
|
4347 Label done;
|
|
4348 if (src == dst) {
|
|
4349 // optimize for frequent case src == dst
|
|
4350 bpr(rc_nz, true, Assembler::pt, src, done);
|
|
4351 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
|
|
4352 bind(done);
|
|
4353 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4354 } else {
|
|
4355 bpr(rc_z, false, Assembler::pn, src, done);
|
|
4356 delayed() -> mov(G0, dst);
|
|
4357 // could be moved before branch, and annulate delay,
|
|
4358 // but may add some unneeded work decoding null
|
|
4359 sub(src, G6_heapbase, dst);
|
|
4360 srlx(dst, LogMinObjAlignmentInBytes, dst);
|
|
4361 bind(done);
|
|
4362 }
|
|
4363 }
|
|
4364
|
|
4365
|
|
4366 void MacroAssembler::encode_heap_oop_not_null(Register r) {
|
|
4367 assert (UseCompressedOops, "must be compressed");
|
|
4368 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4369 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4370 verify_oop(r);
|
|
4371 if (Universe::narrow_oop_base() != NULL)
|
|
4372 sub(r, G6_heapbase, r);
|
|
4373 srlx(r, LogMinObjAlignmentInBytes, r);
|
|
4374 }
|
|
4375
|
|
4376 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
|
|
4377 assert (UseCompressedOops, "must be compressed");
|
|
4378 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4379 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4380 verify_oop(src);
|
|
4381 if (Universe::narrow_oop_base() == NULL) {
|
|
4382 srlx(src, LogMinObjAlignmentInBytes, dst);
|
|
4383 } else {
|
|
4384 sub(src, G6_heapbase, dst);
|
|
4385 srlx(dst, LogMinObjAlignmentInBytes, dst);
|
|
4386 }
|
|
4387 }
|
|
4388
|
|
4389 // Same algorithm as oops.inline.hpp decode_heap_oop.
|
|
4390 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
|
|
4391 assert (UseCompressedOops, "must be compressed");
|
|
4392 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4393 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4394 sllx(src, LogMinObjAlignmentInBytes, dst);
|
|
4395 if (Universe::narrow_oop_base() != NULL) {
|
|
4396 Label done;
|
|
4397 bpr(rc_nz, true, Assembler::pt, dst, done);
|
|
4398 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
|
|
4399 bind(done);
|
|
4400 }
|
|
4401 verify_oop(dst);
|
|
4402 }
|
|
4403
|
|
4404 void MacroAssembler::decode_heap_oop_not_null(Register r) {
|
|
4405 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4406 // pd_code_size_limit.
|
|
4407 // Also do not verify_oop as this is called by verify_oop.
|
|
4408 assert (UseCompressedOops, "must be compressed");
|
|
4409 assert (Universe::heap() != NULL, "java heap should be initialized");
|
|
4410 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4411 sllx(r, LogMinObjAlignmentInBytes, r);
|
|
4412 if (Universe::narrow_oop_base() != NULL)
|
|
4413 add(r, G6_heapbase, r);
|
|
4414 }
|
|
4415
|
|
4416 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
|
|
4417 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4418 // pd_code_size_limit.
|
|
4419 // Also do not verify_oop as this is called by verify_oop.
|
|
4420 assert (UseCompressedOops, "must be compressed");
|
|
4421 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
|
|
4422 sllx(src, LogMinObjAlignmentInBytes, dst);
|
|
4423 if (Universe::narrow_oop_base() != NULL)
|
|
4424 add(dst, G6_heapbase, dst);
|
|
4425 }
|
|
4426
|
|
4427 void MacroAssembler::encode_klass_not_null(Register r) {
|
|
4428 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4429 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4430 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4431 if (Universe::narrow_klass_base() != NULL)
|
|
4432 sub(r, G6_heapbase, r);
|
|
4433 srlx(r, LogKlassAlignmentInBytes, r);
|
|
4434 }
|
|
4435
|
|
4436 void MacroAssembler::encode_klass_not_null(Register src, Register dst) {
|
|
4437 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4438 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4439 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4440 if (Universe::narrow_klass_base() == NULL) {
|
|
4441 srlx(src, LogKlassAlignmentInBytes, dst);
|
|
4442 } else {
|
|
4443 sub(src, G6_heapbase, dst);
|
|
4444 srlx(dst, LogKlassAlignmentInBytes, dst);
|
|
4445 }
|
|
4446 }
|
|
4447
|
|
4448 void MacroAssembler::decode_klass_not_null(Register r) {
|
|
4449 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4450 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4451 // pd_code_size_limit.
|
|
4452 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4453 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4454 sllx(r, LogKlassAlignmentInBytes, r);
|
|
4455 if (Universe::narrow_klass_base() != NULL)
|
|
4456 add(r, G6_heapbase, r);
|
|
4457 }
|
|
4458
|
|
4459 void MacroAssembler::decode_klass_not_null(Register src, Register dst) {
|
|
4460 assert(Metaspace::is_initialized(), "metaspace should be initialized");
|
|
4461 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
|
|
4462 // pd_code_size_limit.
|
|
4463 assert (UseCompressedKlassPointers, "must be compressed");
|
|
4464 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
|
|
4465 sllx(src, LogKlassAlignmentInBytes, dst);
|
|
4466 if (Universe::narrow_klass_base() != NULL)
|
|
4467 add(dst, G6_heapbase, dst);
|
|
4468 }
|
|
4469
|
|
4470 void MacroAssembler::reinit_heapbase() {
|
|
4471 if (UseCompressedOops || UseCompressedKlassPointers) {
|
|
4472 AddressLiteral base(Universe::narrow_ptrs_base_addr());
|
|
4473 load_ptr_contents(base, G6_heapbase);
|
|
4474 }
|
|
4475 }
|
|
4476
|
|
4477 // Compare char[] arrays aligned to 4 bytes.
|
|
4478 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
|
|
4479 Register limit, Register result,
|
|
4480 Register chr1, Register chr2, Label& Ldone) {
|
|
4481 Label Lvector, Lloop;
|
|
4482 assert(chr1 == result, "should be the same");
|
|
4483
|
|
4484 // Note: limit contains number of bytes (2*char_elements) != 0.
|
|
4485 andcc(limit, 0x2, chr1); // trailing character ?
|
|
4486 br(Assembler::zero, false, Assembler::pt, Lvector);
|
|
4487 delayed()->nop();
|
|
4488
|
|
4489 // compare the trailing char
|
|
4490 sub(limit, sizeof(jchar), limit);
|
|
4491 lduh(ary1, limit, chr1);
|
|
4492 lduh(ary2, limit, chr2);
|
|
4493 cmp(chr1, chr2);
|
|
4494 br(Assembler::notEqual, true, Assembler::pt, Ldone);
|
|
4495 delayed()->mov(G0, result); // not equal
|
|
4496
|
|
4497 // only one char ?
|
|
4498 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn);
|
|
4499 delayed()->add(G0, 1, result); // zero-length arrays are equal
|
|
4500
|
|
4501 // word by word compare, dont't need alignment check
|
|
4502 bind(Lvector);
|
|
4503 // Shift ary1 and ary2 to the end of the arrays, negate limit
|
|
4504 add(ary1, limit, ary1);
|
|
4505 add(ary2, limit, ary2);
|
|
4506 neg(limit, limit);
|
|
4507
|
|
4508 lduw(ary1, limit, chr1);
|
|
4509 bind(Lloop);
|
|
4510 lduw(ary2, limit, chr2);
|
|
4511 cmp(chr1, chr2);
|
|
4512 br(Assembler::notEqual, true, Assembler::pt, Ldone);
|
|
4513 delayed()->mov(G0, result); // not equal
|
|
4514 inccc(limit, 2*sizeof(jchar));
|
|
4515 // annul LDUW if branch is not taken to prevent access past end of array
|
|
4516 br(Assembler::notZero, true, Assembler::pt, Lloop);
|
|
4517 delayed()->lduw(ary1, limit, chr1); // hoisted
|
|
4518
|
|
4519 // Caller should set it:
|
|
4520 // add(G0, 1, result); // equals
|
|
4521 }
|
|
4522
|
|
4523 // Use BIS for zeroing (count is in bytes).
|
|
4524 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) {
|
|
4525 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing");
|
|
4526 Register end = count;
|
|
4527 int cache_line_size = VM_Version::prefetch_data_size();
|
|
4528 // Minimum count when BIS zeroing can be used since
|
|
4529 // it needs membar which is expensive.
|
|
4530 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit);
|
|
4531
|
|
4532 Label small_loop;
|
|
4533 // Check if count is negative (dead code) or zero.
|
|
4534 // Note, count uses 64bit in 64 bit VM.
|
|
4535 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone);
|
|
4536
|
|
4537 // Use BIS zeroing only for big arrays since it requires membar.
|
|
4538 if (Assembler::is_simm13(block_zero_size)) { // < 4096
|
|
4539 cmp(count, block_zero_size);
|
|
4540 } else {
|
|
4541 set(block_zero_size, temp);
|
|
4542 cmp(count, temp);
|
|
4543 }
|
|
4544 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop);
|
|
4545 delayed()->add(to, count, end);
|
|
4546
|
|
4547 // Note: size is >= three (32 bytes) cache lines.
|
|
4548
|
|
4549 // Clean the beginning of space up to next cache line.
|
|
4550 for (int offs = 0; offs < cache_line_size; offs += 8) {
|
|
4551 stx(G0, to, offs);
|
|
4552 }
|
|
4553
|
|
4554 // align to next cache line
|
|
4555 add(to, cache_line_size, to);
|
|
4556 and3(to, -cache_line_size, to);
|
|
4557
|
|
4558 // Note: size left >= two (32 bytes) cache lines.
|
|
4559
|
|
4560 // BIS should not be used to zero tail (64 bytes)
|
|
4561 // to avoid zeroing a header of the following object.
|
|
4562 sub(end, (cache_line_size*2)-8, end);
|
|
4563
|
|
4564 Label bis_loop;
|
|
4565 bind(bis_loop);
|
|
4566 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
|
|
4567 add(to, cache_line_size, to);
|
|
4568 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop);
|
|
4569
|
|
4570 // BIS needs membar.
|
|
4571 membar(Assembler::StoreLoad);
|
|
4572
|
|
4573 add(end, (cache_line_size*2)-8, end); // restore end
|
|
4574 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone);
|
|
4575
|
|
4576 // Clean the tail.
|
|
4577 bind(small_loop);
|
|
4578 stx(G0, to, 0);
|
|
4579 add(to, 8, to);
|
|
4580 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop);
|
|
4581 nop(); // Separate short branches
|
|
4582 }
|