Mercurial > hg > graal-jvmci-8
annotate src/share/vm/opto/regmask.hpp @ 23886:5601e440e5e7
8130150: Implement BigInteger.montgomeryMultiply intrinsic
Reviewed-by: kvn, mdoerr
| author | vkempik |
|---|---|
| date | Fri, 04 Mar 2016 16:15:48 +0300 |
| parents | ddce0b7cee93 |
| children | dd9cc155639c |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_OPTO_REGMASK_HPP |
| 26 #define SHARE_VM_OPTO_REGMASK_HPP | |
| 27 | |
| 28 #include "code/vmreg.hpp" | |
| 29 #include "libadt/port.hpp" | |
| 30 #include "opto/optoreg.hpp" | |
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31 #if defined ADGLOBALS_MD_HPP |
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32 # include ADGLOBALS_MD_HPP |
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33 #elif defined TARGET_ARCH_MODEL_x86_32 |
| 1972 | 34 # include "adfiles/adGlobals_x86_32.hpp" |
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35 #elif defined TARGET_ARCH_MODEL_x86_64 |
| 1972 | 36 # include "adfiles/adGlobals_x86_64.hpp" |
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37 #elif defined TARGET_ARCH_MODEL_sparc |
| 1972 | 38 # include "adfiles/adGlobals_sparc.hpp" |
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39 #elif defined TARGET_ARCH_MODEL_zero |
| 1972 | 40 # include "adfiles/adGlobals_zero.hpp" |
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41 #elif defined TARGET_ARCH_MODEL_ppc_64 |
| 14391 | 42 # include "adfiles/adGlobals_ppc_64.hpp" |
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43 #endif |
| 1972 | 44 |
| 0 | 45 // Some fun naming (textual) substitutions: |
| 46 // | |
| 47 // RegMask::get_low_elem() ==> RegMask::find_first_elem() | |
| 48 // RegMask::Special ==> RegMask::Empty | |
| 49 // RegMask::_flags ==> RegMask::is_AllStack() | |
| 50 // RegMask::operator<<=() ==> RegMask::Insert() | |
| 51 // RegMask::operator>>=() ==> RegMask::Remove() | |
| 52 // RegMask::Union() ==> RegMask::OR | |
| 53 // RegMask::Inter() ==> RegMask::AND | |
| 54 // | |
| 55 // OptoRegister::RegName ==> OptoReg::Name | |
| 56 // | |
| 57 // OptoReg::stack0() ==> _last_Mach_Reg or ZERO in core version | |
| 58 // | |
| 59 // numregs in chaitin ==> proper degree in chaitin | |
| 60 | |
| 61 //-------------Non-zero bit search methods used by RegMask--------------------- | |
| 62 // Find lowest 1, or return 32 if empty | |
| 63 int find_lowest_bit( uint32 mask ); | |
| 64 // Find highest 1, or return 32 if empty | |
| 65 int find_hihghest_bit( uint32 mask ); | |
| 66 | |
| 67 //------------------------------RegMask---------------------------------------- | |
| 68 // The ADL file describes how to print the machine-specific registers, as well | |
| 69 // as any notion of register classes. We provide a register mask, which is | |
| 70 // just a collection of Register numbers. | |
| 71 | |
| 72 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY. | |
| 73 // RM_SIZE is the size of a register mask in words. | |
| 74 // FORALL_BODY replicates a BODY macro once per word in the register mask. | |
| 75 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files. | |
| 76 // However, it means the ADLC can redefine the unroll macro and all loops | |
| 77 // over register masks will be unrolled by the correct amount. | |
| 78 | |
| 79 class RegMask VALUE_OBJ_CLASS_SPEC { | |
| 80 union { | |
| 81 double _dummy_force_double_alignment[RM_SIZE>>1]; | |
| 82 // Array of Register Mask bits. This array is large enough to cover | |
| 83 // all the machine registers and all parameters that need to be passed | |
| 84 // on the stack (stack registers) up to some interesting limit. Methods | |
| 85 // that need more parameters will NOT be compiled. On Intel, the limit | |
| 86 // is something like 90+ parameters. | |
| 87 int _A[RM_SIZE]; | |
| 88 }; | |
| 89 | |
| 90 enum { | |
| 91 _WordBits = BitsPerInt, | |
| 92 _LogWordBits = LogBitsPerInt, | |
| 93 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef | |
| 94 }; | |
| 95 | |
| 96 public: | |
| 97 enum { CHUNK_SIZE = RM_SIZE*_WordBits }; | |
| 98 | |
| 99 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits. | |
| 100 // Also, consider the maximum alignment size for a normally allocated | |
| 101 // value. Since we allocate register pairs but not register quads (at | |
| 102 // present), this alignment is SlotsPerLong (== 2). A normally | |
| 103 // aligned allocated register is either a single register, or a pair | |
| 104 // of adjacent registers, the lower-numbered being even. | |
| 105 // See also is_aligned_Pairs() below, and the padding added before | |
| 106 // Matcher::_new_SP to keep allocated pairs aligned properly. | |
| 107 // If we ever go to quad-word allocations, SlotsPerQuad will become | |
| 108 // the controlling alignment constraint. Note that this alignment | |
| 109 // requirement is internal to the allocator, and independent of any | |
| 110 // particular platform. | |
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111 enum { SlotsPerLong = 2, |
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112 SlotsPerVecS = 1, |
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113 SlotsPerVecD = 2, |
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114 SlotsPerVecX = 4, |
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115 SlotsPerVecY = 8 }; |
| 0 | 116 |
| 117 // A constructor only used by the ADLC output. All mask fields are filled | |
| 118 // in directly. Calls to this look something like RM(1,2,3,4); | |
| 119 RegMask( | |
| 120 # define BODY(I) int a##I, | |
| 121 FORALL_BODY | |
| 122 # undef BODY | |
| 123 int dummy = 0 ) { | |
| 124 # define BODY(I) _A[I] = a##I; | |
| 125 FORALL_BODY | |
| 126 # undef BODY | |
| 127 } | |
| 128 | |
| 129 // Handy copying constructor | |
| 130 RegMask( RegMask *rm ) { | |
| 131 # define BODY(I) _A[I] = rm->_A[I]; | |
| 132 FORALL_BODY | |
| 133 # undef BODY | |
| 134 } | |
| 135 | |
| 136 // Construct an empty mask | |
| 137 RegMask( ) { Clear(); } | |
| 138 | |
| 139 // Construct a mask with a single bit | |
| 140 RegMask( OptoReg::Name reg ) { Clear(); Insert(reg); } | |
| 141 | |
| 142 // Check for register being in mask | |
| 143 int Member( OptoReg::Name reg ) const { | |
| 144 assert( reg < CHUNK_SIZE, "" ); | |
| 145 return _A[reg>>_LogWordBits] & (1<<(reg&(_WordBits-1))); | |
| 146 } | |
| 147 | |
| 148 // The last bit in the register mask indicates that the mask should repeat | |
| 149 // indefinitely with ONE bits. Returns TRUE if mask is infinite or | |
| 150 // unbounded in size. Returns FALSE if mask is finite size. | |
| 151 int is_AllStack() const { return _A[RM_SIZE-1] >> (_WordBits-1); } | |
| 152 | |
| 153 // Work around an -xO3 optimization problme in WS6U1. The old way: | |
| 154 // void set_AllStack() { _A[RM_SIZE-1] |= (1<<(_WordBits-1)); } | |
| 155 // will cause _A[RM_SIZE-1] to be clobbered, not updated when set_AllStack() | |
| 156 // follows an Insert() loop, like the one found in init_spill_mask(). Using | |
| 157 // Insert() instead works because the index into _A in computed instead of | |
| 158 // constant. See bug 4665841. | |
| 159 void set_AllStack() { Insert(OptoReg::Name(CHUNK_SIZE-1)); } | |
| 160 | |
| 161 // Test for being a not-empty mask. | |
| 162 int is_NotEmpty( ) const { | |
| 163 int tmp = 0; | |
| 164 # define BODY(I) tmp |= _A[I]; | |
| 165 FORALL_BODY | |
| 166 # undef BODY | |
| 167 return tmp; | |
| 168 } | |
| 169 | |
| 170 // Find lowest-numbered register from mask, or BAD if mask is empty. | |
| 171 OptoReg::Name find_first_elem() const { | |
| 172 int base, bits; | |
| 173 # define BODY(I) if( (bits = _A[I]) != 0 ) base = I<<_LogWordBits; else | |
| 174 FORALL_BODY | |
| 175 # undef BODY | |
| 176 { base = OptoReg::Bad; bits = 1<<0; } | |
| 177 return OptoReg::Name(base + find_lowest_bit(bits)); | |
| 178 } | |
| 179 // Get highest-numbered register from mask, or BAD if mask is empty. | |
| 180 OptoReg::Name find_last_elem() const { | |
| 181 int base, bits; | |
| 182 # define BODY(I) if( (bits = _A[RM_SIZE-1-I]) != 0 ) base = (RM_SIZE-1-I)<<_LogWordBits; else | |
| 183 FORALL_BODY | |
| 184 # undef BODY | |
| 185 { base = OptoReg::Bad; bits = 1<<0; } | |
| 186 return OptoReg::Name(base + find_hihghest_bit(bits)); | |
| 187 } | |
| 188 | |
| 189 // Find the lowest-numbered register pair in the mask. Return the | |
| 190 // HIGHEST register number in the pair, or BAD if no pairs. | |
| 191 // Assert that the mask contains only bit pairs. | |
| 192 OptoReg::Name find_first_pair() const; | |
| 193 | |
| 194 // Clear out partial bits; leave only aligned adjacent bit pairs. | |
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195 void clear_to_pairs(); |
| 0 | 196 // Smear out partial bits; leave only aligned adjacent bit pairs. |
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197 void smear_to_pairs(); |
| 0 | 198 // Verify that the mask contains only aligned adjacent bit pairs |
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199 void verify_pairs() const { assert( is_aligned_pairs(), "mask is not aligned, adjacent pairs" ); } |
| 0 | 200 // Test that the mask contains only aligned adjacent bit pairs |
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201 bool is_aligned_pairs() const; |
| 0 | 202 |
| 203 // mask is a pair of misaligned registers | |
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204 bool is_misaligned_pair() const { return Size()==2 && !is_aligned_pairs(); } |
| 0 | 205 // Test for single register |
| 206 int is_bound1() const; | |
| 207 // Test for a single adjacent pair | |
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208 int is_bound_pair() const; |
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209 // Test for a single adjacent set of ideal register's size. |
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210 int is_bound(uint ireg) const { |
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211 if (is_vector(ireg)) { |
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212 if (is_bound_set(num_registers(ireg))) |
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213 return true; |
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214 } else if (is_bound1() || is_bound_pair()) { |
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215 return true; |
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216 } |
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217 return false; |
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218 } |
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219 |
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220 // Find the lowest-numbered register set in the mask. Return the |
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221 // HIGHEST register number in the set, or BAD if no sets. |
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222 // Assert that the mask contains only bit sets. |
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223 OptoReg::Name find_first_set(const int size) const; |
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224 |
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225 // Clear out partial bits; leave only aligned adjacent bit sets of size. |
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226 void clear_to_sets(const int size); |
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227 // Smear out partial bits to aligned adjacent bit sets. |
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228 void smear_to_sets(const int size); |
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229 // Verify that the mask contains only aligned adjacent bit sets |
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230 void verify_sets(int size) const { assert(is_aligned_sets(size), "mask is not aligned, adjacent sets"); } |
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231 // Test that the mask contains only aligned adjacent bit sets |
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232 bool is_aligned_sets(const int size) const; |
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233 |
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234 // mask is a set of misaligned registers |
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235 bool is_misaligned_set(int size) const { return (int)Size()==size && !is_aligned_sets(size);} |
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236 |
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237 // Test for a single adjacent set |
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238 int is_bound_set(const int size) const; |
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239 |
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240 static bool is_vector(uint ireg); |
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241 static int num_registers(uint ireg); |
| 0 | 242 |
| 243 // Fast overlap test. Non-zero if any registers in common. | |
| 244 int overlap( const RegMask &rm ) const { | |
| 245 return | |
| 246 # define BODY(I) (_A[I] & rm._A[I]) | | |
| 247 FORALL_BODY | |
| 248 # undef BODY | |
| 249 0 ; | |
| 250 } | |
| 251 | |
| 252 // Special test for register pressure based splitting | |
| 253 // UP means register only, Register plus stack, or stack only is DOWN | |
| 254 bool is_UP() const; | |
| 255 | |
| 256 // Clear a register mask | |
| 257 void Clear( ) { | |
| 258 # define BODY(I) _A[I] = 0; | |
| 259 FORALL_BODY | |
| 260 # undef BODY | |
| 261 } | |
| 262 | |
| 263 // Fill a register mask with 1's | |
| 264 void Set_All( ) { | |
| 265 # define BODY(I) _A[I] = -1; | |
| 266 FORALL_BODY | |
| 267 # undef BODY | |
| 268 } | |
| 269 | |
| 270 // Insert register into mask | |
| 271 void Insert( OptoReg::Name reg ) { | |
| 272 assert( reg < CHUNK_SIZE, "" ); | |
| 273 _A[reg>>_LogWordBits] |= (1<<(reg&(_WordBits-1))); | |
| 274 } | |
| 275 | |
| 276 // Remove register from mask | |
| 277 void Remove( OptoReg::Name reg ) { | |
| 278 assert( reg < CHUNK_SIZE, "" ); | |
| 279 _A[reg>>_LogWordBits] &= ~(1<<(reg&(_WordBits-1))); | |
| 280 } | |
| 281 | |
| 282 // OR 'rm' into 'this' | |
| 283 void OR( const RegMask &rm ) { | |
| 284 # define BODY(I) this->_A[I] |= rm._A[I]; | |
| 285 FORALL_BODY | |
| 286 # undef BODY | |
| 287 } | |
| 288 | |
| 289 // AND 'rm' into 'this' | |
| 290 void AND( const RegMask &rm ) { | |
| 291 # define BODY(I) this->_A[I] &= rm._A[I]; | |
| 292 FORALL_BODY | |
| 293 # undef BODY | |
| 294 } | |
| 295 | |
| 296 // Subtract 'rm' from 'this' | |
| 297 void SUBTRACT( const RegMask &rm ) { | |
| 298 # define BODY(I) _A[I] &= ~rm._A[I]; | |
| 299 FORALL_BODY | |
| 300 # undef BODY | |
| 301 } | |
| 302 | |
| 303 // Compute size of register mask: number of bits | |
| 304 uint Size() const; | |
| 305 | |
| 306 #ifndef PRODUCT | |
| 307 void print() const { dump(); } | |
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308 void dump(outputStream *st = tty) const; // Print a mask |
| 0 | 309 #endif |
| 310 | |
| 311 static const RegMask Empty; // Common empty mask | |
| 312 | |
| 313 static bool can_represent(OptoReg::Name reg) { | |
| 314 // NOTE: -1 in computation reflects the usage of the last | |
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315 // bit of the regmask as an infinite stack flag and |
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316 // -7 is to keep mask aligned for largest value (VecY). |
| 0 | 317 return (int)reg < (int)(CHUNK_SIZE-1); |
| 318 } | |
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319 static bool can_represent_arg(OptoReg::Name reg) { |
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320 // NOTE: -SlotsPerVecY in computation reflects the need |
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321 // to keep mask aligned for largest value (VecY). |
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322 return (int)reg < (int)(CHUNK_SIZE-SlotsPerVecY); |
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323 } |
| 0 | 324 }; |
| 325 | |
| 326 // Do not use this constant directly in client code! | |
| 327 #undef RM_SIZE | |
| 1972 | 328 |
| 329 #endif // SHARE_VM_OPTO_REGMASK_HPP |