Mercurial > hg > graal-jvmci-8
annotate graal/GraalCompiler/src/com/sun/c1x/target/amd64/AMD64LIRGenerator.java @ 2632:776e026f2e15
Small cleanup.
author | Thomas Wuerthinger <thomas@wuerthinger.net> |
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date | Tue, 10 May 2011 17:17:28 +0200 |
parents | c93adece95d2 |
children | 194d93d089bd |
rev | line source |
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1 /* |
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2 * Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 |
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24 package com.sun.c1x.target.amd64; |
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25 |
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26 import com.sun.c1x.*; |
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27 import com.sun.c1x.alloc.OperandPool.VariableFlag; |
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28 import com.sun.c1x.gen.*; |
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29 import com.sun.c1x.globalstub.*; |
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30 import com.sun.c1x.ir.*; |
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31 import com.sun.c1x.lir.*; |
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32 import com.sun.c1x.util.*; |
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33 import com.sun.c1x.value.*; |
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34 import com.sun.cri.bytecode.*; |
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35 import com.sun.cri.ci.*; |
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36 |
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37 /** |
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38 * This class implements the X86-specific portion of the LIR generator. |
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39 * |
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40 * @author Thomas Wuerthinger |
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41 * @author Ben L. Titzer |
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42 */ |
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43 public class AMD64LIRGenerator extends LIRGenerator { |
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44 |
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45 private static final CiRegisterValue RAX_I = AMD64.rax.asValue(CiKind.Int); |
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46 private static final CiRegisterValue RAX_L = AMD64.rax.asValue(CiKind.Long); |
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47 private static final CiRegisterValue RAX_W = AMD64.rax.asValue(CiKind.Word); |
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48 private static final CiRegisterValue RDX_I = AMD64.rdx.asValue(CiKind.Int); |
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49 private static final CiRegisterValue RDX_L = AMD64.rdx.asValue(CiKind.Long); |
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50 |
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51 private static final CiRegisterValue LDIV_TMP = RDX_L; |
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52 |
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53 |
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54 /** |
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55 * The register in which MUL puts the result for 64-bit multiplication. |
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56 */ |
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57 private static final CiRegisterValue LMUL_OUT = RAX_L; |
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58 |
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59 private static final CiRegisterValue SHIFT_COUNT_IN = AMD64.rcx.asValue(CiKind.Int); |
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60 |
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61 protected static final CiValue ILLEGAL = CiValue.IllegalValue; |
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62 |
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63 public AMD64LIRGenerator(C1XCompilation compilation) { |
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64 super(compilation); |
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65 } |
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66 |
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67 @Override |
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68 protected boolean canStoreAsConstant(Value v, CiKind kind) { |
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69 if (kind == CiKind.Short || kind == CiKind.Char) { |
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70 // there is no immediate move of word values in asemblerI486.?pp |
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71 return false; |
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72 } |
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73 return v instanceof Constant; |
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74 } |
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75 |
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76 @Override |
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77 protected boolean canInlineAsConstant(Value v) { |
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78 if (v.kind == CiKind.Long) { |
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79 if (v.isConstant() && Util.isInt(v.asConstant().asLong())) { |
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80 return true; |
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81 } |
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82 return false; |
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83 } |
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84 return v.kind != CiKind.Object || v.isNullConstant(); |
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85 } |
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86 |
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87 @Override |
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88 protected CiAddress genAddress(CiValue base, CiValue index, int shift, int disp, CiKind kind) { |
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89 assert base.isVariableOrRegister(); |
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90 if (index.isConstant()) { |
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91 return new CiAddress(kind, base, (((CiConstant) index).asInt() << shift) + disp); |
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92 } else { |
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93 assert index.isVariableOrRegister(); |
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94 return new CiAddress(kind, base, (index), CiAddress.Scale.fromShift(shift), disp); |
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95 } |
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96 } |
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97 |
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98 @Override |
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99 protected void genCmpMemInt(Condition condition, CiValue base, int disp, int c, LIRDebugInfo info) { |
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100 lir.cmpMemInt(condition, base, disp, c, info); |
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101 } |
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102 |
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103 @Override |
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104 protected void genCmpRegMem(Condition condition, CiValue reg, CiValue base, int disp, CiKind kind, LIRDebugInfo info) { |
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105 lir.cmpRegMem(condition, reg, new CiAddress(kind, base, disp), info); |
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106 } |
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107 |
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108 @Override |
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109 protected boolean strengthReduceMultiply(CiValue left, int c, CiValue result, CiValue tmp) { |
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110 if (tmp.isLegal()) { |
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111 if (CiUtil.isPowerOf2(c + 1)) { |
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112 lir.move(left, tmp); |
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113 lir.shiftLeft(left, CiUtil.log2(c + 1), left); |
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114 lir.sub(left, tmp, result); |
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115 return true; |
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116 } else if (CiUtil.isPowerOf2(c - 1)) { |
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117 lir.move(left, tmp); |
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118 lir.shiftLeft(left, CiUtil.log2(c - 1), left); |
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119 lir.add(left, tmp, result); |
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120 return true; |
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121 } |
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122 } |
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123 return false; |
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124 } |
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125 |
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126 @Override |
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127 public void visitNegateOp(NegateOp x) { |
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128 LIRItem value = new LIRItem(x.x(), this); |
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129 value.setDestroysRegister(); |
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130 value.loadItem(); |
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131 CiVariable reg = newVariable(x.kind); |
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132 GlobalStub globalStub = null; |
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133 if (x.kind == CiKind.Float) { |
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134 globalStub = stubFor(GlobalStub.Id.fneg); |
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135 } else if (x.kind == CiKind.Double) { |
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136 globalStub = stubFor(GlobalStub.Id.dneg); |
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137 } |
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138 lir.negate(value.result(), reg, globalStub); |
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139 setResult(x, reg); |
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140 } |
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141 |
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142 public boolean livesLonger(Value x, Value y) { |
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143 BlockBegin bx = x.block(); |
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144 BlockBegin by = y.block(); |
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145 if (bx == null || by == null) { |
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146 return false; |
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147 } |
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148 return bx.loopDepth() < by.loopDepth(); |
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149 } |
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150 |
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151 public void visitArithmeticOpFloat(ArithmeticOp x) { |
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152 LIRItem left = new LIRItem(x.x(), this); |
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153 LIRItem right = new LIRItem(x.y(), this); |
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154 assert !left.isStack() || !right.isStack() : "can't both be memory operands"; |
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155 boolean mustLoadBoth = (x.opcode == Bytecodes.FREM || x.opcode == Bytecodes.DREM); |
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156 |
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157 // Both are in register, swap operands such that the short-living one is on the left side. |
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158 if (x.isCommutative() && left.isRegisterOrVariable() && right.isRegisterOrVariable()) { |
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159 if (livesLonger(x.x(), x.y())) { |
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160 LIRItem tmp = left; |
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161 left = right; |
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162 right = tmp; |
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163 } |
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164 } |
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165 |
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166 if (left.isRegisterOrVariable() || x.x().isConstant() || mustLoadBoth) { |
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167 left.loadItem(); |
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168 } |
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169 |
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170 if (mustLoadBoth) { |
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171 // frem and drem destroy also right operand, so move it to a new register |
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172 right.setDestroysRegister(); |
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173 right.loadItem(); |
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174 } else if (right.isRegisterOrVariable()) { |
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175 right.loadItem(); |
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176 } |
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177 |
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178 CiVariable reg; |
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179 |
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180 if (x.opcode == Bytecodes.FREM) { |
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181 reg = callRuntimeWithResult(CiRuntimeCall.ArithmeticFrem, null, left.result(), right.result()); |
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182 } else if (x.opcode == Bytecodes.DREM) { |
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183 reg = callRuntimeWithResult(CiRuntimeCall.ArithmeticDrem, null, left.result(), right.result()); |
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184 } else { |
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185 reg = newVariable(x.kind); |
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186 arithmeticOpFpu(x.opcode, reg, left.result(), right.result(), ILLEGAL); |
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187 } |
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188 |
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189 setResult(x, reg); |
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190 } |
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191 |
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192 public void visitArithmeticOpLong(ArithmeticOp x) { |
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193 int opcode = x.opcode; |
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194 if (opcode == Bytecodes.LDIV || opcode == Bytecodes.LREM) { |
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195 // emit inline 64-bit code |
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196 LIRDebugInfo info = stateFor(x); |
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197 CiValue dividend = force(x.x(), RAX_L); // dividend must be in RAX |
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198 CiValue divisor = load(x.y()); // divisor can be in any (other) register |
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199 |
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200 CiValue result = createResultVariable(x); |
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201 CiValue resultReg; |
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202 if (opcode == Bytecodes.LREM) { |
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203 resultReg = RDX_L; // remainder result is produced in rdx |
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204 lir.lrem(dividend, divisor, resultReg, LDIV_TMP, info); |
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205 } else { |
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206 resultReg = RAX_L; // division result is produced in rax |
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207 lir.ldiv(dividend, divisor, resultReg, LDIV_TMP, info); |
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208 } |
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209 |
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210 lir.move(resultReg, result); |
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211 } else if (opcode == Bytecodes.LMUL) { |
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212 LIRItem right = new LIRItem(x.y(), this); |
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213 |
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214 // right register is destroyed by the long mul, so it must be |
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215 // copied to a new register. |
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216 right.setDestroysRegister(); |
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217 |
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218 CiValue left = load(x.x()); |
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219 right.loadItem(); |
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220 |
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221 arithmeticOpLong(opcode, LMUL_OUT, left, right.result(), null); |
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222 CiValue result = createResultVariable(x); |
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223 lir.move(LMUL_OUT, result); |
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224 } else { |
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225 LIRItem right = new LIRItem(x.y(), this); |
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226 |
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227 CiValue left = load(x.x()); |
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228 // don't load constants to save register |
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229 right.loadNonconstant(); |
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230 createResultVariable(x); |
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231 arithmeticOpLong(opcode, x.operand(), left, right.result(), null); |
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232 } |
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233 } |
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234 |
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235 public void visitArithmeticOpInt(ArithmeticOp x) { |
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236 int opcode = x.opcode; |
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237 if (opcode == Bytecodes.IDIV || opcode == Bytecodes.IREM) { |
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238 // emit code for integer division or modulus |
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239 |
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240 // Call 'stateFor' before 'force()' because 'stateFor()' may |
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241 // force the evaluation of other instructions that are needed for |
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242 // correct debug info. Otherwise the live range of the fixed |
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243 // register might be too long. |
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244 LIRDebugInfo info = stateFor(x); |
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245 |
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246 CiValue dividend = force(x.x(), RAX_I); // dividend must be in RAX |
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247 CiValue divisor = load(x.y()); // divisor can be in any (other) register |
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248 |
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249 // idiv and irem use rdx in their implementation so the |
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250 // register allocator must not assign it to an interval that overlaps |
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251 // this division instruction. |
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252 CiRegisterValue tmp = RDX_I; |
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253 |
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254 CiValue result = createResultVariable(x); |
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255 CiValue resultReg; |
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256 if (opcode == Bytecodes.IREM) { |
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257 resultReg = tmp; // remainder result is produced in rdx |
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258 lir.irem(dividend, divisor, resultReg, tmp, info); |
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259 } else { |
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260 resultReg = RAX_I; // division result is produced in rax |
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261 lir.idiv(dividend, divisor, resultReg, tmp, info); |
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262 } |
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263 |
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264 lir.move(resultReg, result); |
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265 } else { |
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266 // emit code for other integer operations |
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267 LIRItem left = new LIRItem(x.x(), this); |
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268 LIRItem right = new LIRItem(x.y(), this); |
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269 LIRItem leftArg = left; |
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270 LIRItem rightArg = right; |
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271 if (x.isCommutative() && left.isStack() && right.isRegisterOrVariable()) { |
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272 // swap them if left is real stack (or cached) and right is real register(not cached) |
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273 leftArg = right; |
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274 rightArg = left; |
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275 } |
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276 |
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277 leftArg.loadItem(); |
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278 |
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279 // do not need to load right, as we can handle stack and constants |
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280 if (opcode == Bytecodes.IMUL) { |
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281 // check if we can use shift instead |
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282 boolean useConstant = false; |
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283 boolean useTmp = false; |
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284 if (rightArg.result().isConstant()) { |
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285 int iconst = rightArg.instruction.asConstant().asInt(); |
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286 if (iconst > 0) { |
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287 if (CiUtil.isPowerOf2(iconst)) { |
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288 useConstant = true; |
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289 } else if (CiUtil.isPowerOf2(iconst - 1) || CiUtil.isPowerOf2(iconst + 1)) { |
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290 useConstant = true; |
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291 useTmp = true; |
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292 } |
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293 } |
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294 } |
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295 if (!useConstant) { |
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296 rightArg.loadItem(); |
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297 } |
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298 CiValue tmp = ILLEGAL; |
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299 if (useTmp) { |
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300 tmp = newVariable(CiKind.Int); |
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301 } |
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302 createResultVariable(x); |
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303 |
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304 arithmeticOpInt(opcode, x.operand(), leftArg.result(), rightArg.result(), tmp); |
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305 } else { |
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306 createResultVariable(x); |
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307 CiValue tmp = ILLEGAL; |
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308 arithmeticOpInt(opcode, x.operand(), leftArg.result(), rightArg.result(), tmp); |
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309 } |
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310 } |
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311 } |
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312 |
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313 public void visitArithmeticOpWord(ArithmeticOp x) { |
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314 int opcode = x.opcode; |
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315 if (opcode == Bytecodes.WDIV || opcode == Bytecodes.WREM || opcode == Bytecodes.WDIVI || opcode == Bytecodes.WREMI) { |
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316 // emit code for long division or modulus |
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317 // emit inline 64-bit code |
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318 LIRDebugInfo info = stateFor(x); |
2507
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319 CiValue dividend = force(x.x(), RAX_L); // dividend must be in RAX |
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320 CiValue divisor = load(x.y()); // divisor can be in any (other) register |
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321 |
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322 CiValue result = createResultVariable(x); |
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323 CiValue resultReg; |
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324 if (opcode == Bytecodes.WREM) { |
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325 resultReg = RDX_L; // remainder result is produced in rdx |
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326 lir.wrem(dividend, divisor, resultReg, LDIV_TMP, info); |
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327 } else if (opcode == Bytecodes.WREMI) { |
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328 resultReg = RDX_L; // remainder result is produced in rdx |
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329 lir.wremi(dividend, divisor, resultReg, LDIV_TMP, info); |
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330 } else if (opcode == Bytecodes.WDIV) { |
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331 resultReg = RAX_L; // division result is produced in rax |
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332 lir.wdiv(dividend, divisor, resultReg, LDIV_TMP, info); |
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333 } else { |
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334 assert opcode == Bytecodes.WDIVI; |
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335 resultReg = RAX_L; // division result is produced in rax |
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336 lir.wdivi(dividend, divisor, resultReg, LDIV_TMP, info); |
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337 } |
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338 |
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339 lir.move(resultReg, result); |
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340 } else if (opcode == Bytecodes.LMUL) { |
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341 LIRItem right = new LIRItem(x.y(), this); |
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342 |
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343 // right register is destroyed by the long mul, so it must be |
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344 // copied to a new register. |
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345 right.setDestroysRegister(); |
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346 |
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347 CiValue left = load(x.x()); |
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348 right.loadItem(); |
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349 |
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350 CiValue reg = LMUL_OUT; |
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351 arithmeticOpLong(opcode, reg, left, right.result(), null); |
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352 CiValue result = createResultVariable(x); |
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353 lir.move(reg, result); |
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354 } else { |
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355 LIRItem right = new LIRItem(x.y(), this); |
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356 |
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357 CiValue left = load(x.x()); |
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358 // don't load constants to save register |
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359 right.loadNonconstant(); |
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360 createResultVariable(x); |
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361 arithmeticOpLong(opcode, x.operand(), left, right.result(), null); |
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362 } |
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363 } |
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364 |
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365 @Override |
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366 public void visitArithmeticOp(ArithmeticOp x) { |
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367 trySwap(x); |
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368 |
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369 if (x.kind.isWord() || x.opcode == Bytecodes.WREMI) { |
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370 visitArithmeticOpWord(x); |
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371 return; |
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372 } |
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373 |
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374 assert Util.archKindsEqual(x.x().kind, x.kind) && Util.archKindsEqual(x.y().kind, x.kind) : "wrong parameter types: " + Bytecodes.nameOf(x.opcode); |
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375 switch (x.kind) { |
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376 case Float: |
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377 case Double: |
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378 visitArithmeticOpFloat(x); |
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379 return; |
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380 case Long: |
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381 visitArithmeticOpLong(x); |
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382 return; |
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383 case Int: |
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384 visitArithmeticOpInt(x); |
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385 return; |
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386 } |
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387 throw Util.shouldNotReachHere(); |
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388 } |
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389 |
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390 @Override |
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391 public void visitShiftOp(ShiftOp x) { |
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392 // count must always be in rcx |
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393 CiValue count = makeOperand(x.y()); |
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394 boolean mustLoadCount = !count.isConstant() || x.kind == CiKind.Long; |
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395 if (mustLoadCount) { |
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396 // count for long must be in register |
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397 count = force(x.y(), SHIFT_COUNT_IN); |
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398 } |
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399 |
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400 CiValue value = load(x.x()); |
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401 CiValue reg = createResultVariable(x); |
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402 |
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403 shiftOp(x.opcode, reg, value, count, ILLEGAL); |
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404 } |
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405 |
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406 @Override |
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407 public void visitLogicOp(LogicOp x) { |
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408 trySwap(x); |
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409 |
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410 LIRItem right = new LIRItem(x.y(), this); |
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411 |
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412 CiValue left = load(x.x()); |
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413 right.loadNonconstant(); |
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414 CiValue reg = createResultVariable(x); |
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415 |
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416 logicOp(x.opcode, reg, left, right.result()); |
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417 } |
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418 |
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419 private void trySwap(Op2 x) { |
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420 // (tw) TODO: Check what this is for? |
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421 } |
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422 |
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423 @Override |
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424 public void visitCompareOp(CompareOp x) { |
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425 LIRItem left = new LIRItem(x.x(), this); |
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426 LIRItem right = new LIRItem(x.y(), this); |
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427 if (!x.kind.isVoid() && x.x().kind.isLong()) { |
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428 left.setDestroysRegister(); |
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429 } |
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430 left.loadItem(); |
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431 right.loadItem(); |
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432 |
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433 if (x.kind.isVoid()) { |
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434 lir.cmp(Condition.TRUE, left.result(), right.result()); |
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435 } else if (x.x().kind.isFloat() || x.x().kind.isDouble()) { |
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436 CiValue reg = createResultVariable(x); |
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437 int code = x.opcode; |
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438 lir.fcmp2int(left.result(), right.result(), reg, (code == Bytecodes.FCMPL || code == Bytecodes.DCMPL)); |
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439 } else if (x.x().kind.isLong() || x.x().kind.isWord()) { |
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440 CiValue reg = createResultVariable(x); |
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441 lir.lcmp2int(left.result(), right.result(), reg); |
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442 } else { |
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443 Util.unimplemented(); |
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444 } |
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445 } |
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446 |
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447 @Override |
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448 public void visitConvert(Convert x) { |
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449 CiValue input = load(x.value()); |
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450 CiVariable result = newVariable(x.kind); |
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451 // arguments of lirConvert |
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452 GlobalStub globalStub = null; |
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453 switch (x.opcode) { |
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454 case Bytecodes.F2I: globalStub = stubFor(GlobalStub.Id.f2i); break; |
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455 case Bytecodes.F2L: globalStub = stubFor(GlobalStub.Id.f2l); break; |
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456 case Bytecodes.D2I: globalStub = stubFor(GlobalStub.Id.d2i); break; |
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457 case Bytecodes.D2L: globalStub = stubFor(GlobalStub.Id.d2l); break; |
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458 } |
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459 if (globalStub != null) { |
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460 // Force result to be rax to match global stubs expectation. |
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461 CiValue stubResult = x.kind == CiKind.Int ? RAX_I : RAX_L; |
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462 lir.convert(x.opcode, input, stubResult, globalStub); |
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463 lir.move(stubResult, result); |
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464 } else { |
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465 lir.convert(x.opcode, input, result, globalStub); |
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466 } |
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467 setResult(x, result); |
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468 } |
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469 |
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470 @Override |
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471 public void visitBlockBegin(BlockBegin x) { |
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472 // nothing to do for now |
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473 } |
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474 |
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475 @Override |
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476 public void visitIf(If x) { |
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477 CiKind kind = x.x().kind; |
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478 |
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479 Condition cond = x.condition(); |
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480 |
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481 LIRItem xitem = new LIRItem(x.x(), this); |
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482 LIRItem yitem = new LIRItem(x.y(), this); |
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483 LIRItem xin = xitem; |
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484 LIRItem yin = yitem; |
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485 |
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486 if (kind.isLong()) { |
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487 // for longs, only conditions "eql", "neq", "lss", "geq" are valid; |
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488 // mirror for other conditions |
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489 if (cond == Condition.GT || cond == Condition.LE) { |
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490 cond = cond.mirror(); |
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491 xin = yitem; |
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492 yin = xitem; |
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493 } |
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494 xin.setDestroysRegister(); |
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495 } |
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496 xin.loadItem(); |
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497 if (kind.isLong() && yin.result().isConstant() && yin.instruction.asConstant().asLong() == 0 && (cond == Condition.EQ || cond == Condition.NE)) { |
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498 // dont load item |
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499 } else if (kind.isLong() || kind.isFloat() || kind.isDouble()) { |
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500 // longs cannot handle constants at right side |
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501 yin.loadItem(); |
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502 } |
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503 |
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504 // add safepoint before generating condition code so it can be recomputed |
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505 if (x.isSafepoint()) { |
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506 emitXir(xir.genSafepoint(site(x)), x, stateFor(x, x.stateAfter()), null, false); |
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507 } |
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508 setNoResult(x); |
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509 |
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510 CiValue left = xin.result(); |
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511 CiValue right = yin.result(); |
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512 lir.cmp(cond, left, right); |
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513 moveToPhi(); |
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514 if (x.x().kind.isFloat() || x.x().kind.isDouble()) { |
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515 lir.branch(cond, right.kind, x.trueSuccessor(), x.unorderedSuccessor()); |
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516 } else { |
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517 lir.branch(cond, right.kind, x.trueSuccessor()); |
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518 } |
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519 assert x.defaultSuccessor() == x.falseSuccessor() : "wrong destination above"; |
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520 lir.jump(x.defaultSuccessor()); |
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521 } |
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522 } |