Mercurial > hg > graal-jvmci-8
annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 22465:b14500c9da22
documented JVMCI-specific _implicit_exception_pc and _alternate_call_target fields in JavaThread and prepared for them to be in a union
author | Doug Simon <doug.simon@oracle.com> |
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date | Tue, 25 Aug 2015 14:34:50 +0200 |
parents | f27c163d7dc2 |
children | f58e7b5fe0ab |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.inline.hpp" |
1972 | 27 #include "code/debugInfoRec.hpp" |
28 #include "code/icBuffer.hpp" | |
29 #include "code/vtableStubs.hpp" | |
30 #include "interpreter/interpreter.hpp" | |
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31 #include "oops/compiledICHolder.hpp" |
1972 | 32 #include "prims/jvmtiRedefineClassesTrace.hpp" |
33 #include "runtime/sharedRuntime.hpp" | |
34 #include "runtime/vframeArray.hpp" | |
35 #include "vmreg_sparc.inline.hpp" | |
36 #ifdef COMPILER1 | |
37 #include "c1/c1_Runtime1.hpp" | |
38 #endif | |
39 #ifdef COMPILER2 | |
40 #include "opto/runtime.hpp" | |
41 #endif | |
42 #ifdef SHARK | |
43 #include "compiler/compileBroker.hpp" | |
44 #include "shark/sharkCompiler.hpp" | |
45 #endif | |
22298 | 46 #if INCLUDE_JVMCI |
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47 #include "jvmci/jvmciJavaAccess.hpp" |
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48 #endif |
0 | 49 |
50 #define __ masm-> | |
51 | |
52 | |
53 class RegisterSaver { | |
54 | |
55 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. | |
56 // The Oregs are problematic. In the 32bit build the compiler can | |
57 // have O registers live with 64 bit quantities. A window save will | |
58 // cut the heads off of the registers. We have to do a very extensive | |
59 // stack dance to save and restore these properly. | |
60 | |
61 // Note that the Oregs problem only exists if we block at either a polling | |
62 // page exception a compiled code safepoint that was not originally a call | |
63 // or deoptimize following one of these kinds of safepoints. | |
64 | |
65 // Lots of registers to save. For all builds, a window save will preserve | |
66 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit | |
67 // builds a window-save will preserve the %o registers. In the LION build | |
68 // we need to save the 64-bit %o registers which requires we save them | |
69 // before the window-save (as then they become %i registers and get their | |
70 // heads chopped off on interrupt). We have to save some %g registers here | |
71 // as well. | |
72 enum { | |
73 // This frame's save area. Includes extra space for the native call: | |
74 // vararg's layout space and the like. Briefly holds the caller's | |
75 // register save area. | |
76 call_args_area = frame::register_save_words_sp_offset + | |
77 frame::memory_parameter_word_sp_offset*wordSize, | |
78 // Make sure save locations are always 8 byte aligned. | |
79 // can't use round_to because it doesn't produce compile time constant | |
80 start_of_extra_save_area = ((call_args_area + 7) & ~7), | |
81 g1_offset = start_of_extra_save_area, // g-regs needing saving | |
82 g3_offset = g1_offset+8, | |
83 g4_offset = g3_offset+8, | |
84 g5_offset = g4_offset+8, | |
85 o0_offset = g5_offset+8, | |
86 o1_offset = o0_offset+8, | |
87 o2_offset = o1_offset+8, | |
88 o3_offset = o2_offset+8, | |
89 o4_offset = o3_offset+8, | |
90 o5_offset = o4_offset+8, | |
91 start_of_flags_save_area = o5_offset+8, | |
92 ccr_offset = start_of_flags_save_area, | |
93 fsr_offset = ccr_offset + 8, | |
94 d00_offset = fsr_offset+8, // Start of float save area | |
95 register_save_size = d00_offset+8*32 | |
96 }; | |
97 | |
98 | |
99 public: | |
100 | |
101 static int Oexception_offset() { return o0_offset; }; | |
102 static int G3_offset() { return g3_offset; }; | |
103 static int G5_offset() { return g5_offset; }; | |
104 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); | |
105 static void restore_live_registers(MacroAssembler* masm); | |
106 | |
107 // During deoptimization only the result register need to be restored | |
108 // all the other values have already been extracted. | |
109 | |
110 static void restore_result_registers(MacroAssembler* masm); | |
111 }; | |
112 | |
113 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { | |
114 // Record volatile registers as callee-save values in an OopMap so their save locations will be | |
115 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for | |
116 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers | |
117 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame | |
118 // (as the stub's I's) when the runtime routine called by the stub creates its frame. | |
119 int i; | |
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120 // Always make the frame size 16 byte aligned. |
0 | 121 int frame_size = round_to(additional_frame_words + register_save_size, 16); |
122 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words | |
123 int frame_size_in_slots = frame_size / sizeof(jint); | |
124 // CodeBlob frame size is in words. | |
125 *total_frame_words = frame_size / wordSize; | |
126 // OopMap* map = new OopMap(*total_frame_words, 0); | |
127 OopMap* map = new OopMap(frame_size_in_slots, 0); | |
128 | |
129 #if !defined(_LP64) | |
130 | |
131 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. | |
132 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
133 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
134 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
135 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
136 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
137 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
138 #endif /* _LP64 */ | |
139 | |
140 __ save(SP, -frame_size, SP); | |
141 | |
142 #ifndef _LP64 | |
143 // Reload the 64 bit Oregs. Although they are now Iregs we load them | |
144 // to Oregs here to avoid interrupts cutting off their heads | |
145 | |
146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
150 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
151 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
152 | |
153 __ stx(O0, SP, o0_offset+STACK_BIAS); | |
154 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); | |
155 | |
156 __ stx(O1, SP, o1_offset+STACK_BIAS); | |
157 | |
158 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); | |
159 | |
160 __ stx(O2, SP, o2_offset+STACK_BIAS); | |
161 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); | |
162 | |
163 __ stx(O3, SP, o3_offset+STACK_BIAS); | |
164 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); | |
165 | |
166 __ stx(O4, SP, o4_offset+STACK_BIAS); | |
167 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); | |
168 | |
169 __ stx(O5, SP, o5_offset+STACK_BIAS); | |
170 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); | |
171 #endif /* _LP64 */ | |
172 | |
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173 |
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174 #ifdef _LP64 |
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175 int debug_offset = 0; |
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176 #else |
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177 int debug_offset = 4; |
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178 #endif |
0 | 179 // Save the G's |
180 __ stx(G1, SP, g1_offset+STACK_BIAS); | |
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181 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); |
0 | 182 |
183 __ stx(G3, SP, g3_offset+STACK_BIAS); | |
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184 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); |
0 | 185 |
186 __ stx(G4, SP, g4_offset+STACK_BIAS); | |
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187 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); |
0 | 188 |
189 __ stx(G5, SP, g5_offset+STACK_BIAS); | |
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190 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); |
0 | 191 |
192 // This is really a waste but we'll keep things as they were for now | |
193 if (true) { | |
194 #ifndef _LP64 | |
195 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); | |
196 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); | |
197 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); | |
198 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); | |
199 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); | |
200 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); | |
201 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); | |
202 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); | |
203 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); | |
204 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); | |
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205 #endif /* _LP64 */ |
0 | 206 } |
207 | |
208 | |
209 // Save the flags | |
210 __ rdccr( G5 ); | |
211 __ stx(G5, SP, ccr_offset+STACK_BIAS); | |
212 __ stxfsr(SP, fsr_offset+STACK_BIAS); | |
213 | |
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214 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) |
0 | 215 int offset = d00_offset; |
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216 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
0 | 217 FloatRegister f = as_FloatRegister(i); |
218 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); | |
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219 // Record as callee saved both halves of double registers (2 float registers). |
0 | 220 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); |
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221 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); |
0 | 222 offset += sizeof(double); |
223 } | |
224 | |
225 // And we're done. | |
226 | |
227 return map; | |
228 } | |
229 | |
230 | |
231 // Pop the current frame and restore all the registers that we | |
232 // saved. | |
233 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { | |
234 | |
235 // Restore all the FP registers | |
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236 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
0 | 237 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); |
238 } | |
239 | |
240 __ ldx(SP, ccr_offset+STACK_BIAS, G1); | |
241 __ wrccr (G1) ; | |
242 | |
243 // Restore the G's | |
244 // Note that G2 (AKA GThread) must be saved and restored separately. | |
245 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. | |
246 | |
247 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
248 __ ldx(SP, g3_offset+STACK_BIAS, G3); | |
249 __ ldx(SP, g4_offset+STACK_BIAS, G4); | |
250 __ ldx(SP, g5_offset+STACK_BIAS, G5); | |
251 | |
252 | |
253 #if !defined(_LP64) | |
254 // Restore the 64-bit O's. | |
255 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
256 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
257 __ ldx(SP, o2_offset+STACK_BIAS, O2); | |
258 __ ldx(SP, o3_offset+STACK_BIAS, O3); | |
259 __ ldx(SP, o4_offset+STACK_BIAS, O4); | |
260 __ ldx(SP, o5_offset+STACK_BIAS, O5); | |
261 | |
262 // And temporarily place them in TLS | |
263 | |
264 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
265 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
266 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
267 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
268 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
269 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
270 #endif /* _LP64 */ | |
271 | |
272 // Restore flags | |
273 | |
274 __ ldxfsr(SP, fsr_offset+STACK_BIAS); | |
275 | |
276 __ restore(); | |
277 | |
278 #if !defined(_LP64) | |
279 // Now reload the 64bit Oregs after we've restore the window. | |
280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
284 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
285 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
286 #endif /* _LP64 */ | |
287 | |
288 } | |
289 | |
290 // Pop the current frame and restore the registers that might be holding | |
291 // a result. | |
292 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { | |
293 | |
294 #if !defined(_LP64) | |
295 // 32bit build returns longs in G1 | |
296 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
297 | |
298 // Retrieve the 64-bit O's. | |
299 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
300 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
301 // and save to TLS | |
302 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
303 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
304 #endif /* _LP64 */ | |
305 | |
306 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); | |
307 | |
308 __ restore(); | |
309 | |
310 #if !defined(_LP64) | |
311 // Now reload the 64bit Oregs after we've restore the window. | |
312 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
313 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
314 #endif /* _LP64 */ | |
315 | |
316 } | |
317 | |
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318 // Is vector's size (in bytes) bigger than a size saved by default? |
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319 // 8 bytes FP registers are saved by default on SPARC. |
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320 bool SharedRuntime::is_wide_vector(int size) { |
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321 // Note, MaxVectorSize == 8 on SPARC. |
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322 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size)); |
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323 return size > 8; |
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324 } |
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325 |
0 | 326 // The java_calling_convention describes stack locations as ideal slots on |
327 // a frame with no abi restrictions. Since we must observe abi restrictions | |
328 // (like the placement of the register window) the slots must be biased by | |
329 // the following value. | |
330 static int reg2offset(VMReg r) { | |
331 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
332 } | |
333 | |
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334 static VMRegPair reg64_to_VMRegPair(Register r) { |
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335 VMRegPair ret; |
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336 if (wordSize == 8) { |
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337 ret.set2(r->as_VMReg()); |
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338 } else { |
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339 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); |
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340 } |
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341 return ret; |
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342 } |
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343 |
0 | 344 // --------------------------------------------------------------------------- |
345 // Read the array of BasicTypes from a signature, and compute where the | |
346 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) | |
347 // quantities. Values less than VMRegImpl::stack0 are registers, those above | |
348 // refer to 4-byte stack slots. All stack slots are based off of the window | |
349 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, | |
350 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register | |
351 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit | |
352 // integer registers. Values 64-95 are the (32-bit only) float registers. | |
353 // Each 32-bit quantity is given its own number, so the integer registers | |
354 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is | |
355 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. | |
356 | |
357 // Register results are passed in O0-O5, for outgoing call arguments. To | |
358 // convert to incoming arguments, convert all O's to I's. The regs array | |
359 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. | |
360 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a | |
361 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was | |
362 // passed (used as a placeholder for the other half of longs and doubles in | |
363 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is | |
364 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). | |
365 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() | |
366 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the | |
367 // same VMRegPair. | |
368 | |
369 // Note: the INPUTS in sig_bt are in units of Java argument words, which are | |
370 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit | |
371 // units regardless of build. | |
372 | |
373 | |
374 // --------------------------------------------------------------------------- | |
375 // The compiled Java calling convention. The Java convention always passes | |
376 // 64-bit values in adjacent aligned locations (either registers or stack), | |
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377 // floats in float registers and doubles in aligned float pairs. There is |
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378 // no backing varargs store for values in registers. |
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379 // In the 32-bit build, longs are passed on the stack (cannot be |
0 | 380 // passed in I's, because longs in I's get their heads chopped off at |
381 // interrupt). | |
382 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | |
383 VMRegPair *regs, | |
384 int total_args_passed, | |
385 int is_outgoing) { | |
386 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); | |
387 | |
388 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; | |
389 const int flt_reg_max = 8; | |
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390 |
0 | 391 int int_reg = 0; |
392 int flt_reg = 0; | |
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393 int slot = 0; |
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394 |
0 | 395 for (int i = 0; i < total_args_passed; i++) { |
396 switch (sig_bt[i]) { | |
397 case T_INT: | |
398 case T_SHORT: | |
399 case T_CHAR: | |
400 case T_BYTE: | |
401 case T_BOOLEAN: | |
402 #ifndef _LP64 | |
403 case T_OBJECT: | |
404 case T_ARRAY: | |
405 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
406 #endif // _LP64 | |
407 if (int_reg < int_reg_max) { | |
408 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
409 regs[i].set1(r->as_VMReg()); | |
410 } else { | |
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411 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
0 | 412 } |
413 break; | |
414 | |
415 #ifdef _LP64 | |
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416 case T_LONG: |
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417 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); |
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418 // fall-through |
0 | 419 case T_OBJECT: |
420 case T_ARRAY: | |
421 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
422 if (int_reg < int_reg_max) { | |
423 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
424 regs[i].set2(r->as_VMReg()); | |
425 } else { | |
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426 slot = round_to(slot, 2); // align |
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427 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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428 slot += 2; |
0 | 429 } |
430 break; | |
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431 #else |
0 | 432 case T_LONG: |
433 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | |
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434 // On 32-bit SPARC put longs always on the stack to keep the pressure off |
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435 // integer argument registers. They should be used for oops. |
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436 slot = round_to(slot, 2); // align |
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437 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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438 slot += 2; |
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439 #endif |
0 | 440 break; |
441 | |
442 case T_FLOAT: | |
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443 if (flt_reg < flt_reg_max) { |
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444 FloatRegister r = as_FloatRegister(flt_reg++); |
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445 regs[i].set1(r->as_VMReg()); |
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446 } else { |
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447 regs[i].set1(VMRegImpl::stack2reg(slot++)); |
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448 } |
0 | 449 break; |
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450 |
0 | 451 case T_DOUBLE: |
452 assert(sig_bt[i+1] == T_VOID, "expecting half"); | |
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453 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { |
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454 flt_reg = round_to(flt_reg, 2); // align |
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455 FloatRegister r = as_FloatRegister(flt_reg); |
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456 regs[i].set2(r->as_VMReg()); |
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457 flt_reg += 2; |
0 | 458 } else { |
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459 slot = round_to(slot, 2); // align |
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460 regs[i].set2(VMRegImpl::stack2reg(slot)); |
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461 slot += 2; |
0 | 462 } |
463 break; | |
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464 |
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465 case T_VOID: |
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466 regs[i].set_bad(); // Halves of longs & doubles |
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467 break; |
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468 |
0 | 469 default: |
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470 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); |
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471 break; |
0 | 472 } |
473 } | |
474 | |
475 // retun the amount of stack space these arguments will need. | |
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476 return slot; |
0 | 477 } |
478 | |
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479 // Helper class mostly to avoid passing masm everywhere, and handle |
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480 // store displacement overflow logic. |
0 | 481 class AdapterGenerator { |
482 MacroAssembler *masm; | |
483 Register Rdisp; | |
484 void set_Rdisp(Register r) { Rdisp = r; } | |
485 | |
486 void patch_callers_callsite(); | |
487 | |
488 // base+st_off points to top of argument | |
1506 | 489 int arg_offset(const int st_off) { return st_off; } |
0 | 490 int next_arg_offset(const int st_off) { |
1506 | 491 return st_off - Interpreter::stackElementSize; |
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492 } |
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493 |
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494 // Argument slot values may be loaded first into a register because |
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495 // they might not fit into displacement. |
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496 RegisterOrConstant arg_slot(const int st_off); |
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497 RegisterOrConstant next_arg_slot(const int st_off); |
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498 |
0 | 499 // Stores long into offset pointed to by base |
500 void store_c2i_long(Register r, Register base, | |
501 const int st_off, bool is_stack); | |
502 void store_c2i_object(Register r, Register base, | |
503 const int st_off); | |
504 void store_c2i_int(Register r, Register base, | |
505 const int st_off); | |
506 void store_c2i_double(VMReg r_2, | |
507 VMReg r_1, Register base, const int st_off); | |
508 void store_c2i_float(FloatRegister f, Register base, | |
509 const int st_off); | |
510 | |
511 public: | |
512 void gen_c2i_adapter(int total_args_passed, | |
513 // VMReg max_arg, | |
514 int comp_args_on_stack, // VMRegStackSlots | |
515 const BasicType *sig_bt, | |
516 const VMRegPair *regs, | |
517 Label& skip_fixup); | |
518 void gen_i2c_adapter(int total_args_passed, | |
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519 // VMReg max_arg, |
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520 int comp_args_on_stack, // VMRegStackSlots |
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521 const BasicType *sig_bt, |
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522 const VMRegPair *regs); |
0 | 523 |
524 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} | |
525 }; | |
526 | |
527 | |
528 // Patch the callers callsite with entry to compiled code if it exists. | |
529 void AdapterGenerator::patch_callers_callsite() { | |
530 Label L; | |
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531 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
3839 | 532 __ br_null(G3_scratch, false, Assembler::pt, L); |
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533 __ delayed()->nop(); |
0 | 534 // Call into the VM to patch the caller, then jump to compiled callee |
535 __ save_frame(4); // Args in compiled layout; do not blow them | |
536 | |
537 // Must save all the live Gregs the list is: | |
538 // G1: 1st Long arg (32bit build) | |
539 // G2: global allocated to TLS | |
540 // G3: used in inline cache check (scratch) | |
541 // G4: 2nd Long arg (32bit build); | |
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542 // G5: used in inline cache check (Method*) |
0 | 543 |
544 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. | |
545 | |
546 #ifdef _LP64 | |
547 // mov(s,d) | |
548 __ mov(G1, L1); | |
549 __ mov(G4, L4); | |
550 __ mov(G5_method, L5); | |
551 __ mov(G5_method, O0); // VM needs target method | |
552 __ mov(I7, O1); // VM needs caller's callsite | |
553 // Must be a leaf call... | |
554 // can be very far once the blob has been relocated | |
727 | 555 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); |
0 | 556 __ relocate(relocInfo::runtime_call_type); |
727 | 557 __ jumpl_to(dest, O7, O7); |
0 | 558 __ delayed()->mov(G2_thread, L7_thread_cache); |
559 __ mov(L7_thread_cache, G2_thread); | |
560 __ mov(L1, G1); | |
561 __ mov(L4, G4); | |
562 __ mov(L5, G5_method); | |
563 #else | |
564 __ stx(G1, FP, -8 + STACK_BIAS); | |
565 __ stx(G4, FP, -16 + STACK_BIAS); | |
566 __ mov(G5_method, L5); | |
567 __ mov(G5_method, O0); // VM needs target method | |
568 __ mov(I7, O1); // VM needs caller's callsite | |
569 // Must be a leaf call... | |
570 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); | |
571 __ delayed()->mov(G2_thread, L7_thread_cache); | |
572 __ mov(L7_thread_cache, G2_thread); | |
573 __ ldx(FP, -8 + STACK_BIAS, G1); | |
574 __ ldx(FP, -16 + STACK_BIAS, G4); | |
575 __ mov(L5, G5_method); | |
576 #endif /* _LP64 */ | |
577 | |
578 __ restore(); // Restore args | |
579 __ bind(L); | |
580 } | |
581 | |
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582 |
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583 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { |
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584 RegisterOrConstant roc(arg_offset(st_off)); |
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585 return __ ensure_simm13_or_reg(roc, Rdisp); |
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586 } |
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587 |
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588 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { |
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589 RegisterOrConstant roc(next_arg_offset(st_off)); |
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590 return __ ensure_simm13_or_reg(roc, Rdisp); |
0 | 591 } |
592 | |
1006
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593 |
0 | 594 // Stores long into offset pointed to by base |
595 void AdapterGenerator::store_c2i_long(Register r, Register base, | |
596 const int st_off, bool is_stack) { | |
597 #ifdef _LP64 | |
598 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
599 // data is passed in only 1 slot. | |
600 __ stx(r, base, next_arg_slot(st_off)); | |
601 #else | |
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602 #ifdef COMPILER2 |
0 | 603 // Misaligned store of 64-bit data |
604 __ stw(r, base, arg_slot(st_off)); // lo bits | |
605 __ srlx(r, 32, r); | |
606 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
607 #else | |
608 if (is_stack) { | |
609 // Misaligned store of 64-bit data | |
610 __ stw(r, base, arg_slot(st_off)); // lo bits | |
611 __ srlx(r, 32, r); | |
612 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
613 } else { | |
614 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits | |
615 __ stw(r , base, next_arg_slot(st_off)); // hi bits | |
616 } | |
617 #endif // COMPILER2 | |
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618 #endif // _LP64 |
0 | 619 } |
620 | |
621 void AdapterGenerator::store_c2i_object(Register r, Register base, | |
622 const int st_off) { | |
623 __ st_ptr (r, base, arg_slot(st_off)); | |
624 } | |
625 | |
626 void AdapterGenerator::store_c2i_int(Register r, Register base, | |
627 const int st_off) { | |
628 __ st (r, base, arg_slot(st_off)); | |
629 } | |
630 | |
631 // Stores into offset pointed to by base | |
632 void AdapterGenerator::store_c2i_double(VMReg r_2, | |
633 VMReg r_1, Register base, const int st_off) { | |
634 #ifdef _LP64 | |
635 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
636 // data is passed in only 1 slot. | |
637 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
638 #else | |
639 // Need to marshal 64-bit value from misaligned Lesp loads | |
640 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
641 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); | |
642 #endif | |
643 } | |
644 | |
645 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, | |
646 const int st_off) { | |
647 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); | |
648 } | |
649 | |
650 void AdapterGenerator::gen_c2i_adapter( | |
651 int total_args_passed, | |
652 // VMReg max_arg, | |
653 int comp_args_on_stack, // VMRegStackSlots | |
654 const BasicType *sig_bt, | |
655 const VMRegPair *regs, | |
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656 Label& L_skip_fixup) { |
0 | 657 |
658 // Before we get into the guts of the C2I adapter, see if we should be here | |
659 // at all. We've come from compiled code and are attempting to jump to the | |
660 // interpreter, which means the caller made a static call to get here | |
661 // (vcalls always get a compiled target if there is one). Check for a | |
662 // compiled target. If there is one, we need to patch the caller's call. | |
663 // However we will run interpreted if we come thru here. The next pass | |
664 // thru the call site will run compiled. If we ran compiled here then | |
665 // we can (theorectically) do endless i2c->c2i->i2c transitions during | |
666 // deopt/uncommon trap cycles. If we always go interpreted here then | |
667 // we can have at most one and don't need to play any tricks to keep | |
668 // from endlessly growing the stack. | |
669 // | |
670 // Actually if we detected that we had an i2c->c2i transition here we | |
671 // ought to be able to reset the world back to the state of the interpreted | |
672 // call and not bother building another interpreter arg area. We don't | |
673 // do that at this point. | |
674 | |
675 patch_callers_callsite(); | |
676 | |
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677 __ bind(L_skip_fixup); |
0 | 678 |
679 // Since all args are passed on the stack, total_args_passed*wordSize is the | |
680 // space we need. Add in varargs area needed by the interpreter. Round up | |
681 // to stack alignment. | |
1506 | 682 const int arg_size = total_args_passed * Interpreter::stackElementSize; |
0 | 683 const int varargs_area = |
684 (frame::varargs_offset - frame::register_save_words)*wordSize; | |
685 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); | |
686 | |
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687 const int bias = STACK_BIAS; |
0 | 688 const int interp_arg_offset = frame::varargs_offset*wordSize + |
1506 | 689 (total_args_passed-1)*Interpreter::stackElementSize; |
0 | 690 |
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691 const Register base = SP; |
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692 |
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693 // Make some extra space on the stack. |
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694 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); |
0 | 695 set_Rdisp(G3_scratch); |
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696 |
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697 // Write the args into the outgoing interpreter space. |
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698 for (int i = 0; i < total_args_passed; i++) { |
1506 | 699 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
0 | 700 VMReg r_1 = regs[i].first(); |
701 VMReg r_2 = regs[i].second(); | |
702 if (!r_1->is_valid()) { | |
703 assert(!r_2->is_valid(), ""); | |
704 continue; | |
705 } | |
706 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 | |
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707 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; |
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708 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); |
0 | 709 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle |
710 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); | |
711 else __ ldx(base, ld_off, G1_scratch); | |
712 } | |
713 | |
714 if (r_1->is_Register()) { | |
715 Register r = r_1->as_Register()->after_restore(); | |
716 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
717 store_c2i_object(r, base, st_off); | |
718 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
719 store_c2i_long(r, base, st_off, r_2->is_stack()); | |
720 } else { | |
721 store_c2i_int(r, base, st_off); | |
722 } | |
723 } else { | |
724 assert(r_1->is_FloatRegister(), ""); | |
725 if (sig_bt[i] == T_FLOAT) { | |
726 store_c2i_float(r_1->as_FloatRegister(), base, st_off); | |
727 } else { | |
728 assert(sig_bt[i] == T_DOUBLE, "wrong type"); | |
729 store_c2i_double(r_2, r_1, base, st_off); | |
730 } | |
731 } | |
732 } | |
733 | |
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734 // Load the interpreter entry point. |
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735 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); |
0 | 736 |
737 // Pass O5_savedSP as an argument to the interpreter. | |
738 // The interpreter will restore SP to this value before returning. | |
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739 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); |
0 | 740 |
741 __ mov((frame::varargs_offset)*wordSize - | |
1506 | 742 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); |
0 | 743 // Jump to the interpreter just as if interpreter was doing it. |
744 __ jmpl(G3_scratch, 0, G0); | |
745 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp | |
746 // (really L0) is in use by the compiled frame as a generic temp. However, | |
747 // the interpreter does not know where its args are without some kind of | |
748 // arg pointer being passed in. Pass it in Gargs. | |
749 __ delayed()->add(SP, G1, Gargs); | |
750 } | |
751 | |
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752 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg, |
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753 address code_start, address code_end, |
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754 Label& L_ok) { |
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755 Label L_fail; |
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756 __ set(ExternalAddress(code_start), temp_reg); |
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757 __ set(pointer_delta(code_end, code_start, 1), temp2_reg); |
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758 __ cmp(pc_reg, temp_reg); |
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759 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail); |
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760 __ delayed()->add(temp_reg, temp2_reg, temp_reg); |
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761 __ cmp(pc_reg, temp_reg); |
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762 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok); |
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763 __ bind(L_fail); |
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764 } |
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765 |
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766 void AdapterGenerator::gen_i2c_adapter(int total_args_passed, |
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767 // VMReg max_arg, |
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768 int comp_args_on_stack, // VMRegStackSlots |
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769 const BasicType *sig_bt, |
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770 const VMRegPair *regs) { |
0 | 771 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame |
772 // layout. Lesp was saved by the calling I-frame and will be restored on | |
773 // return. Meanwhile, outgoing arg space is all owned by the callee | |
774 // C-frame, so we can mangle it at will. After adjusting the frame size, | |
775 // hoist register arguments and repack other args according to the compiled | |
776 // code convention. Finally, end in a jump to the compiled code. The entry | |
777 // point address is the start of the buffer. | |
778 | |
779 // We will only enter here from an interpreted frame and never from after | |
780 // passing thru a c2i. Azul allowed this but we do not. If we lose the | |
781 // race and use a c2i we will remain interpreted for the race loser(s). | |
782 // This removes all sorts of headaches on the x86 side and also eliminates | |
783 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. | |
784 | |
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785 // More detail: |
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786 // Adapters can be frameless because they do not require the caller |
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787 // to perform additional cleanup work, such as correcting the stack pointer. |
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788 // An i2c adapter is frameless because the *caller* frame, which is interpreted, |
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789 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), |
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790 // even if a callee has modified the stack pointer. |
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791 // A c2i adapter is frameless because the *callee* frame, which is interpreted, |
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792 // routinely repairs its caller's stack pointer (from sender_sp, which is set |
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793 // up via the senderSP register). |
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794 // In other words, if *either* the caller or callee is interpreted, we can |
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795 // get the stack pointer repaired after a call. |
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796 // This is why c2i and i2c adapters cannot be indefinitely composed. |
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797 // In particular, if a c2i adapter were to somehow call an i2c adapter, |
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798 // both caller and callee would be compiled methods, and neither would |
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799 // clean up the stack pointer changes performed by the two adapters. |
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800 // If this happens, control eventually transfers back to the compiled |
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801 // caller, but with an uncorrected stack, causing delayed havoc. |
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802 |
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803 if (VerifyAdapterCalls && |
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804 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { |
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805 // So, let's test for cascading c2i/i2c adapters right now. |
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806 // assert(Interpreter::contains($return_addr) || |
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807 // StubRoutines::contains($return_addr), |
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808 // "i2c adapter must return to an interpreter frame"); |
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809 __ block_comment("verify_i2c { "); |
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810 Label L_ok; |
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811 if (Interpreter::code() != NULL) |
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812 range_check(masm, O7, O0, O1, |
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813 Interpreter::code()->code_start(), Interpreter::code()->code_end(), |
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814 L_ok); |
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815 if (StubRoutines::code1() != NULL) |
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816 range_check(masm, O7, O0, O1, |
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817 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), |
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818 L_ok); |
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819 if (StubRoutines::code2() != NULL) |
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820 range_check(masm, O7, O0, O1, |
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821 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), |
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822 L_ok); |
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823 const char* msg = "i2c adapter must return to an interpreter frame"; |
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824 __ block_comment(msg); |
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825 __ stop(msg); |
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826 __ bind(L_ok); |
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827 __ block_comment("} verify_i2ce "); |
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828 } |
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829 |
0 | 830 // As you can see from the list of inputs & outputs there are not a lot |
831 // of temp registers to work with: mostly G1, G3 & G4. | |
832 | |
833 // Inputs: | |
834 // G2_thread - TLS | |
835 // G5_method - Method oop | |
710 | 836 // G4 (Gargs) - Pointer to interpreter's args |
837 // O0..O4 - free for scratch | |
838 // O5_savedSP - Caller's saved SP, to be restored if needed | |
0 | 839 // O6 - Current SP! |
840 // O7 - Valid return address | |
710 | 841 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
0 | 842 |
843 // Outputs: | |
844 // G2_thread - TLS | |
845 // O0-O5 - Outgoing args in compiled layout | |
846 // O6 - Adjusted or restored SP | |
847 // O7 - Valid return address | |
1564 | 848 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
0 | 849 // F0-F7 - more outgoing args |
850 | |
851 | |
710 | 852 // Gargs is the incoming argument base, and also an outgoing argument. |
0 | 853 __ sub(Gargs, BytesPerWord, Gargs); |
854 | |
855 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME | |
856 // WITH O7 HOLDING A VALID RETURN PC | |
857 // | |
858 // | | | |
859 // : java stack : | |
860 // | | | |
861 // +--------------+ <--- start of outgoing args | |
862 // | receiver | | | |
863 // : rest of args : |---size is java-arg-words | |
864 // | | | | |
865 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I | |
866 // | | | | |
867 // : unused : |---Space for max Java stack, plus stack alignment | |
868 // | | | | |
869 // +--------------+ <--- SP + 16*wordsize | |
870 // | | | |
871 // : window : | |
872 // | | | |
873 // +--------------+ <--- SP | |
874 | |
875 // WE REPACK THE STACK. We use the common calling convention layout as | |
876 // discovered by calling SharedRuntime::calling_convention. We assume it | |
877 // causes an arbitrary shuffle of memory, which may require some register | |
878 // temps to do the shuffle. We hope for (and optimize for) the case where | |
879 // temps are not needed. We may have to resize the stack slightly, in case | |
880 // we need alignment padding (32-bit interpreter can pass longs & doubles | |
881 // misaligned, but the compilers expect them aligned). | |
882 // | |
883 // | | | |
884 // : java stack : | |
885 // | | | |
886 // +--------------+ <--- start of outgoing args | |
887 // | pad, align | | | |
888 // +--------------+ | | |
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889 // | ints, longs, | | |
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890 // | floats, | |---Outgoing stack args. |
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891 // : doubles : | First few args in registers. |
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892 // | | | |
0 | 893 // +--------------+ <--- SP' + 16*wordsize |
894 // | | | |
895 // : window : | |
896 // | | | |
897 // +--------------+ <--- SP' | |
898 | |
899 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME | |
900 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP | |
901 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. | |
902 | |
903 // Cut-out for having no stack args. Since up to 6 args are passed | |
904 // in registers, we will commonly have no stack args. | |
905 if (comp_args_on_stack > 0) { | |
906 // Convert VMReg stack slots to words. | |
907 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | |
908 // Round up to miminum stack alignment, in wordSize | |
909 comp_words_on_stack = round_to(comp_words_on_stack, 2); | |
910 // Now compute the distance from Lesp to SP. This calculation does not | |
911 // include the space for total_args_passed because Lesp has not yet popped | |
912 // the arguments. | |
913 __ sub(SP, (comp_words_on_stack)*wordSize, SP); | |
914 } | |
915 | |
916 // Now generate the shuffle code. Pick up all register args and move the | |
917 // rest through G1_scratch. | |
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918 for (int i = 0; i < total_args_passed; i++) { |
0 | 919 if (sig_bt[i] == T_VOID) { |
920 // Longs and doubles are passed in native word order, but misaligned | |
921 // in the 32-bit build. | |
922 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
923 continue; | |
924 } | |
925 | |
926 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the | |
927 // 32-bit build and aligned in the 64-bit build. Look for the obvious | |
928 // ldx/lddf optimizations. | |
929 | |
930 // Load in argument order going down. | |
1506 | 931 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; |
0 | 932 set_Rdisp(G1_scratch); |
933 | |
934 VMReg r_1 = regs[i].first(); | |
935 VMReg r_2 = regs[i].second(); | |
936 if (!r_1->is_valid()) { | |
937 assert(!r_2->is_valid(), ""); | |
938 continue; | |
939 } | |
940 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 | |
941 r_1 = F8->as_VMReg(); // as part of the load/store shuffle | |
942 if (r_2->is_valid()) r_2 = r_1->next(); | |
943 } | |
944 if (r_1->is_Register()) { // Register argument | |
945 Register r = r_1->as_Register()->after_restore(); | |
946 if (!r_2->is_valid()) { | |
947 __ ld(Gargs, arg_slot(ld_off), r); | |
948 } else { | |
949 #ifdef _LP64 | |
950 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
951 // data is passed in only 1 slot. | |
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952 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? |
0 | 953 next_arg_slot(ld_off) : arg_slot(ld_off); |
954 __ ldx(Gargs, slot, r); | |
955 #else | |
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956 fatal("longs should be on stack"); |
0 | 957 #endif |
958 } | |
959 } else { | |
960 assert(r_1->is_FloatRegister(), ""); | |
961 if (!r_2->is_valid()) { | |
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962 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); |
0 | 963 } else { |
964 #ifdef _LP64 | |
965 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
966 // data is passed in only 1 slot. This code also handles longs that | |
967 // are passed on the stack, but need a stack-to-stack move through a | |
968 // spare float register. | |
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969 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? |
0 | 970 next_arg_slot(ld_off) : arg_slot(ld_off); |
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971 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); |
0 | 972 #else |
973 // Need to marshal 64-bit value from misaligned Lesp loads | |
974 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); | |
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975 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); |
0 | 976 #endif |
977 } | |
978 } | |
979 // Was the argument really intended to be on the stack, but was loaded | |
980 // into F8/F9? | |
981 if (regs[i].first()->is_stack()) { | |
982 assert(r_1->as_FloatRegister() == F8, "fix this code"); | |
983 // Convert stack slot to an SP offset | |
984 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; | |
985 // Store down the shuffled stack word. Target address _is_ aligned. | |
1006
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986 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); |
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987 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); |
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988 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); |
0 | 989 } |
990 } | |
991 | |
992 // Jump to the compiled code just as if compiled code was doing it. | |
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993 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); |
22298 | 994 #if INCLUDE_JVMCI |
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995 // check if this call should be routed towards a specific entry point |
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996 __ ld(Address(G2_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), G1); |
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997 __ cmp(G0, G1); |
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998 Label no_alternative_target; |
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999 __ br(Assembler::equal, false, Assembler::pn, no_alternative_target); |
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1000 __ delayed()->nop(); |
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1001 |
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1002 __ ld_ptr(G2_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset()), G3); |
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1003 __ st(G0, Address(G2_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset()))); |
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1004 |
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1005 __ bind(no_alternative_target); |
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1006 #endif |
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1007 |
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1008 // 6243940 We might end up in handle_wrong_method if |
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1009 // the callee is deoptimized as we race thru here. If that |
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1010 // happens we don't want to take a safepoint because the |
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1011 // caller frame will look interpreted and arguments are now |
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1012 // "compiled" so it is much better to make this transition |
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1013 // invisible to the stack walking code. Unfortunately if |
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1014 // we try and find the callee by normal means a safepoint |
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1015 // is possible. So we stash the desired callee in the thread |
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1016 // and the vm will find there should this case occur. |
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1017 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); |
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1018 __ st_ptr(G5_method, callee_target_addr); |
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1019 __ jmpl(G3, 0, G0); |
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1020 __ delayed()->nop(); |
0 | 1021 } |
1022 | |
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1023 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, |
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1024 int total_args_passed, |
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1025 int comp_args_on_stack, |
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1026 const BasicType *sig_bt, |
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1027 const VMRegPair *regs) { |
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1028 AdapterGenerator agen(masm); |
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1029 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); |
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1030 } |
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1031 |
0 | 1032 // --------------------------------------------------------------- |
1033 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | |
1034 int total_args_passed, | |
1035 // VMReg max_arg, | |
1036 int comp_args_on_stack, // VMRegStackSlots | |
1037 const BasicType *sig_bt, | |
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1038 const VMRegPair *regs, |
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1039 AdapterFingerPrint* fingerprint) { |
0 | 1040 address i2c_entry = __ pc(); |
1041 | |
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1042 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); |
0 | 1043 |
1044 | |
1045 // ------------------------------------------------------------------------- | |
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1046 // Generate a C2I adapter. On entry we know G5 holds the Method*. The |
0 | 1047 // args start out packed in the compiled layout. They need to be unpacked |
1048 // into the interpreter layout. This will almost always require some stack | |
1049 // space. We grow the current (compiled) stack, then repack the args. We | |
1050 // finally end in a jump to the generic interpreter entry point. On exit | |
1051 // from the interpreter, the interpreter will restore our SP (lest the | |
1052 // compiled code, which relys solely on SP and not FP, get sick). | |
1053 | |
1054 address c2i_unverified_entry = __ pc(); | |
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1055 Label L_skip_fixup; |
0 | 1056 { |
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1057 Register R_temp = G1; // another scratch register |
0 | 1058 |
727 | 1059 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
0 | 1060 |
1061 __ verify_oop(O0); | |
113
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1062 __ load_klass(O0, G3_scratch); |
0 | 1063 |
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1064 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); |
0 | 1065 __ cmp(G3_scratch, R_temp); |
1066 | |
1067 Label ok, ok2; | |
1068 __ brx(Assembler::equal, false, Assembler::pt, ok); | |
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1069 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); |
727 | 1070 __ jump_to(ic_miss, G3_scratch); |
0 | 1071 __ delayed()->nop(); |
1072 | |
1073 __ bind(ok); | |
1074 // Method might have been compiled since the call site was patched to | |
1075 // interpreted if that is the case treat it as a miss so we can get | |
1076 // the call site corrected. | |
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1077 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); |
0 | 1078 __ bind(ok2); |
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1079 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); |
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1080 __ delayed()->nop(); |
727 | 1081 __ jump_to(ic_miss, G3_scratch); |
0 | 1082 __ delayed()->nop(); |
1083 | |
1084 } | |
1085 | |
1086 address c2i_entry = __ pc(); | |
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1087 AdapterGenerator agen(masm); |
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1088 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); |
0 | 1089 |
1090 __ flush(); | |
1187
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1091 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
0 | 1092 |
1093 } | |
1094 | |
1095 // Helper function for native calling conventions | |
1096 static VMReg int_stk_helper( int i ) { | |
1097 // Bias any stack based VMReg we get by ignoring the window area | |
1098 // but not the register parameter save area. | |
1099 // | |
1100 // This is strange for the following reasons. We'd normally expect | |
1101 // the calling convention to return an VMReg for a stack slot | |
1102 // completely ignoring any abi reserved area. C2 thinks of that | |
1103 // abi area as only out_preserve_stack_slots. This does not include | |
1104 // the area allocated by the C abi to store down integer arguments | |
1105 // because the java calling convention does not use it. So | |
1106 // since c2 assumes that there are only out_preserve_stack_slots | |
1107 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack | |
1108 // location the c calling convention must add in this bias amount | |
1109 // to make up for the fact that the out_preserve_stack_slots is | |
1110 // insufficient for C calls. What a mess. I sure hope those 6 | |
1111 // stack words were worth it on every java call! | |
1112 | |
1113 // Another way of cleaning this up would be for out_preserve_stack_slots | |
1114 // to take a parameter to say whether it was C or java calling conventions. | |
1115 // Then things might look a little better (but not much). | |
1116 | |
1117 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; | |
1118 if( mem_parm_offset < 0 ) { | |
1119 return as_oRegister(i)->as_VMReg(); | |
1120 } else { | |
1121 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; | |
1122 // Now return a biased offset that will be correct when out_preserve_slots is added back in | |
1123 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); | |
1124 } | |
1125 } | |
1126 | |
1127 | |
1128 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, | |
1129 VMRegPair *regs, | |
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1130 VMRegPair *regs2, |
0 | 1131 int total_args_passed) { |
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1132 assert(regs2 == NULL, "not needed on sparc"); |
0 | 1133 |
1134 // Return the number of VMReg stack_slots needed for the args. | |
1135 // This value does not include an abi space (like register window | |
1136 // save area). | |
1137 | |
1138 // The native convention is V8 if !LP64 | |
1139 // The LP64 convention is the V9 convention which is slightly more sane. | |
1140 | |
1141 // We return the amount of VMReg stack slots we need to reserve for all | |
1142 // the arguments NOT counting out_preserve_stack_slots. Since we always | |
1143 // have space for storing at least 6 registers to memory we start with that. | |
1144 // See int_stk_helper for a further discussion. | |
1145 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); | |
1146 | |
1147 #ifdef _LP64 | |
1148 // V9 convention: All things "as-if" on double-wide stack slots. | |
1149 // Hoist any int/ptr/long's in the first 6 to int regs. | |
1150 // Hoist any flt/dbl's in the first 16 dbl regs. | |
1151 int j = 0; // Count of actual args, not HALVES | |
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1152 VMRegPair param_array_reg; // location of the argument in the parameter array |
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1153 for (int i = 0; i < total_args_passed; i++, j++) { |
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1154 param_array_reg.set_bad(); |
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1155 switch (sig_bt[i]) { |
0 | 1156 case T_BOOLEAN: |
1157 case T_BYTE: | |
1158 case T_CHAR: | |
1159 case T_INT: | |
1160 case T_SHORT: | |
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1161 regs[i].set1(int_stk_helper(j)); |
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1162 break; |
0 | 1163 case T_LONG: |
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1164 assert(sig_bt[i+1] == T_VOID, "expecting half"); |
0 | 1165 case T_ADDRESS: // raw pointers, like current thread, for VM calls |
1166 case T_ARRAY: | |
1167 case T_OBJECT: | |
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1168 case T_METADATA: |
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1169 regs[i].set2(int_stk_helper(j)); |
0 | 1170 break; |
1171 case T_FLOAT: | |
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1172 // Per SPARC Compliance Definition 2.4.1, page 3P-12 available here |
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1173 // http://www.sparc.org/wp-content/uploads/2014/01/SCD.2.4.1.pdf.gz |
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1174 // |
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1175 // "When a callee prototype exists, and does not indicate variable arguments, |
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1176 // floating-point values assigned to locations %sp+BIAS+128 through %sp+BIAS+248 |
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1177 // will be promoted to floating-point registers" |
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1178 // |
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1179 // By "promoted" it means that the argument is located in two places, an unused |
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1180 // spill slot in the "parameter array" (starts at %sp+BIAS+128), and a live |
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1181 // float register. In most cases, there are 6 or fewer arguments of any type, |
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1182 // and the standard parameter array slots (%sp+BIAS+128 to %sp+BIAS+176 exclusive) |
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1183 // serve as shadow slots. Per the spec floating point registers %d6 to %d16 |
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1184 // require slots beyond that (up to %sp+BIAS+248). |
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1185 // |
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1186 { |
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1187 // V9ism: floats go in ODD registers and stack slots |
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1188 int float_index = 1 + (j << 1); |
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1189 param_array_reg.set1(VMRegImpl::stack2reg(float_index)); |
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1190 if (j < 16) { |
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1191 regs[i].set1(as_FloatRegister(float_index)->as_VMReg()); |
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1192 } else { |
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1193 regs[i] = param_array_reg; |
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1194 } |
0 | 1195 } |
1196 break; | |
1197 case T_DOUBLE: | |
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1198 { |
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1199 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
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1200 // V9ism: doubles go in EVEN/ODD regs and stack slots |
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1201 int double_index = (j << 1); |
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1202 param_array_reg.set2(VMRegImpl::stack2reg(double_index)); |
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1203 if (j < 16) { |
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1204 regs[i].set2(as_FloatRegister(double_index)->as_VMReg()); |
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1205 } else { |
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1206 // V9ism: doubles go in EVEN/ODD stack slots |
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1207 regs[i] = param_array_reg; |
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1208 } |
0 | 1209 } |
1210 break; | |
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1211 case T_VOID: |
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1212 regs[i].set_bad(); |
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1213 j--; |
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1214 break; // Do not count HALVES |
0 | 1215 default: |
1216 ShouldNotReachHere(); | |
1217 } | |
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1218 // Keep track of the deepest parameter array slot. |
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1219 if (!param_array_reg.first()->is_valid()) { |
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1220 param_array_reg = regs[i]; |
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1221 } |
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1222 if (param_array_reg.first()->is_stack()) { |
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1223 int off = param_array_reg.first()->reg2stack(); |
0 | 1224 if (off > max_stack_slots) max_stack_slots = off; |
1225 } | |
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1226 if (param_array_reg.second()->is_stack()) { |
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1227 int off = param_array_reg.second()->reg2stack(); |
0 | 1228 if (off > max_stack_slots) max_stack_slots = off; |
1229 } | |
1230 } | |
1231 | |
1232 #else // _LP64 | |
1233 // V8 convention: first 6 things in O-regs, rest on stack. | |
1234 // Alignment is willy-nilly. | |
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1235 for (int i = 0; i < total_args_passed; i++) { |
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1236 switch (sig_bt[i]) { |
0 | 1237 case T_ADDRESS: // raw pointers, like current thread, for VM calls |
1238 case T_ARRAY: | |
1239 case T_BOOLEAN: | |
1240 case T_BYTE: | |
1241 case T_CHAR: | |
1242 case T_FLOAT: | |
1243 case T_INT: | |
1244 case T_OBJECT: | |
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1245 case T_METADATA: |
0 | 1246 case T_SHORT: |
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1247 regs[i].set1(int_stk_helper(i)); |
0 | 1248 break; |
1249 case T_DOUBLE: | |
1250 case T_LONG: | |
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1251 assert(sig_bt[i + 1] == T_VOID, "expecting half"); |
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1252 regs[i].set_pair(int_stk_helper(i + 1), int_stk_helper(i)); |
0 | 1253 break; |
1254 case T_VOID: regs[i].set_bad(); break; | |
1255 default: | |
1256 ShouldNotReachHere(); | |
1257 } | |
1258 if (regs[i].first()->is_stack()) { | |
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1259 int off = regs[i].first()->reg2stack(); |
0 | 1260 if (off > max_stack_slots) max_stack_slots = off; |
1261 } | |
1262 if (regs[i].second()->is_stack()) { | |
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1263 int off = regs[i].second()->reg2stack(); |
0 | 1264 if (off > max_stack_slots) max_stack_slots = off; |
1265 } | |
1266 } | |
1267 #endif // _LP64 | |
1268 | |
1269 return round_to(max_stack_slots + 1, 2); | |
1270 | |
1271 } | |
1272 | |
1273 | |
1274 // --------------------------------------------------------------------------- | |
1275 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
1276 switch (ret_type) { | |
1277 case T_FLOAT: | |
1278 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); | |
1279 break; | |
1280 case T_DOUBLE: | |
1281 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); | |
1282 break; | |
1283 } | |
1284 } | |
1285 | |
1286 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
1287 switch (ret_type) { | |
1288 case T_FLOAT: | |
1289 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); | |
1290 break; | |
1291 case T_DOUBLE: | |
1292 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); | |
1293 break; | |
1294 } | |
1295 } | |
1296 | |
1297 // Check and forward and pending exception. Thread is stored in | |
1298 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there | |
1299 // is no exception handler. We merely pop this frame off and throw the | |
1300 // exception in the caller's frame. | |
1301 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { | |
1302 Label L; | |
1303 __ br_null(Rex_oop, false, Assembler::pt, L); | |
1304 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception | |
1305 // Since this is a native call, we *know* the proper exception handler | |
1306 // without calling into the VM: it's the empty function. Just pop this | |
1307 // frame and then jump to forward_exception_entry; O7 will contain the | |
1308 // native caller's return PC. | |
727 | 1309 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); |
1310 __ jump_to(exception_entry, G3_scratch); | |
0 | 1311 __ delayed()->restore(); // Pop this frame off. |
1312 __ bind(L); | |
1313 } | |
1314 | |
1315 // A simple move of integer like type | |
1316 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1317 if (src.first()->is_stack()) { | |
1318 if (dst.first()->is_stack()) { | |
1319 // stack to stack | |
1320 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1321 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1322 } else { | |
1323 // stack to reg | |
1324 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1325 } | |
1326 } else if (dst.first()->is_stack()) { | |
1327 // reg to stack | |
1328 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1329 } else { | |
1330 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1331 } | |
1332 } | |
1333 | |
1334 // On 64 bit we will store integer like items to the stack as | |
1335 // 64 bits items (sparc abi) even though java would only store | |
1336 // 32bits for a parameter. On 32bit it will simply be 32 bits | |
1337 // So this routine will do 32->32 on 32bit and 32->64 on 64bit | |
1338 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1339 if (src.first()->is_stack()) { | |
1340 if (dst.first()->is_stack()) { | |
1341 // stack to stack | |
1342 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1343 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1344 } else { | |
1345 // stack to reg | |
1346 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1347 } | |
1348 } else if (dst.first()->is_stack()) { | |
1349 // reg to stack | |
1350 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1351 } else { | |
1352 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1353 } | |
1354 } | |
1355 | |
1356 | |
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1357 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { |
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1358 if (src.first()->is_stack()) { |
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1359 if (dst.first()->is_stack()) { |
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1360 // stack to stack |
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1361 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); |
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1362 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); |
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1363 } else { |
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1364 // stack to reg |
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1365 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
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1366 } |
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1367 } else if (dst.first()->is_stack()) { |
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1368 // reg to stack |
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1369 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); |
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1370 } else { |
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1371 __ mov(src.first()->as_Register(), dst.first()->as_Register()); |
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1372 } |
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1373 } |
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1374 |
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1375 |
0 | 1376 // An oop arg. Must pass a handle not the oop itself |
1377 static void object_move(MacroAssembler* masm, | |
1378 OopMap* map, | |
1379 int oop_handle_offset, | |
1380 int framesize_in_slots, | |
1381 VMRegPair src, | |
1382 VMRegPair dst, | |
1383 bool is_receiver, | |
1384 int* receiver_offset) { | |
1385 | |
1386 // must pass a handle. First figure out the location we use as a handle | |
1387 | |
1388 if (src.first()->is_stack()) { | |
1389 // Oop is already on the stack | |
1390 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); | |
1391 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); | |
1392 __ ld_ptr(rHandle, 0, L4); | |
1393 #ifdef _LP64 | |
1394 __ movr( Assembler::rc_z, L4, G0, rHandle ); | |
1395 #else | |
1396 __ tst( L4 ); | |
1397 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
1398 #endif | |
1399 if (dst.first()->is_stack()) { | |
1400 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1401 } | |
1402 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); | |
1403 if (is_receiver) { | |
1404 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; | |
1405 } | |
1406 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); | |
1407 } else { | |
1408 // Oop is in an input register pass we must flush it to the stack | |
1409 const Register rOop = src.first()->as_Register(); | |
1410 const Register rHandle = L5; | |
1411 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; | |
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1412 int offset = oop_slot * VMRegImpl::stack_slot_size; |
0 | 1413 __ st_ptr(rOop, SP, offset + STACK_BIAS); |
1414 if (is_receiver) { | |
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1415 *receiver_offset = offset; |
0 | 1416 } |
1417 map->set_oop(VMRegImpl::stack2reg(oop_slot)); | |
1418 __ add(SP, offset + STACK_BIAS, rHandle); | |
1419 #ifdef _LP64 | |
1420 __ movr( Assembler::rc_z, rOop, G0, rHandle ); | |
1421 #else | |
1422 __ tst( rOop ); | |
1423 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
1424 #endif | |
1425 | |
1426 if (dst.first()->is_stack()) { | |
1427 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1428 } else { | |
1429 __ mov(rHandle, dst.first()->as_Register()); | |
1430 } | |
1431 } | |
1432 } | |
1433 | |
1434 // A float arg may have to do float reg int reg conversion | |
1435 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1436 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); | |
1437 | |
1438 if (src.first()->is_stack()) { | |
1439 if (dst.first()->is_stack()) { | |
1440 // stack to stack the easiest of the bunch | |
1441 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1442 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1443 } else { | |
1444 // stack to reg | |
1445 if (dst.first()->is_Register()) { | |
1446 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1447 } else { | |
1448 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1449 } | |
1450 } | |
1451 } else if (dst.first()->is_stack()) { | |
1452 // reg to stack | |
1453 if (src.first()->is_Register()) { | |
1454 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1455 } else { | |
1456 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1457 } | |
1458 } else { | |
1459 // reg to reg | |
1460 if (src.first()->is_Register()) { | |
1461 if (dst.first()->is_Register()) { | |
1462 // gpr -> gpr | |
1463 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1464 } else { | |
1465 // gpr -> fpr | |
1466 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); | |
1467 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1468 } | |
1469 } else if (dst.first()->is_Register()) { | |
1470 // fpr -> gpr | |
1471 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); | |
1472 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); | |
1473 } else { | |
1474 // fpr -> fpr | |
1475 // In theory these overlap but the ordering is such that this is likely a nop | |
1476 if ( src.first() != dst.first()) { | |
1477 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
1478 } | |
1479 } | |
1480 } | |
1481 } | |
1482 | |
1483 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1484 VMRegPair src_lo(src.first()); | |
1485 VMRegPair src_hi(src.second()); | |
1486 VMRegPair dst_lo(dst.first()); | |
1487 VMRegPair dst_hi(dst.second()); | |
1488 simple_move32(masm, src_lo, dst_lo); | |
1489 simple_move32(masm, src_hi, dst_hi); | |
1490 } | |
1491 | |
1492 // A long move | |
1493 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1494 | |
1495 // Do the simple ones here else do two int moves | |
1496 if (src.is_single_phys_reg() ) { | |
1497 if (dst.is_single_phys_reg()) { | |
1498 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1499 } else { | |
1500 // split src into two separate registers | |
1501 // Remember hi means hi address or lsw on sparc | |
1502 // Move msw to lsw | |
1503 if (dst.second()->is_reg()) { | |
1504 // MSW -> MSW | |
1505 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); | |
1506 // Now LSW -> LSW | |
1507 // this will only move lo -> lo and ignore hi | |
1508 VMRegPair split(dst.second()); | |
1509 simple_move32(masm, src, split); | |
1510 } else { | |
1511 VMRegPair split(src.first(), L4->as_VMReg()); | |
1512 // MSW -> MSW (lo ie. first word) | |
1513 __ srax(src.first()->as_Register(), 32, L4); | |
1514 split_long_move(masm, split, dst); | |
1515 } | |
1516 } | |
1517 } else if (dst.is_single_phys_reg()) { | |
1518 if (src.is_adjacent_aligned_on_stack(2)) { | |
304 | 1519 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
0 | 1520 } else { |
1521 // dst is a single reg. | |
1522 // Remember lo is low address not msb for stack slots | |
1523 // and lo is the "real" register for registers | |
1524 // src is | |
1525 | |
1526 VMRegPair split; | |
1527 | |
1528 if (src.first()->is_reg()) { | |
1529 // src.lo (msw) is a reg, src.hi is stk/reg | |
1530 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] | |
1531 split.set_pair(dst.first(), src.first()); | |
1532 } else { | |
1533 // msw is stack move to L5 | |
1534 // lsw is stack move to dst.lo (real reg) | |
1535 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 | |
1536 split.set_pair(dst.first(), L5->as_VMReg()); | |
1537 } | |
1538 | |
1539 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) | |
1540 // msw -> src.lo/L5, lsw -> dst.lo | |
1541 split_long_move(masm, src, split); | |
1542 | |
1543 // So dst now has the low order correct position the | |
1544 // msw half | |
1545 __ sllx(split.first()->as_Register(), 32, L5); | |
1546 | |
1547 const Register d = dst.first()->as_Register(); | |
1548 __ or3(L5, d, d); | |
1549 } | |
1550 } else { | |
1551 // For LP64 we can probably do better. | |
1552 split_long_move(masm, src, dst); | |
1553 } | |
1554 } | |
1555 | |
1556 // A double move | |
1557 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1558 | |
1559 // The painful thing here is that like long_move a VMRegPair might be | |
1560 // 1: a single physical register | |
1561 // 2: two physical registers (v8) | |
1562 // 3: a physical reg [lo] and a stack slot [hi] (v8) | |
1563 // 4: two stack slots | |
1564 | |
1565 // Since src is always a java calling convention we know that the src pair | |
1566 // is always either all registers or all stack (and aligned?) | |
1567 | |
1568 // in a register [lo] and a stack slot [hi] | |
1569 if (src.first()->is_stack()) { | |
1570 if (dst.first()->is_stack()) { | |
1571 // stack to stack the easiest of the bunch | |
1572 // ought to be a way to do this where if alignment is ok we use ldd/std when possible | |
1573 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1574 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1575 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1576 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1577 } else { | |
1578 // stack to reg | |
1579 if (dst.second()->is_stack()) { | |
1580 // stack -> reg, stack -> stack | |
1581 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1582 if (dst.first()->is_Register()) { | |
1583 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1584 } else { | |
1585 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1586 } | |
1587 // This was missing. (very rare case) | |
1588 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1589 } else { | |
1590 // stack -> reg | |
1591 // Eventually optimize for alignment QQQ | |
1592 if (dst.first()->is_Register()) { | |
1593 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1594 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); | |
1595 } else { | |
1596 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1597 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); | |
1598 } | |
1599 } | |
1600 } | |
1601 } else if (dst.first()->is_stack()) { | |
1602 // reg to stack | |
1603 if (src.first()->is_Register()) { | |
1604 // Eventually optimize for alignment QQQ | |
1605 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1606 if (src.second()->is_stack()) { | |
1607 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1608 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1609 } else { | |
1610 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
1611 } | |
1612 } else { | |
1613 // fpr to stack | |
1614 if (src.second()->is_stack()) { | |
1615 ShouldNotReachHere(); | |
1616 } else { | |
1617 // Is the stack aligned? | |
1618 if (reg2offset(dst.first()) & 0x7) { | |
1619 // No do as pairs | |
1620 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1621 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
1622 } else { | |
1623 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1624 } | |
1625 } | |
1626 } | |
1627 } else { | |
1628 // reg to reg | |
1629 if (src.first()->is_Register()) { | |
1630 if (dst.first()->is_Register()) { | |
1631 // gpr -> gpr | |
1632 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1633 __ mov(src.second()->as_Register(), dst.second()->as_Register()); | |
1634 } else { | |
1635 // gpr -> fpr | |
1636 // ought to be able to do a single store | |
1637 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); | |
1638 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); | |
1639 // ought to be able to do a single load | |
1640 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1641 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); | |
1642 } | |
1643 } else if (dst.first()->is_Register()) { | |
1644 // fpr -> gpr | |
1645 // ought to be able to do a single store | |
1646 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); | |
1647 // ought to be able to do a single load | |
1648 // REMEMBER first() is low address not LSB | |
1649 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); | |
1650 if (dst.second()->is_Register()) { | |
1651 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); | |
1652 } else { | |
1653 __ ld(FP, -4 + STACK_BIAS, L4); | |
1654 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1655 } | |
1656 } else { | |
1657 // fpr -> fpr | |
1658 // In theory these overlap but the ordering is such that this is likely a nop | |
1659 if ( src.first() != dst.first()) { | |
1660 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
1661 } | |
1662 } | |
1663 } | |
1664 } | |
1665 | |
1666 // Creates an inner frame if one hasn't already been created, and | |
1667 // saves a copy of the thread in L7_thread_cache | |
1668 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { | |
1669 if (!*already_created) { | |
1670 __ save_frame(0); | |
1671 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below | |
1672 // Don't use save_thread because it smashes G2 and we merely want to save a | |
1673 // copy | |
1674 __ mov(G2_thread, L7_thread_cache); | |
1675 *already_created = true; | |
1676 } | |
1677 } | |
1678 | |
4873
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1679 |
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1680 static void save_or_restore_arguments(MacroAssembler* masm, |
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1681 const int stack_slots, |
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1682 const int total_in_args, |
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1683 const int arg_save_area, |
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1684 OopMap* map, |
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1685 VMRegPair* in_regs, |
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1686 BasicType* in_sig_bt) { |
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1687 // if map is non-NULL then the code should store the values, |
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1688 // otherwise it should load them. |
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1689 if (map != NULL) { |
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1690 // Fill in the map |
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1691 for (int i = 0; i < total_in_args; i++) { |
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1692 if (in_sig_bt[i] == T_ARRAY) { |
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1693 if (in_regs[i].first()->is_stack()) { |
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1694 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); |
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1695 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); |
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1696 } else if (in_regs[i].first()->is_Register()) { |
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1697 map->set_oop(in_regs[i].first()); |
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1698 } else { |
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1699 ShouldNotReachHere(); |
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1700 } |
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1701 } |
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1702 } |
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1703 } |
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1704 |
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1705 // Save or restore double word values |
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1706 int handle_index = 0; |
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1707 for (int i = 0; i < total_in_args; i++) { |
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1708 int slot = handle_index + arg_save_area; |
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1709 int offset = slot * VMRegImpl::stack_slot_size; |
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1710 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { |
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1711 const Register reg = in_regs[i].first()->as_Register(); |
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1712 if (reg->is_global()) { |
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1713 handle_index += 2; |
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1714 assert(handle_index <= stack_slots, "overflow"); |
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1715 if (map != NULL) { |
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1716 __ stx(reg, SP, offset + STACK_BIAS); |
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1717 } else { |
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1718 __ ldx(SP, offset + STACK_BIAS, reg); |
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1719 } |
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1720 } |
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1721 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { |
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1722 handle_index += 2; |
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1723 assert(handle_index <= stack_slots, "overflow"); |
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1724 if (map != NULL) { |
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1725 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1726 } else { |
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1727 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1728 } |
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1729 } |
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1730 } |
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1731 // Save floats |
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1732 for (int i = 0; i < total_in_args; i++) { |
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1733 int slot = handle_index + arg_save_area; |
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1734 int offset = slot * VMRegImpl::stack_slot_size; |
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1735 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { |
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1736 handle_index++; |
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1737 assert(handle_index <= stack_slots, "overflow"); |
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1738 if (map != NULL) { |
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1739 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1740 } else { |
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1741 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1742 } |
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1743 } |
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1744 } |
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1745 |
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1746 } |
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1747 |
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1748 |
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1749 // Check GC_locker::needs_gc and enter the runtime if it's true. This |
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1750 // keeps a new JNI critical region from starting until a GC has been |
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1751 // forced. Save down any oops in registers and describe them in an |
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1752 // OopMap. |
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1753 static void check_needs_gc_for_critical_native(MacroAssembler* masm, |
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1754 const int stack_slots, |
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1755 const int total_in_args, |
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1756 const int arg_save_area, |
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1757 OopMapSet* oop_maps, |
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1758 VMRegPair* in_regs, |
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1759 BasicType* in_sig_bt) { |
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1760 __ block_comment("check GC_locker::needs_gc"); |
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1761 Label cont; |
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1762 AddressLiteral sync_state(GC_locker::needs_gc_address()); |
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1763 __ load_bool_contents(sync_state, G3_scratch); |
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1764 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); |
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1765 __ delayed()->nop(); |
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1766 |
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1767 // Save down any values that are live in registers and call into the |
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1768 // runtime to halt for a GC |
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1769 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1770 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1771 arg_save_area, map, in_regs, in_sig_bt); |
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1772 |
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1773 __ mov(G2_thread, L7_thread_cache); |
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1774 |
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1775 __ set_last_Java_frame(SP, noreg); |
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1776 |
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1777 __ block_comment("block_for_jni_critical"); |
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1778 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); |
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1779 __ delayed()->mov(L7_thread_cache, O0); |
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1780 oop_maps->add_gc_map( __ offset(), map); |
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1781 |
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1782 __ restore_thread(L7_thread_cache); // restore G2_thread |
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1783 __ reset_last_Java_frame(); |
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1784 |
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1785 // Reload all the register arguments |
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1786 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1787 arg_save_area, NULL, in_regs, in_sig_bt); |
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1788 |
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1789 __ bind(cont); |
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1790 #ifdef ASSERT |
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1791 if (StressCriticalJNINatives) { |
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1792 // Stress register saving |
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1793 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1794 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1795 arg_save_area, map, in_regs, in_sig_bt); |
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1796 // Destroy argument registers |
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1797 for (int i = 0; i < total_in_args; i++) { |
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1798 if (in_regs[i].first()->is_Register()) { |
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1799 const Register reg = in_regs[i].first()->as_Register(); |
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1800 if (reg->is_global()) { |
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1801 __ mov(G0, reg); |
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1802 } |
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1803 } else if (in_regs[i].first()->is_FloatRegister()) { |
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1804 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); |
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1805 } |
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1806 } |
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1807 |
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1808 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1809 arg_save_area, NULL, in_regs, in_sig_bt); |
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1810 } |
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1811 #endif |
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1812 } |
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1813 |
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1814 // Unpack an array argument into a pointer to the body and the length |
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1815 // if the array is non-null, otherwise pass 0 for both. |
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1816 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { |
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1817 // Pass the length, ptr pair |
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1818 Label is_null, done; |
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1819 if (reg.first()->is_stack()) { |
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1820 VMRegPair tmp = reg64_to_VMRegPair(L2); |
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1821 // Load the arg up from the stack |
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1822 move_ptr(masm, reg, tmp); |
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1823 reg = tmp; |
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1824 } |
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1825 __ cmp(reg.first()->as_Register(), G0); |
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1826 __ brx(Assembler::equal, false, Assembler::pt, is_null); |
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1827 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); |
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1828 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); |
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1829 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); |
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1830 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); |
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1831 __ ba_short(done); |
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1832 __ bind(is_null); |
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1833 // Pass zeros |
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1834 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); |
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1835 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); |
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1836 __ bind(done); |
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1837 } |
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1838 |
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1839 static void verify_oop_args(MacroAssembler* masm, |
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1840 methodHandle method, |
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1841 const BasicType* sig_bt, |
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1842 const VMRegPair* regs) { |
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1843 Register temp_reg = G5_method; // not part of any compiled calling seq |
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1844 if (VerifyOops) { |
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1845 for (int i = 0; i < method->size_of_parameters(); i++) { |
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1846 if (sig_bt[i] == T_OBJECT || |
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1847 sig_bt[i] == T_ARRAY) { |
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1848 VMReg r = regs[i].first(); |
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1849 assert(r->is_valid(), "bad oop arg"); |
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1850 if (r->is_stack()) { |
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1851 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1852 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg); |
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1853 __ ld_ptr(SP, ld_off, temp_reg); |
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1854 __ verify_oop(temp_reg); |
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1855 } else { |
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1856 __ verify_oop(r->as_Register()); |
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1857 } |
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1858 } |
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1859 } |
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1860 } |
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1861 } |
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1862 |
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1863 static void gen_special_dispatch(MacroAssembler* masm, |
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1864 methodHandle method, |
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1865 const BasicType* sig_bt, |
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1866 const VMRegPair* regs) { |
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1867 verify_oop_args(masm, method, sig_bt, regs); |
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1868 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1869 |
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1870 // Now write the args into the outgoing interpreter space |
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1871 bool has_receiver = false; |
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1872 Register receiver_reg = noreg; |
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1873 int member_arg_pos = -1; |
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1874 Register member_reg = noreg; |
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1875 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); |
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1876 if (ref_kind != 0) { |
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1877 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument |
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1878 member_reg = G5_method; // known to be free at this point |
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1879 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); |
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1880 } else if (iid == vmIntrinsics::_invokeBasic) { |
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1881 has_receiver = true; |
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1882 } else { |
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1883 fatal(err_msg_res("unexpected intrinsic id %d", iid)); |
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1884 } |
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1885 |
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1886 if (member_reg != noreg) { |
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1887 // Load the member_arg into register, if necessary. |
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1888 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); |
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1889 VMReg r = regs[member_arg_pos].first(); |
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1890 if (r->is_stack()) { |
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1891 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1892 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1893 __ ld_ptr(SP, ld_off, member_reg); |
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1894 } else { |
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1895 // no data motion is needed |
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1896 member_reg = r->as_Register(); |
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1897 } |
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1898 } |
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1899 |
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1900 if (has_receiver) { |
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1901 // Make sure the receiver is loaded into a register. |
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1902 assert(method->size_of_parameters() > 0, "oob"); |
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1903 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); |
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1904 VMReg r = regs[0].first(); |
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1905 assert(r->is_valid(), "bad receiver arg"); |
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1906 if (r->is_stack()) { |
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1907 // Porting note: This assumes that compiled calling conventions always |
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1908 // pass the receiver oop in a register. If this is not true on some |
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1909 // platform, pick a temp and load the receiver from stack. |
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1910 fatal("receiver always in a register"); |
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1911 receiver_reg = G3_scratch; // known to be free at this point |
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1912 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; |
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1913 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); |
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1914 __ ld_ptr(SP, ld_off, receiver_reg); |
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1915 } else { |
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1916 // no data motion is needed |
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1917 receiver_reg = r->as_Register(); |
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1918 } |
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1919 } |
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1920 |
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1921 // Figure out which address we are really jumping to: |
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1922 MethodHandles::generate_method_handle_dispatch(masm, iid, |
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1923 receiver_reg, member_reg, /*for_compiler_entry:*/ true); |
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1924 } |
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1925 |
0 | 1926 // --------------------------------------------------------------------------- |
1927 // Generate a native wrapper for a given method. The method takes arguments | |
1928 // in the Java compiled code convention, marshals them to the native | |
1929 // convention (handlizes oops, etc), transitions to native, makes the call, | |
1930 // returns to java state (possibly blocking), unhandlizes any result and | |
1931 // returns. | |
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1932 // |
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1933 // Critical native functions are a shorthand for the use of |
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1934 // GetPrimtiveArrayCritical and disallow the use of any other JNI |
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1935 // functions. The wrapper is expected to unpack the arguments before |
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1936 // passing them to the callee and perform checks before and after the |
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1937 // native call to ensure that they GC_locker |
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1938 // lock_critical/unlock_critical semantics are followed. Some other |
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1939 // parts of JNI setup are skipped like the tear down of the JNI handle |
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1940 // block and the check for pending exceptions it's impossible for them |
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1941 // to be thrown. |
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1942 // |
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1943 // They are roughly structured like this: |
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1944 // if (GC_locker::needs_gc()) |
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1945 // SharedRuntime::block_for_jni_critical(); |
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1946 // tranistion to thread_in_native |
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1947 // unpack arrray arguments and call native entry point |
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1948 // check for safepoint in progress |
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1949 // check if any thread suspend flags are set |
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1950 // call into JVM and possible unlock the JNI critical |
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1951 // if a GC was suppressed while in the critical native. |
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1952 // transition back to thread_in_Java |
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1953 // return to caller |
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1954 // |
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1955 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, |
0 | 1956 methodHandle method, |
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1957 int compile_id, |
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1958 BasicType* in_sig_bt, |
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1959 VMRegPair* in_regs, |
0 | 1960 BasicType ret_type) { |
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1961 if (method->is_method_handle_intrinsic()) { |
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1962 vmIntrinsics::ID iid = method->intrinsic_id(); |
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1963 intptr_t start = (intptr_t)__ pc(); |
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1964 int vep_offset = ((intptr_t)__ pc()) - start; |
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1965 gen_special_dispatch(masm, |
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1966 method, |
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1967 in_sig_bt, |
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1968 in_regs); |
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1969 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period |
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1970 __ flush(); |
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1971 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually |
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1972 return nmethod::new_native_nmethod(method, |
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1973 compile_id, |
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1974 masm->code(), |
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1975 vep_offset, |
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1976 frame_complete, |
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1977 stack_slots / VMRegImpl::slots_per_word, |
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1978 in_ByteSize(-1), |
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1979 in_ByteSize(-1), |
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1980 (OopMapSet*)NULL); |
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1981 } |
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1982 bool is_critical_native = true; |
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1983 address native_func = method->critical_native_function(); |
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1984 if (native_func == NULL) { |
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1985 native_func = method->native_function(); |
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1986 is_critical_native = false; |
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1987 } |
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1988 assert(native_func != NULL, "must have function"); |
0 | 1989 |
1990 // Native nmethod wrappers never take possesion of the oop arguments. | |
1991 // So the caller will gc the arguments. The only thing we need an | |
1992 // oopMap for is if the call is static | |
1993 // | |
1994 // An OopMap for lock (and class if static), and one for the VM call itself | |
1995 OopMapSet *oop_maps = new OopMapSet(); | |
1996 intptr_t start = (intptr_t)__ pc(); | |
1997 | |
1998 // First thing make an ic check to see if we should even be here | |
1999 { | |
2000 Label L; | |
2001 const Register temp_reg = G3_scratch; | |
727 | 2002 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
0 | 2003 __ verify_oop(O0); |
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2004 __ load_klass(O0, temp_reg); |
3839 | 2005 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
0 | 2006 |
727 | 2007 __ jump_to(ic_miss, temp_reg); |
0 | 2008 __ delayed()->nop(); |
2009 __ align(CodeEntryAlignment); | |
2010 __ bind(L); | |
2011 } | |
2012 | |
2013 int vep_offset = ((intptr_t)__ pc()) - start; | |
2014 | |
2015 #ifdef COMPILER1 | |
2016 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { | |
2017 // Object.hashCode can pull the hashCode from the header word | |
2018 // instead of doing a full VM transition once it's been computed. | |
2019 // Since hashCode is usually polymorphic at call sites we can't do | |
2020 // this optimization at the call site without a lot of work. | |
2021 Label slowCase; | |
2022 Register receiver = O0; | |
2023 Register result = O0; | |
2024 Register header = G3_scratch; | |
2025 Register hash = G3_scratch; // overwrite header value with hash value | |
2026 Register mask = G1; // to get hash field from header | |
2027 | |
2028 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. | |
2029 // We depend on hash_mask being at most 32 bits and avoid the use of | |
2030 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit | |
2031 // vm: see markOop.hpp. | |
2032 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); | |
2033 __ sethi(markOopDesc::hash_mask, mask); | |
2034 __ btst(markOopDesc::unlocked_value, header); | |
2035 __ br(Assembler::zero, false, Assembler::pn, slowCase); | |
2036 if (UseBiasedLocking) { | |
2037 // Check if biased and fall through to runtime if so | |
2038 __ delayed()->nop(); | |
2039 __ btst(markOopDesc::biased_lock_bit_in_place, header); | |
2040 __ br(Assembler::notZero, false, Assembler::pn, slowCase); | |
2041 } | |
2042 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); | |
2043 | |
2044 // Check for a valid (non-zero) hash code and get its value. | |
2045 #ifdef _LP64 | |
2046 __ srlx(header, markOopDesc::hash_shift, hash); | |
2047 #else | |
2048 __ srl(header, markOopDesc::hash_shift, hash); | |
2049 #endif | |
2050 __ andcc(hash, mask, hash); | |
2051 __ br(Assembler::equal, false, Assembler::pn, slowCase); | |
2052 __ delayed()->nop(); | |
2053 | |
2054 // leaf return. | |
2055 __ retl(); | |
2056 __ delayed()->mov(hash, result); | |
2057 __ bind(slowCase); | |
2058 } | |
2059 #endif // COMPILER1 | |
2060 | |
2061 | |
2062 // We have received a description of where all the java arg are located | |
2063 // on entry to the wrapper. We need to convert these args to where | |
2064 // the jni function will expect them. To figure out where they go | |
2065 // we convert the java signature to a C signature by inserting | |
2066 // the hidden arguments as arg[0] and possibly arg[1] (static method) | |
2067 | |
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2068 const int total_in_args = method->size_of_parameters(); |
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2069 int total_c_args = total_in_args; |
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2070 int total_save_slots = 6 * VMRegImpl::slots_per_word; |
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2071 if (!is_critical_native) { |
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2072 total_c_args += 1; |
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2073 if (method->is_static()) { |
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2074 total_c_args++; |
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2075 } |
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2076 } else { |
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2077 for (int i = 0; i < total_in_args; i++) { |
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2078 if (in_sig_bt[i] == T_ARRAY) { |
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2079 // These have to be saved and restored across the safepoint |
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2080 total_c_args++; |
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2081 } |
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2082 } |
0 | 2083 } |
2084 | |
2085 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); | |
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2086 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); |
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2087 BasicType* in_elem_bt = NULL; |
0 | 2088 |
2089 int argc = 0; | |
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2090 if (!is_critical_native) { |
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2091 out_sig_bt[argc++] = T_ADDRESS; |
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2092 if (method->is_static()) { |
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2093 out_sig_bt[argc++] = T_OBJECT; |
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2094 } |
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2095 |
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2096 for (int i = 0; i < total_in_args ; i++ ) { |
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2097 out_sig_bt[argc++] = in_sig_bt[i]; |
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2098 } |
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2099 } else { |
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2100 Thread* THREAD = Thread::current(); |
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2101 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); |
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2102 SignatureStream ss(method->signature()); |
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2103 for (int i = 0; i < total_in_args ; i++ ) { |
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2104 if (in_sig_bt[i] == T_ARRAY) { |
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2105 // Arrays are passed as int, elem* pair |
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2106 out_sig_bt[argc++] = T_INT; |
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2107 out_sig_bt[argc++] = T_ADDRESS; |
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2108 Symbol* atype = ss.as_symbol(CHECK_NULL); |
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2109 const char* at = atype->as_C_string(); |
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2110 if (strlen(at) == 2) { |
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2111 assert(at[0] == '[', "must be"); |
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2112 switch (at[1]) { |
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2113 case 'B': in_elem_bt[i] = T_BYTE; break; |
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2114 case 'C': in_elem_bt[i] = T_CHAR; break; |
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2115 case 'D': in_elem_bt[i] = T_DOUBLE; break; |
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2116 case 'F': in_elem_bt[i] = T_FLOAT; break; |
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2117 case 'I': in_elem_bt[i] = T_INT; break; |
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2118 case 'J': in_elem_bt[i] = T_LONG; break; |
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2119 case 'S': in_elem_bt[i] = T_SHORT; break; |
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2120 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; |
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2121 default: ShouldNotReachHere(); |
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2122 } |
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2123 } |
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2124 } else { |
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2125 out_sig_bt[argc++] = in_sig_bt[i]; |
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2126 in_elem_bt[i] = T_VOID; |
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2127 } |
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2128 if (in_sig_bt[i] != T_VOID) { |
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2129 assert(in_sig_bt[i] == ss.type(), "must match"); |
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2130 ss.next(); |
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2131 } |
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2132 } |
0 | 2133 } |
2134 | |
2135 // Now figure out where the args must be stored and how much stack space | |
2136 // they require (neglecting out_preserve_stack_slots but space for storing | |
2137 // the 1st six register arguments). It's weird see int_stk_helper. | |
2138 // | |
2139 int out_arg_slots; | |
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2140 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); |
0 | 2141 |
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2142 if (is_critical_native) { |
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2143 // Critical natives may have to call out so they need a save area |
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2144 // for register arguments. |
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2145 int double_slots = 0; |
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2146 int single_slots = 0; |
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2147 for ( int i = 0; i < total_in_args; i++) { |
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2148 if (in_regs[i].first()->is_Register()) { |
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2149 const Register reg = in_regs[i].first()->as_Register(); |
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2150 switch (in_sig_bt[i]) { |
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2151 case T_ARRAY: |
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2152 case T_BOOLEAN: |
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2153 case T_BYTE: |
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2154 case T_SHORT: |
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2155 case T_CHAR: |
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2156 case T_INT: assert(reg->is_in(), "don't need to save these"); break; |
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2157 case T_LONG: if (reg->is_global()) double_slots++; break; |
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2158 default: ShouldNotReachHere(); |
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2159 } |
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2160 } else if (in_regs[i].first()->is_FloatRegister()) { |
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2161 switch (in_sig_bt[i]) { |
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2162 case T_FLOAT: single_slots++; break; |
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2163 case T_DOUBLE: double_slots++; break; |
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2164 default: ShouldNotReachHere(); |
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2165 } |
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2166 } |
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2167 } |
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2168 total_save_slots = double_slots * 2 + single_slots; |
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2169 } |
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2170 |
0 | 2171 // Compute framesize for the wrapper. We need to handlize all oops in |
2172 // registers. We must create space for them here that is disjoint from | |
2173 // the windowed save area because we have no control over when we might | |
2174 // flush the window again and overwrite values that gc has since modified. | |
2175 // (The live window race) | |
2176 // | |
2177 // We always just allocate 6 word for storing down these object. This allow | |
2178 // us to simply record the base and use the Ireg number to decide which | |
2179 // slot to use. (Note that the reg number is the inbound number not the | |
2180 // outbound number). | |
2181 // We must shuffle args to match the native convention, and include var-args space. | |
2182 | |
2183 // Calculate the total number of stack slots we will need. | |
2184 | |
2185 // First count the abi requirement plus all of the outgoing args | |
2186 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; | |
2187 | |
2188 // Now the space for the inbound oop handle area | |
2189 | |
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2190 int oop_handle_offset = round_to(stack_slots, 2); |
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2191 stack_slots += total_save_slots; |
0 | 2192 |
2193 // Now any space we need for handlizing a klass if static method | |
2194 | |
2195 int klass_slot_offset = 0; | |
2196 int klass_offset = -1; | |
2197 int lock_slot_offset = 0; | |
2198 bool is_static = false; | |
2199 | |
2200 if (method->is_static()) { | |
2201 klass_slot_offset = stack_slots; | |
2202 stack_slots += VMRegImpl::slots_per_word; | |
2203 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; | |
2204 is_static = true; | |
2205 } | |
2206 | |
2207 // Plus a lock if needed | |
2208 | |
2209 if (method->is_synchronized()) { | |
2210 lock_slot_offset = stack_slots; | |
2211 stack_slots += VMRegImpl::slots_per_word; | |
2212 } | |
2213 | |
2214 // Now a place to save return value or as a temporary for any gpr -> fpr moves | |
2215 stack_slots += 2; | |
2216 | |
2217 // Ok The space we have allocated will look like: | |
2218 // | |
2219 // | |
2220 // FP-> | | | |
2221 // |---------------------| | |
2222 // | 2 slots for moves | | |
2223 // |---------------------| | |
2224 // | lock box (if sync) | | |
2225 // |---------------------| <- lock_slot_offset | |
2226 // | klass (if static) | | |
2227 // |---------------------| <- klass_slot_offset | |
2228 // | oopHandle area | | |
2229 // |---------------------| <- oop_handle_offset | |
2230 // | outbound memory | | |
2231 // | based arguments | | |
2232 // | | | |
2233 // |---------------------| | |
2234 // | vararg area | | |
2235 // |---------------------| | |
2236 // | | | |
2237 // SP-> | out_preserved_slots | | |
2238 // | |
2239 // | |
2240 | |
2241 | |
2242 // Now compute actual number of stack words we need rounding to make | |
2243 // stack properly aligned. | |
2244 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); | |
2245 | |
2246 int stack_size = stack_slots * VMRegImpl::stack_slot_size; | |
2247 | |
2248 // Generate stack overflow check before creating frame | |
2249 __ generate_stack_overflow_check(stack_size); | |
2250 | |
2251 // Generate a new frame for the wrapper. | |
2252 __ save(SP, -stack_size, SP); | |
2253 | |
2254 int frame_complete = ((intptr_t)__ pc()) - start; | |
2255 | |
2256 __ verify_thread(); | |
2257 | |
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2258 if (is_critical_native) { |
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2259 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, |
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2260 oop_handle_offset, oop_maps, in_regs, in_sig_bt); |
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2261 } |
0 | 2262 |
2263 // | |
2264 // We immediately shuffle the arguments so that any vm call we have to | |
2265 // make from here on out (sync slow path, jvmti, etc.) we will have | |
2266 // captured the oops from our caller and have a valid oopMap for | |
2267 // them. | |
2268 | |
2269 // ----------------- | |
2270 // The Grand Shuffle | |
2271 // | |
2272 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* | |
2273 // (derived from JavaThread* which is in L7_thread_cache) and, if static, | |
2274 // the class mirror instead of a receiver. This pretty much guarantees that | |
2275 // register layout will not match. We ignore these extra arguments during | |
2276 // the shuffle. The shuffle is described by the two calling convention | |
2277 // vectors we have in our possession. We simply walk the java vector to | |
2278 // get the source locations and the c vector to get the destinations. | |
2279 // Because we have a new window and the argument registers are completely | |
2280 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about | |
2281 // here. | |
2282 | |
2283 // This is a trick. We double the stack slots so we can claim | |
2284 // the oops in the caller's frame. Since we are sure to have | |
2285 // more args than the caller doubling is enough to make | |
2286 // sure we can capture all the incoming oop args from the | |
2287 // caller. | |
2288 // | |
2289 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); | |
2290 // Record sp-based slot for receiver on stack for non-static methods | |
2291 int receiver_offset = -1; | |
2292 | |
2293 // We move the arguments backward because the floating point registers | |
2294 // destination will always be to a register with a greater or equal register | |
2295 // number or the stack. | |
2296 | |
2297 #ifdef ASSERT | |
2298 bool reg_destroyed[RegisterImpl::number_of_registers]; | |
2299 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; | |
2300 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { | |
2301 reg_destroyed[r] = false; | |
2302 } | |
2303 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { | |
2304 freg_destroyed[f] = false; | |
2305 } | |
2306 | |
2307 #endif /* ASSERT */ | |
2308 | |
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2309 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { |
0 | 2310 |
2311 #ifdef ASSERT | |
2312 if (in_regs[i].first()->is_Register()) { | |
2313 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); | |
2314 } else if (in_regs[i].first()->is_FloatRegister()) { | |
2315 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); | |
2316 } | |
2317 if (out_regs[c_arg].first()->is_Register()) { | |
2318 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; | |
2319 } else if (out_regs[c_arg].first()->is_FloatRegister()) { | |
2320 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; | |
2321 } | |
2322 #endif /* ASSERT */ | |
2323 | |
2324 switch (in_sig_bt[i]) { | |
2325 case T_ARRAY: | |
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2326 if (is_critical_native) { |
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2327 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); |
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2328 c_arg--; |
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2329 break; |
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|
2330 } |
0 | 2331 case T_OBJECT: |
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2332 assert(!is_critical_native, "no oop arguments"); |
0 | 2333 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], |
2334 ((i == 0) && (!is_static)), | |
2335 &receiver_offset); | |
2336 break; | |
2337 case T_VOID: | |
2338 break; | |
2339 | |
2340 case T_FLOAT: | |
2341 float_move(masm, in_regs[i], out_regs[c_arg]); | |
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2342 break; |
0 | 2343 |
2344 case T_DOUBLE: | |
2345 assert( i + 1 < total_in_args && | |
2346 in_sig_bt[i + 1] == T_VOID && | |
2347 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); | |
2348 double_move(masm, in_regs[i], out_regs[c_arg]); | |
2349 break; | |
2350 | |
2351 case T_LONG : | |
2352 long_move(masm, in_regs[i], out_regs[c_arg]); | |
2353 break; | |
2354 | |
2355 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); | |
2356 | |
2357 default: | |
2358 move32_64(masm, in_regs[i], out_regs[c_arg]); | |
2359 } | |
2360 } | |
2361 | |
2362 // Pre-load a static method's oop into O1. Used both by locking code and | |
2363 // the normal JNI call code. | |
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2364 if (method->is_static() && !is_critical_native) { |
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2365 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1); |
0 | 2366 |
2367 // Now handlize the static class mirror in O1. It's known not-null. | |
2368 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); | |
2369 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); | |
2370 __ add(SP, klass_offset + STACK_BIAS, O1); | |
2371 } | |
2372 | |
2373 | |
2374 const Register L6_handle = L6; | |
2375 | |
2376 if (method->is_synchronized()) { | |
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2377 assert(!is_critical_native, "unhandled"); |
0 | 2378 __ mov(O1, L6_handle); |
2379 } | |
2380 | |
2381 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs | |
2382 // except O6/O7. So if we must call out we must push a new frame. We immediately | |
2383 // push a new frame and flush the windows. | |
2384 #ifdef _LP64 | |
2385 intptr_t thepc = (intptr_t) __ pc(); | |
2386 { | |
2387 address here = __ pc(); | |
2388 // Call the next instruction | |
2389 __ call(here + 8, relocInfo::none); | |
2390 __ delayed()->nop(); | |
2391 } | |
2392 #else | |
2393 intptr_t thepc = __ load_pc_address(O7, 0); | |
2394 #endif /* _LP64 */ | |
2395 | |
2396 // We use the same pc/oopMap repeatedly when we call out | |
2397 oop_maps->add_gc_map(thepc - start, map); | |
2398 | |
2399 // O7 now has the pc loaded that we will use when we finally call to native. | |
2400 | |
2401 // Save thread in L7; it crosses a bunch of VM calls below | |
2402 // Don't use save_thread because it smashes G2 and we merely | |
2403 // want to save a copy | |
2404 __ mov(G2_thread, L7_thread_cache); | |
2405 | |
2406 | |
2407 // If we create an inner frame once is plenty | |
2408 // when we create it we must also save G2_thread | |
2409 bool inner_frame_created = false; | |
2410 | |
2411 // dtrace method entry support | |
2412 { | |
2413 SkipIfEqual skip_if( | |
2414 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
2415 // create inner frame | |
2416 __ save_frame(0); | |
2417 __ mov(G2_thread, L7_thread_cache); | |
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2418 __ set_metadata_constant(method(), O1); |
0 | 2419 __ call_VM_leaf(L7_thread_cache, |
2420 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), | |
2421 G2_thread, O1); | |
2422 __ restore(); | |
2423 } | |
2424 | |
610
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2425 // RedefineClasses() tracing support for obsolete method entry |
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2426 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { |
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2427 // create inner frame |
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2428 __ save_frame(0); |
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2429 __ mov(G2_thread, L7_thread_cache); |
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2430 __ set_metadata_constant(method(), O1); |
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2431 __ call_VM_leaf(L7_thread_cache, |
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2432 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), |
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2433 G2_thread, O1); |
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2434 __ restore(); |
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2435 } |
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2436 |
0 | 2437 // We are in the jni frame unless saved_frame is true in which case |
2438 // we are in one frame deeper (the "inner" frame). If we are in the | |
2439 // "inner" frames the args are in the Iregs and if the jni frame then | |
2440 // they are in the Oregs. | |
2441 // If we ever need to go to the VM (for locking, jvmti) then | |
2442 // we will always be in the "inner" frame. | |
2443 | |
2444 // Lock a synchronized method | |
2445 int lock_offset = -1; // Set if locked | |
2446 if (method->is_synchronized()) { | |
2447 Register Roop = O1; | |
2448 const Register L3_box = L3; | |
2449 | |
2450 create_inner_frame(masm, &inner_frame_created); | |
2451 | |
2452 __ ld_ptr(I1, 0, O1); | |
2453 Label done; | |
2454 | |
2455 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); | |
2456 __ add(FP, lock_offset+STACK_BIAS, L3_box); | |
2457 #ifdef ASSERT | |
2458 if (UseBiasedLocking) { | |
2459 // making the box point to itself will make it clear it went unused | |
2460 // but also be obviously invalid | |
2461 __ st_ptr(L3_box, L3_box, 0); | |
2462 } | |
2463 #endif // ASSERT | |
2464 // | |
2465 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch | |
2466 // | |
2467 __ compiler_lock_object(Roop, L1, L3_box, L2); | |
2468 __ br(Assembler::equal, false, Assembler::pt, done); | |
2469 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); | |
2470 | |
2471 | |
2472 // None of the above fast optimizations worked so we have to get into the | |
2473 // slow case of monitor enter. Inline a special case of call_VM that | |
2474 // disallows any pending_exception. | |
2475 __ mov(Roop, O0); // Need oop in O0 | |
2476 __ mov(L3_box, O1); | |
2477 | |
2478 // Record last_Java_sp, in case the VM code releases the JVM lock. | |
2479 | |
2480 __ set_last_Java_frame(FP, I7); | |
2481 | |
2482 // do the call | |
2483 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); | |
2484 __ delayed()->mov(L7_thread_cache, O2); | |
2485 | |
2486 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2487 __ reset_last_Java_frame(); | |
2488 | |
2489 #ifdef ASSERT | |
2490 { Label L; | |
2491 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
3839 | 2492 __ br_null_short(O0, Assembler::pt, L); |
0 | 2493 __ stop("no pending exception allowed on exit from IR::monitorenter"); |
2494 __ bind(L); | |
2495 } | |
2496 #endif | |
2497 __ bind(done); | |
2498 } | |
2499 | |
2500 | |
2501 // Finally just about ready to make the JNI call | |
2502 | |
10997 | 2503 __ flushw(); |
0 | 2504 if (inner_frame_created) { |
2505 __ restore(); | |
2506 } else { | |
2507 // Store only what we need from this frame | |
2508 // QQQ I think that non-v9 (like we care) we don't need these saves | |
2509 // either as the flush traps and the current window goes too. | |
2510 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
2511 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
2512 } | |
2513 | |
2514 // get JNIEnv* which is first argument to native | |
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2515 if (!is_critical_native) { |
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2516 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); |
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2517 } |
0 | 2518 |
2519 // Use that pc we placed in O7 a while back as the current frame anchor | |
2520 __ set_last_Java_frame(SP, O7); | |
2521 | |
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2522 // We flushed the windows ages ago now mark them as flushed before transitioning. |
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2523 __ set(JavaFrameAnchor::flushed, G3_scratch); |
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2524 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
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2525 |
0 | 2526 // Transition from _thread_in_Java to _thread_in_native. |
2527 __ set(_thread_in_native, G3_scratch); | |
2528 | |
2529 #ifdef _LP64 | |
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2530 AddressLiteral dest(native_func); |
0 | 2531 __ relocate(relocInfo::runtime_call_type); |
727 | 2532 __ jumpl_to(dest, O7, O7); |
0 | 2533 #else |
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2534 __ call(native_func, relocInfo::runtime_call_type); |
0 | 2535 #endif |
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2536 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
0 | 2537 |
2538 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2539 | |
2540 // Unpack native results. For int-types, we do any needed sign-extension | |
2541 // and move things into I0. The return value there will survive any VM | |
2542 // calls for blocking or unlocking. An FP or OOP result (handle) is done | |
2543 // specially in the slow-path code. | |
2544 switch (ret_type) { | |
2545 case T_VOID: break; // Nothing to do! | |
2546 case T_FLOAT: break; // Got it where we want it (unless slow-path) | |
2547 case T_DOUBLE: break; // Got it where we want it (unless slow-path) | |
2548 // In 64 bits build result is in O0, in O0, O1 in 32bit build | |
2549 case T_LONG: | |
2550 #ifndef _LP64 | |
2551 __ mov(O1, I1); | |
2552 #endif | |
2553 // Fall thru | |
2554 case T_OBJECT: // Really a handle | |
2555 case T_ARRAY: | |
2556 case T_INT: | |
2557 __ mov(O0, I0); | |
2558 break; | |
2559 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false | |
2560 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; | |
2561 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! | |
2562 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; | |
2563 break; // Cannot de-handlize until after reclaiming jvm_lock | |
2564 default: | |
2565 ShouldNotReachHere(); | |
2566 } | |
2567 | |
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2568 Label after_transition; |
0 | 2569 // must we block? |
2570 | |
2571 // Block, if necessary, before resuming in _thread_in_Java state. | |
2572 // In order for GC to work, don't clear the last_Java_sp until after blocking. | |
2573 { Label no_block; | |
727 | 2574 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); |
0 | 2575 |
2576 // Switch thread to "native transition" state before reading the synchronization state. | |
2577 // This additional state is necessary because reading and testing the synchronization | |
2578 // state is not atomic w.r.t. GC, as this scenario demonstrates: | |
2579 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. | |
2580 // VM thread changes sync state to synchronizing and suspends threads for GC. | |
2581 // Thread A is resumed to finish this native method, but doesn't block here since it | |
2582 // didn't see any synchronization is progress, and escapes. | |
2583 __ set(_thread_in_native_trans, G3_scratch); | |
727 | 2584 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
0 | 2585 if(os::is_MP()) { |
2586 if (UseMembar) { | |
2587 // Force this write out before the read below | |
2588 __ membar(Assembler::StoreLoad); | |
2589 } else { | |
2590 // Write serialization page so VM thread can do a pseudo remote membar. | |
2591 // We use the current thread pointer to calculate a thread specific | |
2592 // offset to write to within the page. This minimizes bus traffic | |
2593 // due to cache line collision. | |
2594 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); | |
2595 } | |
2596 } | |
2597 __ load_contents(sync_state, G3_scratch); | |
2598 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); | |
2599 | |
2600 Label L; | |
727 | 2601 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); |
0 | 2602 __ br(Assembler::notEqual, false, Assembler::pn, L); |
727 | 2603 __ delayed()->ld(suspend_state, G3_scratch); |
3839 | 2604 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); |
0 | 2605 __ bind(L); |
2606 | |
2607 // Block. Save any potential method result value before the operation and | |
2608 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this | |
2609 // lets us share the oopMap we used when we went native rather the create | |
2610 // a distinct one for this pc | |
2611 // | |
2612 save_native_result(masm, ret_type, stack_slots); | |
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2613 if (!is_critical_native) { |
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2614 __ call_VM_leaf(L7_thread_cache, |
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2615 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), |
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2616 G2_thread); |
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2617 } else { |
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2618 __ call_VM_leaf(L7_thread_cache, |
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2619 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), |
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2620 G2_thread); |
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2621 } |
0 | 2622 |
2623 // Restore any method result value | |
2624 restore_native_result(masm, ret_type, stack_slots); | |
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2625 |
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2626 if (is_critical_native) { |
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2627 // The call above performed the transition to thread_in_Java so |
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2628 // skip the transition logic below. |
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2629 __ ba(after_transition); |
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2630 __ delayed()->nop(); |
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2631 } |
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2632 |
0 | 2633 __ bind(no_block); |
2634 } | |
2635 | |
2636 // thread state is thread_in_native_trans. Any safepoint blocking has already | |
2637 // happened so we can now change state to _thread_in_Java. | |
2638 __ set(_thread_in_Java, G3_scratch); | |
727 | 2639 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
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2640 __ bind(after_transition); |
0 | 2641 |
2642 Label no_reguard; | |
727 | 2643 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); |
3839 | 2644 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); |
0 | 2645 |
2646 save_native_result(masm, ret_type, stack_slots); | |
2647 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); | |
2648 __ delayed()->nop(); | |
2649 | |
2650 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2651 restore_native_result(masm, ret_type, stack_slots); | |
2652 | |
2653 __ bind(no_reguard); | |
2654 | |
2655 // Handle possible exception (will unlock if necessary) | |
2656 | |
2657 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) | |
2658 | |
2659 // Unlock | |
2660 if (method->is_synchronized()) { | |
2661 Label done; | |
2662 Register I2_ex_oop = I2; | |
2663 const Register L3_box = L3; | |
2664 // Get locked oop from the handle we passed to jni | |
2665 __ ld_ptr(L6_handle, 0, L4); | |
2666 __ add(SP, lock_offset+STACK_BIAS, L3_box); | |
2667 // Must save pending exception around the slow-path VM call. Since it's a | |
2668 // leaf call, the pending exception (if any) can be kept in a register. | |
2669 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); | |
2670 // Now unlock | |
2671 // (Roop, Rmark, Rbox, Rscratch) | |
2672 __ compiler_unlock_object(L4, L1, L3_box, L2); | |
2673 __ br(Assembler::equal, false, Assembler::pt, done); | |
2674 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); | |
2675 | |
2676 // save and restore any potential method result value around the unlocking | |
2677 // operation. Will save in I0 (or stack for FP returns). | |
2678 save_native_result(masm, ret_type, stack_slots); | |
2679 | |
2680 // Must clear pending-exception before re-entering the VM. Since this is | |
2681 // a leaf call, pending-exception-oop can be safely kept in a register. | |
2682 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
2683 | |
2684 // slow case of monitor enter. Inline a special case of call_VM that | |
2685 // disallows any pending_exception. | |
2686 __ mov(L3_box, O1); | |
2687 | |
2688 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); | |
2689 __ delayed()->mov(L4, O0); // Need oop in O0 | |
2690 | |
2691 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2692 | |
2693 #ifdef ASSERT | |
2694 { Label L; | |
2695 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
3839 | 2696 __ br_null_short(O0, Assembler::pt, L); |
0 | 2697 __ stop("no pending exception allowed on exit from IR::monitorexit"); |
2698 __ bind(L); | |
2699 } | |
2700 #endif | |
2701 restore_native_result(masm, ret_type, stack_slots); | |
2702 // check_forward_pending_exception jump to forward_exception if any pending | |
2703 // exception is set. The forward_exception routine expects to see the | |
2704 // exception in pending_exception and not in a register. Kind of clumsy, | |
2705 // since all folks who branch to forward_exception must have tested | |
2706 // pending_exception first and hence have it in a register already. | |
2707 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
2708 __ bind(done); | |
2709 } | |
2710 | |
2711 // Tell dtrace about this method exit | |
2712 { | |
2713 SkipIfEqual skip_if( | |
2714 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
2715 save_native_result(masm, ret_type, stack_slots); | |
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2716 __ set_metadata_constant(method(), O1); |
0 | 2717 __ call_VM_leaf(L7_thread_cache, |
2718 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), | |
2719 G2_thread, O1); | |
2720 restore_native_result(masm, ret_type, stack_slots); | |
2721 } | |
2722 | |
2723 // Clear "last Java frame" SP and PC. | |
2724 __ verify_thread(); // G2_thread must be correct | |
2725 __ reset_last_Java_frame(); | |
2726 | |
2727 // Unpack oop result | |
2728 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { | |
2729 Label L; | |
2730 __ addcc(G0, I0, G0); | |
2731 __ brx(Assembler::notZero, true, Assembler::pt, L); | |
2732 __ delayed()->ld_ptr(I0, 0, I0); | |
2733 __ mov(G0, I0); | |
2734 __ bind(L); | |
2735 __ verify_oop(I0); | |
2736 } | |
2737 | |
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2738 if (!is_critical_native) { |
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2739 // reset handle block |
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2740 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); |
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2741 __ st(G0, L5, JNIHandleBlock::top_offset_in_bytes()); |
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2742 |
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2743 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); |
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2744 check_forward_pending_exception(masm, G3_scratch); |
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2745 } |
0 | 2746 |
2747 | |
2748 // Return | |
2749 | |
2750 #ifndef _LP64 | |
2751 if (ret_type == T_LONG) { | |
2752 | |
2753 // Must leave proper result in O0,O1 and G1 (c2/tiered only) | |
2754 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
2755 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
2756 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
2757 } | |
2758 #endif | |
2759 | |
2760 __ ret(); | |
2761 __ delayed()->restore(); | |
2762 | |
2763 __ flush(); | |
2764 | |
2765 nmethod *nm = nmethod::new_native_nmethod(method, | |
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2766 compile_id, |
0 | 2767 masm->code(), |
2768 vep_offset, | |
2769 frame_complete, | |
2770 stack_slots / VMRegImpl::slots_per_word, | |
2771 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), | |
2772 in_ByteSize(lock_offset), | |
2773 oop_maps); | |
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2774 |
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2775 if (is_critical_native) { |
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2776 nm->set_lazy_critical_native(true); |
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2777 } |
0 | 2778 return nm; |
2779 | |
2780 } | |
2781 | |
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2782 #ifdef HAVE_DTRACE_H |
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2783 // --------------------------------------------------------------------------- |
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2784 // Generate a dtrace nmethod for a given signature. The method takes arguments |
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2785 // in the Java compiled code convention, marshals them to the native |
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2786 // abi and then leaves nops at the position you would expect to call a native |
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2787 // function. When the probe is enabled the nops are replaced with a trap |
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2788 // instruction that dtrace inserts and the trace will cause a notification |
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2789 // to dtrace. |
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2790 // |
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2791 // The probes are only able to take primitive types and java/lang/String as |
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2792 // arguments. No other java types are allowed. Strings are converted to utf8 |
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2793 // strings so that from dtrace point of view java strings are converted to C |
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2794 // strings. There is an arbitrary fixed limit on the total space that a method |
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2795 // can use for converting the strings. (256 chars per string in the signature). |
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2796 // So any java string larger then this is truncated. |
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2797 |
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2798 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; |
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2799 static bool offsets_initialized = false; |
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2800 |
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2801 nmethod *SharedRuntime::generate_dtrace_nmethod( |
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2802 MacroAssembler *masm, methodHandle method) { |
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2803 |
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2804 |
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2805 // generate_dtrace_nmethod is guarded by a mutex so we are sure to |
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2806 // be single threaded in this method. |
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2807 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); |
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2808 |
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2809 // Fill in the signature array, for the calling-convention call. |
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2810 int total_args_passed = method->size_of_parameters(); |
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2811 |
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2812 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); |
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2813 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); |
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2814 |
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2815 // The signature we are going to use for the trap that dtrace will see |
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2816 // java/lang/String is converted. We drop "this" and any other object |
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2817 // is converted to NULL. (A one-slot java/lang/Long object reference |
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2818 // is converted to a two-slot long, which is why we double the allocation). |
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2819 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); |
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2820 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); |
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2821 |
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2822 int i=0; |
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2823 int total_strings = 0; |
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2824 int first_arg_to_pass = 0; |
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2825 int total_c_args = 0; |
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2826 |
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2827 // Skip the receiver as dtrace doesn't want to see it |
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2828 if( !method->is_static() ) { |
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2829 in_sig_bt[i++] = T_OBJECT; |
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2830 first_arg_to_pass = 1; |
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2831 } |
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2832 |
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2833 SignatureStream ss(method->signature()); |
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2834 for ( ; !ss.at_return_type(); ss.next()) { |
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2835 BasicType bt = ss.type(); |
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2836 in_sig_bt[i++] = bt; // Collect remaining bits of signature |
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2837 out_sig_bt[total_c_args++] = bt; |
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2838 if( bt == T_OBJECT) { |
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2839 Symbol* s = ss.as_symbol_or_null(); |
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2840 if (s == vmSymbols::java_lang_String()) { |
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2841 total_strings++; |
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2842 out_sig_bt[total_c_args-1] = T_ADDRESS; |
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2843 } else if (s == vmSymbols::java_lang_Boolean() || |
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2844 s == vmSymbols::java_lang_Byte()) { |
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2845 out_sig_bt[total_c_args-1] = T_BYTE; |
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2846 } else if (s == vmSymbols::java_lang_Character() || |
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2847 s == vmSymbols::java_lang_Short()) { |
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2848 out_sig_bt[total_c_args-1] = T_SHORT; |
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2849 } else if (s == vmSymbols::java_lang_Integer() || |
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2850 s == vmSymbols::java_lang_Float()) { |
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2851 out_sig_bt[total_c_args-1] = T_INT; |
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2852 } else if (s == vmSymbols::java_lang_Long() || |
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2853 s == vmSymbols::java_lang_Double()) { |
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2854 out_sig_bt[total_c_args-1] = T_LONG; |
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2855 out_sig_bt[total_c_args++] = T_VOID; |
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2856 } |
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2857 } else if ( bt == T_LONG || bt == T_DOUBLE ) { |
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2858 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots |
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2859 // We convert double to long |
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2860 out_sig_bt[total_c_args-1] = T_LONG; |
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2861 out_sig_bt[total_c_args++] = T_VOID; |
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2862 } else if ( bt == T_FLOAT) { |
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2863 // We convert float to int |
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2864 out_sig_bt[total_c_args-1] = T_INT; |
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2865 } |
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2866 } |
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2867 |
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2868 assert(i==total_args_passed, "validly parsed signature"); |
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2869 |
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2870 // Now get the compiled-Java layout as input arguments |
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2871 int comp_args_on_stack; |
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2872 comp_args_on_stack = SharedRuntime::java_calling_convention( |
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2873 in_sig_bt, in_regs, total_args_passed, false); |
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2874 |
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2875 // We have received a description of where all the java arg are located |
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2876 // on entry to the wrapper. We need to convert these args to where |
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2877 // the a native (non-jni) function would expect them. To figure out |
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2878 // where they go we convert the java signature to a C signature and remove |
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2879 // T_VOID for any long/double we might have received. |
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2880 |
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2881 |
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2882 // Now figure out where the args must be stored and how much stack space |
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2883 // they require (neglecting out_preserve_stack_slots but space for storing |
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2884 // the 1st six register arguments). It's weird see int_stk_helper. |
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2885 // |
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2886 int out_arg_slots; |
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2887 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); |
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2888 |
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2889 // Calculate the total number of stack slots we will need. |
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2890 |
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2891 // First count the abi requirement plus all of the outgoing args |
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2892 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; |
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2893 |
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2894 // Plus a temp for possible converion of float/double/long register args |
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2895 |
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2896 int conversion_temp = stack_slots; |
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2897 stack_slots += 2; |
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2898 |
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2899 |
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2900 // Now space for the string(s) we must convert |
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2901 |
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2902 int string_locs = stack_slots; |
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2903 stack_slots += total_strings * |
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2904 (max_dtrace_string_size / VMRegImpl::stack_slot_size); |
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2905 |
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2906 // Ok The space we have allocated will look like: |
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2907 // |
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2908 // |
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2909 // FP-> | | |
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2910 // |---------------------| |
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2911 // | string[n] | |
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2912 // |---------------------| <- string_locs[n] |
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2913 // | string[n-1] | |
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2914 // |---------------------| <- string_locs[n-1] |
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2915 // | ... | |
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2916 // | ... | |
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2917 // |---------------------| <- string_locs[1] |
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2918 // | string[0] | |
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2919 // |---------------------| <- string_locs[0] |
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2920 // | temp | |
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2921 // |---------------------| <- conversion_temp |
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2922 // | outbound memory | |
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2923 // | based arguments | |
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2924 // | | |
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2925 // |---------------------| |
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2926 // | | |
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2927 // SP-> | out_preserved_slots | |
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2928 // |
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2929 // |
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2930 |
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2931 // Now compute actual number of stack words we need rounding to make |
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2932 // stack properly aligned. |
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2933 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); |
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2934 |
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2935 int stack_size = stack_slots * VMRegImpl::stack_slot_size; |
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2936 |
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2937 intptr_t start = (intptr_t)__ pc(); |
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2938 |
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2939 // First thing make an ic check to see if we should even be here |
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2940 |
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2941 { |
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2942 Label L; |
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2943 const Register temp_reg = G3_scratch; |
727 | 2944 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
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2945 __ verify_oop(O0); |
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2946 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); |
3839 | 2947 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
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2948 |
727 | 2949 __ jump_to(ic_miss, temp_reg); |
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2950 __ delayed()->nop(); |
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2951 __ align(CodeEntryAlignment); |
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2952 __ bind(L); |
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2953 } |
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2954 |
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2955 int vep_offset = ((intptr_t)__ pc()) - start; |
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2956 |
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2957 |
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2958 // The instruction at the verified entry point must be 5 bytes or longer |
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2959 // because it can be patched on the fly by make_non_entrant. The stack bang |
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2960 // instruction fits that requirement. |
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2961 |
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2962 // Generate stack overflow check before creating frame |
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2963 __ generate_stack_overflow_check(stack_size); |
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2964 |
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2965 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, |
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2966 "valid size for make_non_entrant"); |
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2967 |
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2968 // Generate a new frame for the wrapper. |
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2969 __ save(SP, -stack_size, SP); |
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2970 |
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2971 // Frame is now completed as far a size and linkage. |
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2972 |
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2973 int frame_complete = ((intptr_t)__ pc()) - start; |
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2974 |
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2975 #ifdef ASSERT |
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2976 bool reg_destroyed[RegisterImpl::number_of_registers]; |
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2977 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; |
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2978 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { |
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2979 reg_destroyed[r] = false; |
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2980 } |
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2981 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { |
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2982 freg_destroyed[f] = false; |
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2983 } |
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2984 |
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2985 #endif /* ASSERT */ |
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2986 |
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2987 VMRegPair zero; |
176
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2988 const Register g0 = G0; // without this we get a compiler warning (why??) |
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2989 zero.set2(g0->as_VMReg()); |
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2990 |
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2991 int c_arg, j_arg; |
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2992 |
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2993 Register conversion_off = noreg; |
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2994 |
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2995 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
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2996 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
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2997 |
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2998 VMRegPair src = in_regs[j_arg]; |
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2999 VMRegPair dst = out_regs[c_arg]; |
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3000 |
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3001 #ifdef ASSERT |
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3002 if (src.first()->is_Register()) { |
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3003 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); |
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3004 } else if (src.first()->is_FloatRegister()) { |
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3005 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( |
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3006 FloatRegisterImpl::S)], "ack!"); |
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3007 } |
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3008 if (dst.first()->is_Register()) { |
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3009 reg_destroyed[dst.first()->as_Register()->encoding()] = true; |
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3010 } else if (dst.first()->is_FloatRegister()) { |
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3011 freg_destroyed[dst.first()->as_FloatRegister()->encoding( |
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3012 FloatRegisterImpl::S)] = true; |
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3013 } |
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3014 #endif /* ASSERT */ |
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3015 |
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3016 switch (in_sig_bt[j_arg]) { |
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3017 case T_ARRAY: |
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3018 case T_OBJECT: |
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3019 { |
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3020 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || |
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3021 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
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3022 // need to unbox a one-slot value |
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|
3023 Register in_reg = L0; |
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3024 Register tmp = L2; |
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|
3025 if ( src.first()->is_reg() ) { |
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diff
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|
3026 in_reg = src.first()->as_Register(); |
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kamg
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113
diff
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|
3027 } else { |
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kamg
parents:
113
diff
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|
3028 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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diff
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|
3029 "must be"); |
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diff
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|
3030 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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diff
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|
3031 } |
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diff
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|
3032 // If the final destination is an acceptable register |
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diff
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|
3033 if ( dst.first()->is_reg() ) { |
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|
3034 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { |
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|
3035 tmp = dst.first()->as_Register(); |
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kamg
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diff
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|
3036 } |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3037 } |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3038 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3039 Label skipUnbox; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3040 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { |
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|
3041 __ mov(G0, tmp->successor()); |
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kamg
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113
diff
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|
3042 } |
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diff
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|
3043 __ br_null(in_reg, true, Assembler::pn, skipUnbox); |
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|
3044 __ delayed()->mov(G0, tmp); |
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|
3045 |
165
437d03ea40b1
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kvn
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|
3046 BasicType bt = out_sig_bt[c_arg]; |
437d03ea40b1
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kvn
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|
3047 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
437d03ea40b1
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|
3048 switch (bt) { |
116
018d5b58dd4f
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|
3049 case T_BYTE: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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diff
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|
3050 __ ldub(in_reg, box_offset, tmp); break; |
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kamg
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diff
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|
3051 case T_SHORT: |
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|
3052 __ lduh(in_reg, box_offset, tmp); break; |
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kamg
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diff
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|
3053 case T_INT: |
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diff
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|
3054 __ ld(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3055 case T_LONG: |
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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diff
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|
3056 __ ld_long(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3057 default: ShouldNotReachHere(); |
018d5b58dd4f
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kamg
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113
diff
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|
3058 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3059 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3060 __ bind(skipUnbox); |
018d5b58dd4f
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kamg
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113
diff
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|
3061 // If tmp wasn't final destination copy to final destination |
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kamg
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113
diff
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|
3062 if (tmp == L2) { |
018d5b58dd4f
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113
diff
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|
3063 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3064 if (out_sig_bt[c_arg] == T_LONG) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3065 long_move(masm, tmp_as_VM, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3066 } else { |
018d5b58dd4f
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113
diff
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|
3067 move32_64(masm, tmp_as_VM, out_regs[c_arg]); |
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kamg
parents:
113
diff
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|
3068 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3069 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3070 if (out_sig_bt[c_arg] == T_LONG) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3071 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3072 ++c_arg; // move over the T_VOID to keep the loop indices in sync |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3073 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3074 } else if (out_sig_bt[c_arg] == T_ADDRESS) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3075 Register s = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3076 src.first()->is_reg() ? src.first()->as_Register() : L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3077 Register d = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3078 dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3079 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3080 // We store the oop now so that the conversion pass can reach |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3081 // while in the inner frame. This will be the only store if |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3082 // the oop is NULL. |
018d5b58dd4f
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kamg
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113
diff
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|
3083 if (s != L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3084 // src is register |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3085 if (d != L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3086 // dst is register |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3087 __ mov(s, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3088 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3089 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3090 STACK_BIAS), "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3091 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3092 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3093 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3094 // src not a register |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3095 assert(Assembler::is_simm13(reg2offset(src.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3096 STACK_BIAS), "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3097 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3098 if (d == L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3099 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3100 STACK_BIAS), "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3101 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3102 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3103 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3104 } else if (out_sig_bt[c_arg] != T_VOID) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3105 // Convert the arg to NULL |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3106 if (dst.first()->is_reg()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3107 __ mov(G0, dst.first()->as_Register()); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3108 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3109 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3110 STACK_BIAS), "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3111 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3112 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3113 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3114 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3115 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3116 case T_VOID: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3117 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3118 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3119 case T_FLOAT: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3120 if (src.first()->is_stack()) { |
018d5b58dd4f
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kamg
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113
diff
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|
3121 // Stack to stack/reg is simple |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3122 move32_64(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3123 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3124 if (dst.first()->is_reg()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3125 // freg -> reg |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3126 int off = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3127 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
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kamg
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113
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|
3128 Register d = dst.first()->as_Register(); |
018d5b58dd4f
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kamg
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113
diff
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|
3129 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
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kamg
parents:
113
diff
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|
3130 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3131 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3132 __ ld(SP, off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3133 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3134 if (conversion_off == noreg) { |
018d5b58dd4f
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kamg
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113
diff
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|
3135 __ set(off, L6); |
018d5b58dd4f
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kamg
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113
diff
changeset
|
3136 conversion_off = L6; |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3137 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3138 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3139 SP, conversion_off); |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3140 __ ld(SP, conversion_off , d); |
018d5b58dd4f
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kamg
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113
diff
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|
3141 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3142 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3143 // freg -> mem |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3144 int off = STACK_BIAS + reg2offset(dst.first()); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3145 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3146 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3147 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3148 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3149 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3150 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3151 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3152 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3153 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3154 SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3155 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3156 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3157 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3158 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3159 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3160 case T_DOUBLE: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3161 assert( j_arg + 1 < total_args_passed && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3162 in_sig_bt[j_arg + 1] == T_VOID && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3163 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3164 if (src.first()->is_stack()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3165 // Stack to stack/reg is simple |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3166 long_move(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3167 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3168 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3169 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3170 // Destination could be an odd reg on 32bit in which case |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3171 // we can't load direct to the destination. |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3172 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3173 if (!d->is_even() && wordSize == 4) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3174 d = L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3175 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3176 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3177 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3178 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3179 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3180 __ ld_long(SP, off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3181 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3182 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3183 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3184 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3185 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3186 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3187 SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3188 __ ld_long(SP, conversion_off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3189 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3190 if (d == L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3191 long_move(masm, reg64_to_VMRegPair(L2), dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3192 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3193 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3194 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3195 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3196 case T_LONG : |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3197 // 32bit can't do a split move of something like g1 -> O0, O1 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3198 // so use a memory temp |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3199 if (src.is_single_phys_reg() && wordSize == 4) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3200 Register tmp = L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3201 if (dst.first()->is_reg() && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3202 (wordSize == 8 || dst.first()->as_Register()->is_even())) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3203 tmp = dst.first()->as_Register(); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3204 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3205 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3206 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3207 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3208 __ stx(src.first()->as_Register(), SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3209 __ ld_long(SP, off, tmp); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3210 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3211 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3212 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3213 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3214 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3215 __ stx(src.first()->as_Register(), SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3216 __ ld_long(SP, conversion_off, tmp); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3217 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3218 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3219 if (tmp == L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3220 long_move(masm, reg64_to_VMRegPair(L2), dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3221 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3222 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3223 long_move(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3224 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3225 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3226 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3227 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3228 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3229 default: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3230 move32_64(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3231 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3232 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3233 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3234 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3235 // If we have any strings we must store any register based arg to the stack |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3236 // This includes any still live xmm registers too. |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3237 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3238 if (total_strings > 0 ) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3239 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3240 // protect all the arg registers |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3241 __ save_frame(0); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3242 __ mov(G2_thread, L7_thread_cache); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3243 const Register L2_string_off = L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3244 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3245 // Get first string offset |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3246 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3247 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3248 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3249 if (out_sig_bt[c_arg] == T_ADDRESS) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3250 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3251 VMRegPair dst = out_regs[c_arg]; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3252 const Register d = dst.first()->is_reg() ? |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3253 dst.first()->as_Register()->after_save() : noreg; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3254 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3255 // It's a string the oop and it was already copied to the out arg |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3256 // position |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3257 if (d != noreg) { |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3258 __ mov(d, O0); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3259 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3260 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3261 "must be"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3262 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); |
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3263 } |
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3264 Label skip; |
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3265 |
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3266 __ br_null(O0, false, Assembler::pn, skip); |
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3267 __ delayed()->add(FP, L2_string_off, O1); |
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3268 |
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3269 if (d != noreg) { |
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3270 __ mov(O1, d); |
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3271 } else { |
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3272 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
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3273 "must be"); |
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3274 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); |
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3275 } |
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3276 |
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3277 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), |
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3278 relocInfo::runtime_call_type); |
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3279 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); |
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3280 |
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3281 __ bind(skip); |
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3282 |
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3283 } |
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3284 |
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3285 } |
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3286 __ mov(L7_thread_cache, G2_thread); |
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3287 __ restore(); |
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3288 |
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3289 } |
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3290 |
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3291 |
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3292 // Ok now we are done. Need to place the nop that dtrace wants in order to |
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3293 // patch in the trap |
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3294 |
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3295 int patch_offset = ((intptr_t)__ pc()) - start; |
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3296 |
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3297 __ nop(); |
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3298 |
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3299 |
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3300 // Return |
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3301 |
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3302 __ ret(); |
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3303 __ delayed()->restore(); |
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3304 |
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3305 __ flush(); |
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3306 |
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3307 nmethod *nm = nmethod::new_dtrace_nmethod( |
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3308 method, masm->code(), vep_offset, patch_offset, frame_complete, |
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3309 stack_slots / VMRegImpl::slots_per_word); |
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3310 return nm; |
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3311 |
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3312 } |
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3313 |
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3314 #endif // HAVE_DTRACE_H |
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3315 |
0 | 3316 // this function returns the adjust size (in number of words) to a c2i adapter |
3317 // activation for use during deoptimization | |
3318 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { | |
3319 assert(callee_locals >= callee_parameters, | |
3320 "test and remove; got more parms than locals"); | |
3321 if (callee_locals < callee_parameters) | |
3322 return 0; // No adjustment for negative locals | |
1506 | 3323 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; |
0 | 3324 return round_to(diff, WordsPerLong); |
3325 } | |
3326 | |
3327 // "Top of Stack" slots that may be unused by the calling convention but must | |
3328 // otherwise be preserved. | |
3329 // On Intel these are not necessary and the value can be zero. | |
3330 // On Sparc this describes the words reserved for storing a register window | |
3331 // when an interrupt occurs. | |
3332 uint SharedRuntime::out_preserve_stack_slots() { | |
3333 return frame::register_save_words * VMRegImpl::slots_per_word; | |
3334 } | |
3335 | |
3336 static void gen_new_frame(MacroAssembler* masm, bool deopt) { | |
3337 // | |
3338 // Common out the new frame generation for deopt and uncommon trap | |
3339 // | |
3340 Register G3pcs = G3_scratch; // Array of new pcs (input) | |
3341 Register Oreturn0 = O0; | |
3342 Register Oreturn1 = O1; | |
3343 Register O2UnrollBlock = O2; | |
3344 Register O3array = O3; // Array of frame sizes (input) | |
3345 Register O4array_size = O4; // number of frames (input) | |
3346 Register O7frame_size = O7; // number of frames (input) | |
3347 | |
3348 __ ld_ptr(O3array, 0, O7frame_size); | |
3349 __ sub(G0, O7frame_size, O7frame_size); | |
3350 __ save(SP, O7frame_size, SP); | |
3351 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc | |
3352 | |
3353 #ifdef ASSERT | |
3354 // make sure that the frames are aligned properly | |
3355 #ifndef _LP64 | |
3356 __ btst(wordSize*2-1, SP); | |
5923 | 3357 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc); |
0 | 3358 #endif |
3359 #endif | |
3360 | |
3361 // Deopt needs to pass some extra live values from frame to frame | |
3362 | |
3363 if (deopt) { | |
3364 __ mov(Oreturn0->after_save(), Oreturn0); | |
3365 __ mov(Oreturn1->after_save(), Oreturn1); | |
3366 } | |
3367 | |
3368 __ mov(O4array_size->after_save(), O4array_size); | |
3369 __ sub(O4array_size, 1, O4array_size); | |
3370 __ mov(O3array->after_save(), O3array); | |
3371 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); | |
3372 __ add(G3pcs, wordSize, G3pcs); // point to next pc value | |
3373 | |
3374 #ifdef ASSERT | |
3375 // trash registers to show a clear pattern in backtraces | |
3376 __ set(0xDEAD0000, I0); | |
3377 __ add(I0, 2, I1); | |
3378 __ add(I0, 4, I2); | |
3379 __ add(I0, 6, I3); | |
3380 __ add(I0, 8, I4); | |
3381 // Don't touch I5 could have valuable savedSP | |
3382 __ set(0xDEADBEEF, L0); | |
3383 __ mov(L0, L1); | |
3384 __ mov(L0, L2); | |
3385 __ mov(L0, L3); | |
3386 __ mov(L0, L4); | |
3387 __ mov(L0, L5); | |
3388 | |
3389 // trash the return value as there is nothing to return yet | |
3390 __ set(0xDEAD0001, O7); | |
3391 #endif | |
3392 | |
3393 __ mov(SP, O5_savedSP); | |
3394 } | |
3395 | |
3396 | |
3397 static void make_new_frames(MacroAssembler* masm, bool deopt) { | |
3398 // | |
3399 // loop through the UnrollBlock info and create new frames | |
3400 // | |
3401 Register G3pcs = G3_scratch; | |
3402 Register Oreturn0 = O0; | |
3403 Register Oreturn1 = O1; | |
3404 Register O2UnrollBlock = O2; | |
3405 Register O3array = O3; | |
3406 Register O4array_size = O4; | |
3407 Label loop; | |
3408 | |
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3409 #ifdef ASSERT |
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3410 // Compilers generate code that bang the stack by as much as the |
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3411 // interpreter would need. So this stack banging should never |
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3412 // trigger a fault. Verify that it does not on non product builds. |
0 | 3413 if (UseStackBanging) { |
3414 // Get total frame size for interpreted frames | |
727 | 3415 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); |
0 | 3416 __ bang_stack_size(O4, O3, G3_scratch); |
3417 } | |
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3418 #endif |
0 | 3419 |
727 | 3420 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); |
3421 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); | |
3422 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); | |
0 | 3423 |
3424 // Adjust old interpreter frame to make space for new frame's extra java locals | |
3425 // | |
3426 // We capture the original sp for the transition frame only because it is needed in | |
3427 // order to properly calculate interpreter_sp_adjustment. Even though in real life | |
3428 // every interpreter frame captures a savedSP it is only needed at the transition | |
3429 // (fortunately). If we had to have it correct everywhere then we would need to | |
3430 // be told the sp_adjustment for each frame we create. If the frame size array | |
3431 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] | |
3432 // for each frame we create and keep up the illusion every where. | |
3433 // | |
3434 | |
727 | 3435 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); |
0 | 3436 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment |
3437 __ sub(SP, O7, SP); | |
3438 | |
3439 #ifdef ASSERT | |
3440 // make sure that there is at least one entry in the array | |
3441 __ tst(O4array_size); | |
5923 | 3442 __ breakpoint_trap(Assembler::zero, Assembler::icc); |
0 | 3443 #endif |
3444 | |
3445 // Now push the new interpreter frames | |
3446 __ bind(loop); | |
3447 | |
3448 // allocate a new frame, filling the registers | |
3449 | |
3450 gen_new_frame(masm, deopt); // allocate an interpreter frame | |
3451 | |
3839 | 3452 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); |
0 | 3453 __ delayed()->add(O3array, wordSize, O3array); |
3454 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc | |
3455 | |
3456 } | |
3457 | |
3458 //------------------------------generate_deopt_blob---------------------------- | |
3459 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
3460 // instead. | |
3461 void SharedRuntime::generate_deopt_blob() { | |
3462 // allocate space for the code | |
3463 ResourceMark rm; | |
3464 // setup code generation tools | |
3465 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code | |
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3466 #ifdef ASSERT |
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3467 if (UseStackBanging) { |
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3468 pad += StackShadowPages*16 + 32; |
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3469 } |
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3470 #endif |
22298 | 3471 #if INCLUDE_JVMCI |
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3472 pad += 1000; // Increase the buffer size when compiling for JVMCI |
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3473 #endif |
0 | 3474 #ifdef _LP64 |
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3475 CodeBuffer buffer("deopt_blob", 2100+pad+1000, 512); |
0 | 3476 #else |
3477 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) | |
3478 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) | |
3479 CodeBuffer buffer("deopt_blob", 1600+pad, 512); | |
3480 #endif /* _LP64 */ | |
3481 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3482 FloatRegister Freturn0 = F0; | |
3483 Register Greturn1 = G1; | |
3484 Register Oreturn0 = O0; | |
3485 Register Oreturn1 = O1; | |
3486 Register O2UnrollBlock = O2; | |
1037 | 3487 Register L0deopt_mode = L0; |
3488 Register G4deopt_mode = G4_scratch; | |
0 | 3489 int frame_size_words; |
727 | 3490 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); |
0 | 3491 #if !defined(_LP64) && defined(COMPILER2) |
727 | 3492 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); |
0 | 3493 #endif |
3494 Label cont; | |
3495 | |
3496 OopMapSet *oop_maps = new OopMapSet(); | |
3497 | |
3498 // | |
3499 // This is the entry point for code which is returning to a de-optimized | |
3500 // frame. | |
3501 // The steps taken by this frame are as follows: | |
3502 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) | |
3503 // and all potentially live registers (at a pollpoint many registers can be live). | |
3504 // | |
3505 // - call the C routine: Deoptimization::fetch_unroll_info (this function | |
3506 // returns information about the number and size of interpreter frames | |
3507 // which are equivalent to the frame which is being deoptimized) | |
3508 // - deallocate the unpack frame, restoring only results values. Other | |
3509 // volatile registers will now be captured in the vframeArray as needed. | |
3510 // - deallocate the deoptimization frame | |
3511 // - in a loop using the information returned in the previous step | |
3512 // push new interpreter frames (take care to propagate the return | |
3513 // values through each new frame pushed) | |
3514 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) | |
3515 // - call the C routine: Deoptimization::unpack_frames (this function | |
3516 // lays out values on the interpreter frame which was just created) | |
3517 // - deallocate the dummy unpack_frame | |
3518 // - ensure that all the return values are correctly set and then do | |
3519 // a return to the interpreter entry point | |
3520 // | |
3521 // Refer to the following methods for more information: | |
3522 // - Deoptimization::fetch_unroll_info | |
3523 // - Deoptimization::unpack_frames | |
3524 | |
3525 OopMap* map = NULL; | |
3526 | |
3527 int start = __ offset(); | |
3528 | |
3529 // restore G2, the trampoline destroyed it | |
3530 __ get_thread(); | |
3531 | |
3532 // On entry we have been called by the deoptimized nmethod with a call that | |
3533 // replaced the original call (or safepoint polling location) so the deoptimizing | |
3534 // pc is now in O7. Return values are still in the expected places | |
3535 | |
3536 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3839 | 3537 __ ba(cont); |
1037 | 3538 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); |
0 | 3539 |
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3540 |
22298 | 3541 #if INCLUDE_JVMCI |
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3542 masm->block_comment("BEGIN JVMCI"); |
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3543 int implicit_exception_uncommon_trap_offset = __ offset() - start; |
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3544 __ ld_ptr(G2_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset()), O7); |
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3545 DEBUG_ONLY(__ st(G0, Address(G2_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())));) |
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3546 __ add(O7, -8, O7); |
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3547 |
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3548 int uncommon_trap_offset = __ offset() - start; |
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3549 |
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3550 // Save everything in sight. |
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3551 masm->block_comment("save_live_regs"); |
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3552 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); |
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3553 masm->block_comment("/save_live_regs"); |
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3554 masm->block_comment("set_last_java_frame"); |
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3555 __ set_last_Java_frame(SP, NULL); |
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3556 masm->block_comment("/set_last_java_frame"); |
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3557 |
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3558 __ ld(G2_thread, in_bytes(JavaThread::pending_deoptimization_offset()), O1); |
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3559 __ sub(G0, 1, L1); |
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3560 __ st_ptr(L1, G2_thread, in_bytes(JavaThread::pending_deoptimization_offset())); |
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3561 |
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3562 __ mov((int32_t)Deoptimization::Unpack_reexecute, L0deopt_mode); |
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3563 __ mov(G2_thread, O0); |
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3564 __ call(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)); |
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3565 __ delayed()->nop(); |
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3566 oop_maps->add_gc_map( __ offset()-start, map->deep_copy()); |
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3567 __ get_thread(); |
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3568 __ add(O7, 8, O7); |
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3569 __ reset_last_Java_frame(); |
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3570 |
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3571 Label after_fetch_unroll_info_call; |
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3572 __ ba(after_fetch_unroll_info_call); |
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3573 __ delayed()->nop(); // Delay slot |
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3574 masm->block_comment("END JVMCI"); |
22298 | 3575 #endif // INCLUDE_JVMCI |
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3576 |
0 | 3577 int exception_offset = __ offset() - start; |
3578 | |
3579 // restore G2, the trampoline destroyed it | |
3580 __ get_thread(); | |
3581 | |
3582 // On entry we have been jumped to by the exception handler (or exception_blob | |
3583 // for server). O0 contains the exception oop and O7 contains the original | |
3584 // exception pc. So if we push a frame here it will look to the | |
3585 // stack walking code (fetch_unroll_info) just like a normal call so | |
3586 // state will be extracted normally. | |
3587 | |
3588 // save exception oop in JavaThread and fall through into the | |
3589 // exception_in_tls case since they are handled in same way except | |
3590 // for where the pending exception is kept. | |
727 | 3591 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); |
0 | 3592 |
3593 // | |
3594 // Vanilla deoptimization with an exception pending in exception_oop | |
3595 // | |
3596 int exception_in_tls_offset = __ offset() - start; | |
3597 | |
3598 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
16641
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3599 // Opens a new stack frame |
0 | 3600 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); |
3601 | |
3602 // Restore G2_thread | |
3603 __ get_thread(); | |
3604 | |
3605 #ifdef ASSERT | |
3606 { | |
3607 // verify that there is really an exception oop in exception_oop | |
3608 Label has_exception; | |
727 | 3609 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); |
3839 | 3610 __ br_notnull_short(Oexception, Assembler::pt, has_exception); |
0 | 3611 __ stop("no exception in thread"); |
3612 __ bind(has_exception); | |
3613 | |
3614 // verify that there is no pending exception | |
3615 Label no_pending_exception; | |
727 | 3616 Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
0 | 3617 __ ld_ptr(exception_addr, Oexception); |
3839 | 3618 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); |
0 | 3619 __ stop("must not have pending exception here"); |
3620 __ bind(no_pending_exception); | |
3621 } | |
3622 #endif | |
3623 | |
3839 | 3624 __ ba(cont); |
1037 | 3625 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; |
0 | 3626 |
3627 // | |
3628 // Reexecute entry, similar to c2 uncommon trap | |
3629 // | |
3630 int reexecute_offset = __ offset() - start; | |
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3631 #if defined(COMPILERJVMCI) && !defined(COMPILER1) |
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3632 // JVMCI does not use this kind of deoptimization |
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3633 __ should_not_reach_here(); |
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3634 #endif |
0 | 3635 // No need to update oop_map as each call to save_live_registers will produce identical oopmap |
3636 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3637 | |
1037 | 3638 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); |
0 | 3639 |
3640 __ bind(cont); | |
3641 | |
3642 __ set_last_Java_frame(SP, noreg); | |
3643 | |
3644 // do the call by hand so we can get the oopmap | |
3645 | |
3646 __ mov(G2_thread, L7_thread_cache); | |
3647 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); | |
3648 __ delayed()->mov(G2_thread, O0); | |
3649 | |
3650 // Set an oopmap for the call site this describes all our saved volatile registers | |
3651 | |
3652 oop_maps->add_gc_map( __ offset()-start, map); | |
3653 | |
3654 __ mov(L7_thread_cache, G2_thread); | |
3655 | |
3656 __ reset_last_Java_frame(); | |
3657 | |
22298 | 3658 #if INCLUDE_JVMCI |
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3659 __ bind(after_fetch_unroll_info_call); |
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3660 #endif |
0 | 3661 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers |
3662 // so this move will survive | |
3663 | |
1037 | 3664 __ mov(L0deopt_mode, G4deopt_mode); |
0 | 3665 |
3666 __ mov(O0, O2UnrollBlock->after_save()); | |
3667 | |
3668 RegisterSaver::restore_result_registers(masm); | |
3669 | |
3670 Label noException; | |
3839 | 3671 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); |
0 | 3672 |
3673 // Move the pending exception from exception_oop to Oexception so | |
3674 // the pending exception will be picked up the interpreter. | |
3675 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); | |
3676 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); | |
12884
e504cd481ec0
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3677 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
0 | 3678 __ bind(noException); |
3679 | |
3680 // deallocate the deoptimization frame taking care to preserve the return values | |
3681 __ mov(Oreturn0, Oreturn0->after_save()); | |
3682 __ mov(Oreturn1, Oreturn1->after_save()); | |
3683 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
3684 __ restore(); | |
3685 | |
3686 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
3687 | |
3688 make_new_frames(masm, true); | |
3689 | |
3690 // push a dummy "unpack_frame" taking care of float return values and | |
3691 // call Deoptimization::unpack_frames to have the unpacker layout | |
3692 // information in the interpreter frames just created and then return | |
3693 // to the interpreter entry point | |
3694 __ save(SP, -frame_size_words*wordSize, SP); | |
3695 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); | |
3696 #if !defined(_LP64) | |
3697 #if defined(COMPILER2) | |
1783 | 3698 // 32-bit 1-register longs return longs in G1 |
3699 __ stx(Greturn1, saved_Greturn1_addr); | |
0 | 3700 #endif |
3701 __ set_last_Java_frame(SP, noreg); | |
1037 | 3702 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); |
0 | 3703 #else |
3704 // LP64 uses g4 in set_last_Java_frame | |
1037 | 3705 __ mov(G4deopt_mode, O1); |
0 | 3706 __ set_last_Java_frame(SP, G0); |
3707 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); | |
3708 #endif | |
3709 __ reset_last_Java_frame(); | |
3710 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); | |
3711 | |
3712 #if !defined(_LP64) && defined(COMPILER2) | |
3713 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into | |
1783 | 3714 // I0/I1 if the return value is long. |
3715 Label not_long; | |
3839 | 3716 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); |
1783 | 3717 __ ldd(saved_Greturn1_addr,I0); |
3718 __ bind(not_long); | |
0 | 3719 #endif |
3720 __ ret(); | |
3721 __ delayed()->restore(); | |
3722 | |
3723 masm->flush(); | |
3724 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); | |
3725 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); | |
22298 | 3726 #if INCLUDE_JVMCI |
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3727 _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset); |
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3728 _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset); |
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3729 #endif |
0 | 3730 } |
3731 | |
3732 #ifdef COMPILER2 | |
3733 | |
3734 //------------------------------generate_uncommon_trap_blob-------------------- | |
3735 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
3736 // instead. | |
3737 void SharedRuntime::generate_uncommon_trap_blob() { | |
3738 // allocate space for the code | |
3739 ResourceMark rm; | |
3740 // setup code generation tools | |
3741 int pad = VerifyThread ? 512 : 0; | |
17980
0bf37f737702
8032410: compiler/uncommontrap/TestStackBangRbp.java times out on Solaris-Sparc V9
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|
3742 #ifdef ASSERT |
4957
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|
3743 if (UseStackBanging) { |
931e5f39e365
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3744 pad += StackShadowPages*16 + 32; |
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3745 } |
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3746 #endif |
0 | 3747 #ifdef _LP64 |
3748 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); | |
3749 #else | |
3750 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) | |
3751 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) | |
3752 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); | |
3753 #endif | |
3754 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3755 Register O2UnrollBlock = O2; | |
3756 Register O2klass_index = O2; | |
3757 | |
3758 // | |
3759 // This is the entry point for all traps the compiler takes when it thinks | |
3760 // it cannot handle further execution of compilation code. The frame is | |
3761 // deoptimized in these cases and converted into interpreter frames for | |
3762 // execution | |
3763 // The steps taken by this frame are as follows: | |
3764 // - push a fake "unpack_frame" | |
3765 // - call the C routine Deoptimization::uncommon_trap (this function | |
3766 // packs the current compiled frame into vframe arrays and returns | |
3767 // information about the number and size of interpreter frames which | |
3768 // are equivalent to the frame which is being deoptimized) | |
3769 // - deallocate the "unpack_frame" | |
3770 // - deallocate the deoptimization frame | |
3771 // - in a loop using the information returned in the previous step | |
3772 // push interpreter frames; | |
3773 // - create a dummy "unpack_frame" | |
3774 // - call the C routine: Deoptimization::unpack_frames (this function | |
3775 // lays out values on the interpreter frame which was just created) | |
3776 // - deallocate the dummy unpack_frame | |
3777 // - return to the interpreter entry point | |
3778 // | |
3779 // Refer to the following methods for more information: | |
3780 // - Deoptimization::uncommon_trap | |
3781 // - Deoptimization::unpack_frame | |
3782 | |
3783 // the unloaded class index is in O0 (first parameter to this blob) | |
3784 | |
3785 // push a dummy "unpack_frame" | |
3786 // and call Deoptimization::uncommon_trap to pack the compiled frame into | |
3787 // vframe array and return the UnrollBlock information | |
3788 __ save_frame(0); | |
3789 __ set_last_Java_frame(SP, noreg); | |
3790 __ mov(I0, O2klass_index); | |
3791 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); | |
3792 __ reset_last_Java_frame(); | |
3793 __ mov(O0, O2UnrollBlock->after_save()); | |
3794 __ restore(); | |
3795 | |
3796 // deallocate the deoptimized frame taking care to preserve the return values | |
3797 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
3798 __ restore(); | |
3799 | |
3800 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
3801 | |
3802 make_new_frames(masm, false); | |
3803 | |
3804 // push a dummy "unpack_frame" taking care of float return values and | |
3805 // call Deoptimization::unpack_frames to have the unpacker layout | |
3806 // information in the interpreter frames just created and then return | |
3807 // to the interpreter entry point | |
3808 __ save_frame(0); | |
3809 __ set_last_Java_frame(SP, noreg); | |
3810 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case | |
3811 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); | |
3812 __ reset_last_Java_frame(); | |
3813 __ ret(); | |
3814 __ delayed()->restore(); | |
3815 | |
3816 masm->flush(); | |
3817 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); | |
3818 } | |
3819 | |
3820 #endif // COMPILER2 | |
3821 | |
3822 //------------------------------generate_handler_blob------------------- | |
3823 // | |
3824 // Generate a special Compile2Runtime blob that saves all registers, and sets | |
3825 // up an OopMap. | |
3826 // | |
3827 // This blob is jumped to (via a breakpoint and the signal handler) from a | |
3828 // safepoint in compiled code. On entry to this blob, O7 contains the | |
3829 // address in the original nmethod at which we should resume normal execution. | |
3830 // Thus, this blob looks like a subroutine which must preserve lots of | |
3831 // registers and return normally. Note that O7 is never register-allocated, | |
3832 // so it is guaranteed to be free here. | |
3833 // | |
3834 | |
3835 // The hardest part of what this blob must do is to save the 64-bit %o | |
3836 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and | |
3837 // an interrupt will chop off their heads. Making space in the caller's frame | |
3838 // first will let us save the 64-bit %o's before save'ing, but we cannot hand | |
3839 // the adjusted FP off to the GC stack-crawler: this will modify the caller's | |
3840 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save | |
3841 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). | |
3842 // Tricky, tricky, tricky... | |
3843 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6790
diff
changeset
|
3844 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { |
0 | 3845 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
3846 | |
3847 // allocate space for the code | |
3848 ResourceMark rm; | |
3849 // setup code generation tools | |
3850 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
3851 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
3852 // even larger with TraceJumps | |
3853 int pad = TraceJumps ? 512 : 0; | |
3854 CodeBuffer buffer("handler_blob", 1600 + pad, 512); | |
3855 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3856 int frame_size_words; | |
3857 OopMapSet *oop_maps = new OopMapSet(); | |
3858 OopMap* map = NULL; | |
3859 | |
3860 int start = __ offset(); | |
3861 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6790
diff
changeset
|
3862 bool cause_return = (poll_type == POLL_AT_RETURN); |
0 | 3863 // If this causes a return before the processing, then do a "restore" |
3864 if (cause_return) { | |
3865 __ restore(); | |
3866 } else { | |
3867 // Make it look like we were called via the poll | |
3868 // so that frame constructor always sees a valid return address | |
3869 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); | |
3870 __ sub(O7, frame::pc_return_offset, O7); | |
3871 } | |
3872 | |
3873 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3874 | |
3875 // setup last_Java_sp (blows G4) | |
3876 __ set_last_Java_frame(SP, noreg); | |
3877 | |
3878 // call into the runtime to handle illegal instructions exception | |
3879 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
3880 __ mov(G2_thread, O0); | |
3881 __ save_thread(L7_thread_cache); | |
3882 __ call(call_ptr); | |
3883 __ delayed()->nop(); | |
3884 | |
3885 // Set an oopmap for the call site. | |
3886 // We need this not only for callee-saved registers, but also for volatile | |
3887 // registers that the compiler might be keeping live across a safepoint. | |
3888 | |
3889 oop_maps->add_gc_map( __ offset() - start, map); | |
3890 | |
3891 __ restore_thread(L7_thread_cache); | |
3892 // clear last_Java_sp | |
3893 __ reset_last_Java_frame(); | |
3894 | |
3895 // Check for exceptions | |
3896 Label pending; | |
3897 | |
3898 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
3839 | 3899 __ br_notnull_short(O1, Assembler::pn, pending); |
0 | 3900 |
3901 RegisterSaver::restore_live_registers(masm); | |
3902 | |
3903 // We are back the the original state on entry and ready to go. | |
3904 | |
3905 __ retl(); | |
3906 __ delayed()->nop(); | |
3907 | |
3908 // Pending exception after the safepoint | |
3909 | |
3910 __ bind(pending); | |
3911 | |
3912 RegisterSaver::restore_live_registers(masm); | |
3913 | |
3914 // We are back the the original state on entry. | |
3915 | |
3916 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
3917 // so it looks like the original nmethod called forward_exception_entry. | |
3918 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
3919 __ JMP(O0, 0); | |
3920 __ delayed()->nop(); | |
3921 | |
3922 // ------------- | |
3923 // make sure all code is generated | |
3924 masm->flush(); | |
3925 | |
3926 // return exception blob | |
3927 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); | |
3928 } | |
3929 | |
3930 // | |
3931 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss | |
3932 // | |
3933 // Generate a stub that calls into vm to find out the proper destination | |
3934 // of a java call. All the argument registers are live at this point | |
3935 // but since this is generic code we don't know what they are and the caller | |
3936 // must do any gc of the args. | |
3937 // | |
3442
f7d55ea6ee56
7045514: SPARC assembly code for JSR 292 ricochet frames
never
parents:
2405
diff
changeset
|
3938 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { |
0 | 3939 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
3940 | |
3941 // allocate space for the code | |
3942 ResourceMark rm; | |
3943 // setup code generation tools | |
3944 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
3945 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
3946 // even larger with TraceJumps | |
3947 int pad = TraceJumps ? 512 : 0; | |
3948 CodeBuffer buffer(name, 1600 + pad, 512); | |
3949 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3950 int frame_size_words; | |
3951 OopMapSet *oop_maps = new OopMapSet(); | |
3952 OopMap* map = NULL; | |
3953 | |
3954 int start = __ offset(); | |
3955 | |
3956 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3957 | |
3958 int frame_complete = __ offset(); | |
3959 | |
3960 // setup last_Java_sp (blows G4) | |
3961 __ set_last_Java_frame(SP, noreg); | |
3962 | |
3963 // call into the runtime to handle illegal instructions exception | |
3964 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
3965 __ mov(G2_thread, O0); | |
3966 __ save_thread(L7_thread_cache); | |
3967 __ call(destination, relocInfo::runtime_call_type); | |
3968 __ delayed()->nop(); | |
3969 | |
3970 // O0 contains the address we are going to jump to assuming no exception got installed | |
3971 | |
3972 // Set an oopmap for the call site. | |
3973 // We need this not only for callee-saved registers, but also for volatile | |
3974 // registers that the compiler might be keeping live across a safepoint. | |
3975 | |
3976 oop_maps->add_gc_map( __ offset() - start, map); | |
3977 | |
3978 __ restore_thread(L7_thread_cache); | |
3979 // clear last_Java_sp | |
3980 __ reset_last_Java_frame(); | |
3981 | |
3982 // Check for exceptions | |
3983 Label pending; | |
3984 | |
3985 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
3839 | 3986 __ br_notnull_short(O1, Assembler::pn, pending); |
0 | 3987 |
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6266
diff
changeset
|
3988 // get the returned Method* |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6266
diff
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|
3989 |
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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|
3990 __ get_vm_result_2(G5_method); |
0 | 3991 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); |
3992 | |
3993 // O0 is where we want to jump, overwrite G3 which is saved and scratch | |
3994 | |
3995 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); | |
3996 | |
3997 RegisterSaver::restore_live_registers(masm); | |
3998 | |
3999 // We are back the the original state on entry and ready to go. | |
4000 | |
4001 __ JMP(G3, 0); | |
4002 __ delayed()->nop(); | |
4003 | |
4004 // Pending exception after the safepoint | |
4005 | |
4006 __ bind(pending); | |
4007 | |
4008 RegisterSaver::restore_live_registers(masm); | |
4009 | |
4010 // We are back the the original state on entry. | |
4011 | |
4012 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
4013 // so it looks like the original nmethod called forward_exception_entry. | |
4014 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
4015 __ JMP(O0, 0); | |
4016 __ delayed()->nop(); | |
4017 | |
4018 // ------------- | |
4019 // make sure all code is generated | |
4020 masm->flush(); | |
4021 | |
4022 // return the blob | |
4023 // frame_size_words or bytes?? | |
4024 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); | |
4025 } |