Mercurial > hg > graal-jvmci-8
annotate src/cpu/sparc/vm/nativeInst_sparc.cpp @ 23660:b5f3a471e646
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author | Doug Simon <doug.simon@oracle.com> |
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date | Wed, 01 Jun 2016 00:11:44 +0200 |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.hpp" |
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27 #include "asm/macroAssembler.inline.hpp" |
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28 #include "code/codeCache.hpp" |
1972 | 29 #include "memory/resourceArea.hpp" |
30 #include "nativeInst_sparc.hpp" | |
31 #include "oops/oop.inline.hpp" | |
32 #include "runtime/handles.hpp" | |
33 #include "runtime/sharedRuntime.hpp" | |
34 #include "runtime/stubRoutines.hpp" | |
35 #include "utilities/ostream.hpp" | |
36 #ifdef COMPILER1 | |
37 #include "c1/c1_Runtime1.hpp" | |
38 #endif | |
0 | 39 |
40 | |
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41 bool NativeInstruction::is_dtrace_trap() { |
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42 return !is_nop(); |
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43 } |
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44 |
0 | 45 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) { |
46 ResourceMark rm; | |
47 CodeBuffer buf(instaddr, 10 * BytesPerInstWord ); | |
48 MacroAssembler* _masm = new MacroAssembler(&buf); | |
49 Register destreg; | |
50 | |
51 destreg = inv_rd(*(unsigned int *)instaddr); | |
52 // Generate a the new sequence | |
727 | 53 _masm->patchable_sethi(x, destreg); |
0 | 54 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord); |
55 } | |
56 | |
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57 void NativeInstruction::verify_data64_sethi(address instaddr, intptr_t x) { |
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58 ResourceMark rm; |
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59 unsigned char buffer[10 * BytesPerInstWord]; |
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60 CodeBuffer buf(buffer, 10 * BytesPerInstWord); |
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61 MacroAssembler masm(&buf); |
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62 |
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63 Register destreg = inv_rd(*(unsigned int *)instaddr); |
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64 // Generate the proper sequence into a temporary buffer and compare |
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65 // it with the original sequence. |
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66 masm.patchable_sethi(x, destreg); |
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67 int len = buffer - masm.pc(); |
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68 for (int i = 0; i < len; i++) { |
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69 assert(instaddr[i] == buffer[i], "instructions must match"); |
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70 } |
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71 } |
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72 |
0 | 73 void NativeInstruction::verify() { |
74 // make sure code pattern is actually an instruction address | |
75 address addr = addr_at(0); | |
76 if (addr == 0 || ((intptr_t)addr & 3) != 0) { | |
77 fatal("not an instruction address"); | |
78 } | |
79 } | |
80 | |
81 void NativeInstruction::print() { | |
82 tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0)); | |
83 } | |
84 | |
85 void NativeInstruction::set_long_at(int offset, int i) { | |
86 address addr = addr_at(offset); | |
87 *(int*)addr = i; | |
88 ICache::invalidate_word(addr); | |
89 } | |
90 | |
91 void NativeInstruction::set_jlong_at(int offset, jlong i) { | |
92 address addr = addr_at(offset); | |
93 *(jlong*)addr = i; | |
94 // Don't need to invalidate 2 words here, because | |
95 // the flush instruction operates on doublewords. | |
96 ICache::invalidate_word(addr); | |
97 } | |
98 | |
99 void NativeInstruction::set_addr_at(int offset, address x) { | |
100 address addr = addr_at(offset); | |
101 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment"); | |
102 *(uintptr_t*)addr = (uintptr_t)x; | |
103 // Don't need to invalidate 2 words here in the 64-bit case, | |
104 // because the flush instruction operates on doublewords. | |
105 ICache::invalidate_word(addr); | |
106 // The Intel code has this assertion for NativeCall::set_destination, | |
107 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset, | |
108 // NativeJump::set_jump_destination, and NativePushImm32::set_data | |
109 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction") | |
110 } | |
111 | |
112 bool NativeInstruction::is_zero_test(Register ®) { | |
113 int x = long_at(0); | |
114 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3); | |
115 if (is_op3(x, temp, Assembler::arith_op) && | |
116 inv_immed(x) && inv_rd(x) == G0) { | |
117 if (inv_rs1(x) == G0) { | |
118 reg = inv_rs2(x); | |
119 return true; | |
120 } else if (inv_rs2(x) == G0) { | |
121 reg = inv_rs1(x); | |
122 return true; | |
123 } | |
124 } | |
125 return false; | |
126 } | |
127 | |
128 bool NativeInstruction::is_load_store_with_small_offset(Register reg) { | |
129 int x = long_at(0); | |
130 if (is_op(x, Assembler::ldst_op) && | |
131 inv_rs1(x) == reg && inv_immed(x)) { | |
132 return true; | |
133 } | |
134 return false; | |
135 } | |
136 | |
137 void NativeCall::verify() { | |
138 NativeInstruction::verify(); | |
139 // make sure code pattern is actually a call instruction | |
140 if (!is_op(long_at(0), Assembler::call_op)) { | |
141 fatal("not a call"); | |
142 } | |
143 } | |
144 | |
145 void NativeCall::print() { | |
146 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); | |
147 } | |
148 | |
149 | |
150 // MT-safe patching of a call instruction (and following word). | |
151 // First patches the second word, and then atomicly replaces | |
152 // the first word with the first new instruction word. | |
153 // Other processors might briefly see the old first word | |
154 // followed by the new second word. This is OK if the old | |
155 // second word is harmless, and the new second word may be | |
156 // harmlessly executed in the delay slot of the call. | |
157 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) { | |
158 assert(Patching_lock->is_locked() || | |
159 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
160 assert (instr_addr != NULL, "illegal address for code patching"); | |
161 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call | |
162 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8"); | |
163 int i0 = ((int*)code_buffer)[0]; | |
164 int i1 = ((int*)code_buffer)[1]; | |
165 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord); | |
166 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
10997 | 167 *contention_addr == nop_instruction(), |
0 | 168 "must not interfere with original call"); |
169 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order | |
170 n_call->set_long_at(1*BytesPerInstWord, i1); | |
171 n_call->set_long_at(0*BytesPerInstWord, i0); | |
172 // NOTE: It is possible that another thread T will execute | |
173 // only the second patched word. | |
174 // In other words, since the original instruction is this | |
175 // call patching_stub; nop (NativeCall) | |
176 // and the new sequence from the buffer is this: | |
177 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) | |
178 // what T will execute is this: | |
179 // call patching_stub; add %r, %lo(K), %r | |
180 // thereby putting garbage into %r before calling the patching stub. | |
181 // This is OK, because the patching stub ignores the value of %r. | |
182 | |
183 // Make sure the first-patched instruction, which may co-exist | |
184 // briefly with the call, will do something harmless. | |
185 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
10997 | 186 *contention_addr == nop_instruction(), |
0 | 187 "must not interfere with original call"); |
188 } | |
189 | |
190 // Similar to replace_mt_safe, but just changes the destination. The | |
191 // important thing is that free-running threads are able to execute this | |
192 // call instruction at all times. Thus, the displacement field must be | |
193 // instruction-word-aligned. This is always true on SPARC. | |
194 // | |
195 // Used in the runtime linkage of calls; see class CompiledIC. | |
196 void NativeCall::set_destination_mt_safe(address dest) { | |
197 assert(Patching_lock->is_locked() || | |
198 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
199 // set_destination uses set_long_at which does the ICache::invalidate | |
200 set_destination(dest); | |
201 } | |
202 | |
203 // Code for unit testing implementation of NativeCall class | |
204 void NativeCall::test() { | |
205 #ifdef ASSERT | |
206 ResourceMark rm; | |
207 CodeBuffer cb("test", 100, 100); | |
208 MacroAssembler* a = new MacroAssembler(&cb); | |
209 NativeCall *nc; | |
210 uint idx; | |
211 int offsets[] = { | |
212 0x0, | |
213 0xfffffff0, | |
214 0x7ffffff0, | |
215 0x80000000, | |
216 0x20, | |
217 0x4000, | |
218 }; | |
219 | |
220 VM_Version::allow_all(); | |
221 | |
222 a->call( a->pc(), relocInfo::none ); | |
223 a->delayed()->nop(); | |
1748 | 224 nc = nativeCall_at( cb.insts_begin() ); |
0 | 225 nc->print(); |
226 | |
227 nc = nativeCall_overwriting_at( nc->next_instruction_address() ); | |
228 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
1748 | 229 nc->set_destination( cb.insts_begin() + offsets[idx] ); |
230 assert(nc->destination() == (cb.insts_begin() + offsets[idx]), "check unit test"); | |
0 | 231 nc->print(); |
232 } | |
233 | |
1748 | 234 nc = nativeCall_before( cb.insts_begin() + 8 ); |
0 | 235 nc->print(); |
236 | |
237 VM_Version::revert(); | |
238 #endif | |
239 } | |
240 // End code for unit testing implementation of NativeCall class | |
241 | |
242 //------------------------------------------------------------------- | |
243 | |
244 #ifdef _LP64 | |
245 | |
246 void NativeFarCall::set_destination(address dest) { | |
247 // Address materialized in the instruction stream, so nothing to do. | |
248 return; | |
249 #if 0 // What we'd do if we really did want to change the destination | |
250 if (destination() == dest) { | |
251 return; | |
252 } | |
253 ResourceMark rm; | |
254 CodeBuffer buf(addr_at(0), instruction_size + 1); | |
255 MacroAssembler* _masm = new MacroAssembler(&buf); | |
256 // Generate the new sequence | |
727 | 257 AddressLiteral(dest); |
258 _masm->jumpl_to(dest, O7, O7); | |
0 | 259 ICache::invalidate_range(addr_at(0), instruction_size ); |
260 #endif | |
261 } | |
262 | |
263 void NativeFarCall::verify() { | |
264 // make sure code pattern is actually a jumpl_to instruction | |
265 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to"); | |
266 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
267 nativeJump_at(addr_at(0))->verify(); | |
268 } | |
269 | |
270 bool NativeFarCall::is_call_at(address instr) { | |
271 return nativeInstruction_at(instr)->is_sethi(); | |
272 } | |
273 | |
274 void NativeFarCall::print() { | |
275 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination()); | |
276 } | |
277 | |
278 bool NativeFarCall::destination_is_compiled_verified_entry_point() { | |
279 nmethod* callee = CodeCache::find_nmethod(destination()); | |
280 if (callee == NULL) { | |
281 return false; | |
282 } else { | |
283 return destination() == callee->verified_entry_point(); | |
284 } | |
285 } | |
286 | |
287 // MT-safe patching of a far call. | |
288 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) { | |
289 Unimplemented(); | |
290 } | |
291 | |
292 // Code for unit testing implementation of NativeFarCall class | |
293 void NativeFarCall::test() { | |
294 Unimplemented(); | |
295 } | |
296 // End code for unit testing implementation of NativeFarCall class | |
297 | |
298 #endif // _LP64 | |
299 | |
300 //------------------------------------------------------------------- | |
301 | |
302 | |
303 void NativeMovConstReg::verify() { | |
304 NativeInstruction::verify(); | |
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305 // make sure code pattern is actually a "set_metadata" synthetic instruction |
0 | 306 // see MacroAssembler::set_oop() |
307 int i0 = long_at(sethi_offset); | |
308 int i1 = long_at(add_offset); | |
309 | |
310 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" | |
311 Register rd = inv_rd(i0); | |
312 #ifndef _LP64 | |
313 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && | |
314 is_op3(i1, Assembler::add_op3, Assembler::arith_op) && | |
315 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && | |
316 rd == inv_rs1(i1) && rd == inv_rd(i1))) { | |
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317 fatal("not a set_metadata"); |
0 | 318 } |
319 #else | |
320 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { | |
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321 fatal("not a set_metadata"); |
0 | 322 } |
323 #endif | |
324 } | |
325 | |
326 | |
327 void NativeMovConstReg::print() { | |
328 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); | |
329 } | |
330 | |
331 | |
332 #ifdef _LP64 | |
333 intptr_t NativeMovConstReg::data() const { | |
334 return data64(addr_at(sethi_offset), long_at(add_offset)); | |
335 } | |
336 #else | |
337 intptr_t NativeMovConstReg::data() const { | |
338 return data32(long_at(sethi_offset), long_at(add_offset)); | |
339 } | |
340 #endif | |
341 | |
342 | |
343 void NativeMovConstReg::set_data(intptr_t x) { | |
344 #ifdef _LP64 | |
345 set_data64_sethi(addr_at(sethi_offset), x); | |
346 #else | |
347 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); | |
348 #endif | |
349 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); | |
350 | |
351 // also store the value into an oop_Relocation cell, if any | |
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352 CodeBlob* cb = CodeCache::find_blob(instruction_address()); |
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353 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; |
0 | 354 if (nm != NULL) { |
355 RelocIterator iter(nm, instruction_address(), next_instruction_address()); | |
356 oop* oop_addr = NULL; | |
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357 Metadata** metadata_addr = NULL; |
0 | 358 while (iter.next()) { |
359 if (iter.type() == relocInfo::oop_type) { | |
360 oop_Relocation *r = iter.oop_reloc(); | |
361 if (oop_addr == NULL) { | |
362 oop_addr = r->oop_addr(); | |
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363 *oop_addr = cast_to_oop(x); |
0 | 364 } else { |
365 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); | |
366 } | |
367 } | |
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368 if (iter.type() == relocInfo::metadata_type) { |
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369 metadata_Relocation *r = iter.metadata_reloc(); |
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370 if (metadata_addr == NULL) { |
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371 metadata_addr = r->metadata_addr(); |
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372 *metadata_addr = (Metadata*)x; |
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373 } else { |
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374 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); |
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375 } |
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376 } |
0 | 377 } |
378 } | |
379 } | |
380 | |
381 | |
382 // Code for unit testing implementation of NativeMovConstReg class | |
383 void NativeMovConstReg::test() { | |
384 #ifdef ASSERT | |
385 ResourceMark rm; | |
386 CodeBuffer cb("test", 100, 100); | |
387 MacroAssembler* a = new MacroAssembler(&cb); | |
388 NativeMovConstReg* nm; | |
389 uint idx; | |
390 int offsets[] = { | |
391 0x0, | |
392 0x7fffffff, | |
393 0x80000000, | |
394 0xffffffff, | |
395 0x20, | |
396 4096, | |
397 4097, | |
398 }; | |
399 | |
400 VM_Version::allow_all(); | |
401 | |
727 | 402 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
403 a->sethi(al1, I3); | |
404 a->add(I3, al1.low10(), I3); | |
405 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); | |
406 a->sethi(al2, O2); | |
407 a->add(O2, al2.low10(), O2); | |
0 | 408 |
1748 | 409 nm = nativeMovConstReg_at( cb.insts_begin() ); |
0 | 410 nm->print(); |
411 | |
412 nm = nativeMovConstReg_at( nm->next_instruction_address() ); | |
413 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
414 nm->set_data( offsets[idx] ); | |
415 assert(nm->data() == offsets[idx], "check unit test"); | |
416 } | |
417 nm->print(); | |
418 | |
419 VM_Version::revert(); | |
420 #endif | |
421 } | |
422 // End code for unit testing implementation of NativeMovConstReg class | |
423 | |
424 //------------------------------------------------------------------- | |
425 | |
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426 void NativeMovConstReg32::verify() { |
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427 NativeInstruction::verify(); |
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428 // make sure code pattern is actually a "set_metadata" synthetic instruction |
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429 // see MacroAssembler::set_oop() |
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430 int i0 = long_at(sethi_offset); |
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431 int i1 = long_at(add_offset); |
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432 |
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433 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg" |
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434 Register rd = inv_rd(i0); |
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435 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { |
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436 fatal("not a set_metadata"); |
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437 } |
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438 } |
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439 |
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440 |
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441 void NativeMovConstReg32::print() { |
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442 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); |
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443 } |
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444 |
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445 |
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446 intptr_t NativeMovConstReg32::data() const { |
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447 return data32(long_at(sethi_offset), long_at(add_offset)); |
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448 } |
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449 |
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450 |
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451 void NativeMovConstReg32::set_data(intptr_t x) { |
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452 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x)); |
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453 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x)); |
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454 |
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455 // also store the value into an oop_Relocation cell, if any |
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456 CodeBlob* cb = CodeCache::find_blob(instruction_address()); |
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457 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; |
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458 if (nm != NULL) { |
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459 RelocIterator iter(nm, instruction_address(), next_instruction_address()); |
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460 oop* oop_addr = NULL; |
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461 Metadata** metadata_addr = NULL; |
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462 while (iter.next()) { |
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463 if (iter.type() == relocInfo::oop_type) { |
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464 oop_Relocation *r = iter.oop_reloc(); |
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465 if (oop_addr == NULL) { |
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466 oop_addr = r->oop_addr(); |
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467 *oop_addr = cast_to_oop(x); |
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468 } else { |
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469 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); |
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470 } |
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471 } |
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472 if (iter.type() == relocInfo::metadata_type) { |
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473 metadata_Relocation *r = iter.metadata_reloc(); |
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474 if (metadata_addr == NULL) { |
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475 metadata_addr = r->metadata_addr(); |
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476 *metadata_addr = (Metadata*)x; |
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477 } else { |
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478 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); |
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479 } |
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480 } |
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481 } |
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482 } |
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483 } |
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484 |
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485 //------------------------------------------------------------------- |
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486 |
0 | 487 void NativeMovConstRegPatching::verify() { |
488 NativeInstruction::verify(); | |
489 // Make sure code pattern is sethi/nop/add. | |
490 int i0 = long_at(sethi_offset); | |
491 int i1 = long_at(nop_offset); | |
492 int i2 = long_at(add_offset); | |
493 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
494 | |
495 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg" | |
496 // The casual reader should note that on Sparc a nop is a special case if sethi | |
497 // in which the destination register is %g0. | |
498 Register rd0 = inv_rd(i0); | |
499 Register rd1 = inv_rd(i1); | |
500 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 && | |
501 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi | |
502 is_op3(i2, Assembler::add_op3, Assembler::arith_op) && | |
503 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) && | |
504 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) { | |
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505 fatal("not a set_metadata"); |
0 | 506 } |
507 } | |
508 | |
509 | |
510 void NativeMovConstRegPatching::print() { | |
511 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data()); | |
512 } | |
513 | |
514 | |
515 int NativeMovConstRegPatching::data() const { | |
516 #ifdef _LP64 | |
517 return data64(addr_at(sethi_offset), long_at(add_offset)); | |
518 #else | |
519 return data32(long_at(sethi_offset), long_at(add_offset)); | |
520 #endif | |
521 } | |
522 | |
523 | |
524 void NativeMovConstRegPatching::set_data(int x) { | |
525 #ifdef _LP64 | |
526 set_data64_sethi(addr_at(sethi_offset), x); | |
527 #else | |
528 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x)); | |
529 #endif | |
530 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x)); | |
531 | |
532 // also store the value into an oop_Relocation cell, if any | |
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533 CodeBlob* cb = CodeCache::find_blob(instruction_address()); |
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534 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL; |
0 | 535 if (nm != NULL) { |
536 RelocIterator iter(nm, instruction_address(), next_instruction_address()); | |
537 oop* oop_addr = NULL; | |
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538 Metadata** metadata_addr = NULL; |
0 | 539 while (iter.next()) { |
540 if (iter.type() == relocInfo::oop_type) { | |
541 oop_Relocation *r = iter.oop_reloc(); | |
542 if (oop_addr == NULL) { | |
543 oop_addr = r->oop_addr(); | |
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544 *oop_addr = cast_to_oop(x); |
0 | 545 } else { |
546 assert(oop_addr == r->oop_addr(), "must be only one set-oop here"); | |
547 } | |
548 } | |
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549 if (iter.type() == relocInfo::metadata_type) { |
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550 metadata_Relocation *r = iter.metadata_reloc(); |
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551 if (metadata_addr == NULL) { |
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552 metadata_addr = r->metadata_addr(); |
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553 *metadata_addr = (Metadata*)x; |
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554 } else { |
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555 assert(metadata_addr == r->metadata_addr(), "must be only one set-metadata here"); |
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556 } |
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557 } |
0 | 558 } |
559 } | |
560 } | |
561 | |
562 | |
563 // Code for unit testing implementation of NativeMovConstRegPatching class | |
564 void NativeMovConstRegPatching::test() { | |
565 #ifdef ASSERT | |
566 ResourceMark rm; | |
567 CodeBuffer cb("test", 100, 100); | |
568 MacroAssembler* a = new MacroAssembler(&cb); | |
569 NativeMovConstRegPatching* nm; | |
570 uint idx; | |
571 int offsets[] = { | |
572 0x0, | |
573 0x7fffffff, | |
574 0x80000000, | |
575 0xffffffff, | |
576 0x20, | |
577 4096, | |
578 4097, | |
579 }; | |
580 | |
581 VM_Version::allow_all(); | |
582 | |
727 | 583 AddressLiteral al1(0xaaaabbbb, relocInfo::external_word_type); |
584 a->sethi(al1, I3); | |
0 | 585 a->nop(); |
727 | 586 a->add(I3, al1.low10(), I3); |
587 AddressLiteral al2(0xccccdddd, relocInfo::external_word_type); | |
588 a->sethi(al2, O2); | |
0 | 589 a->nop(); |
727 | 590 a->add(O2, al2.low10(), O2); |
0 | 591 |
1748 | 592 nm = nativeMovConstRegPatching_at( cb.insts_begin() ); |
0 | 593 nm->print(); |
594 | |
595 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() ); | |
596 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
597 nm->set_data( offsets[idx] ); | |
598 assert(nm->data() == offsets[idx], "check unit test"); | |
599 } | |
600 nm->print(); | |
601 | |
602 VM_Version::revert(); | |
603 #endif // ASSERT | |
604 } | |
605 // End code for unit testing implementation of NativeMovConstRegPatching class | |
606 | |
607 | |
608 //------------------------------------------------------------------- | |
609 | |
610 | |
611 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) { | |
612 Untested("copy_instruction_to"); | |
613 int instruction_size = next_instruction_address() - instruction_address(); | |
614 for (int i = 0; i < instruction_size; i += BytesPerInstWord) { | |
615 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i); | |
616 } | |
617 } | |
618 | |
619 | |
620 void NativeMovRegMem::verify() { | |
621 NativeInstruction::verify(); | |
622 // make sure code pattern is actually a "ld" or "st" of some sort. | |
623 int i0 = long_at(0); | |
624 int op3 = inv_op3(i0); | |
625 | |
626 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok"); | |
627 | |
628 if (!(is_op(i0, Assembler::ldst_op) && | |
629 inv_immed(i0) && | |
630 0 != (op3 < op3_ldst_int_limit | |
631 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
632 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) | |
633 { | |
634 int i1 = long_at(ldst_offset); | |
635 Register rd = inv_rd(i0); | |
636 | |
637 op3 = inv_op3(i1); | |
638 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && | |
639 0 != (op3 < op3_ldst_int_limit | |
640 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
641 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { | |
642 fatal("not a ld* or st* op"); | |
643 } | |
644 } | |
645 } | |
646 | |
647 | |
648 void NativeMovRegMem::print() { | |
649 if (is_immediate()) { | |
650 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); | |
651 } else { | |
652 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); | |
653 } | |
654 } | |
655 | |
656 | |
657 // Code for unit testing implementation of NativeMovRegMem class | |
658 void NativeMovRegMem::test() { | |
659 #ifdef ASSERT | |
660 ResourceMark rm; | |
661 CodeBuffer cb("test", 1000, 1000); | |
662 MacroAssembler* a = new MacroAssembler(&cb); | |
663 NativeMovRegMem* nm; | |
664 uint idx = 0; | |
665 uint idx1; | |
666 int offsets[] = { | |
667 0x0, | |
668 0xffffffff, | |
669 0x7fffffff, | |
670 0x80000000, | |
671 4096, | |
672 4097, | |
673 0x20, | |
674 0x4000, | |
675 }; | |
676 | |
677 VM_Version::allow_all(); | |
678 | |
727 | 679 AddressLiteral al1(0xffffffff, relocInfo::external_word_type); |
680 AddressLiteral al2(0xaaaabbbb, relocInfo::external_word_type); | |
681 a->ldsw( G5, al1.low10(), G4 ); idx++; | |
682 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 683 a->ldsw( G5, I3, G4 ); idx++; |
727 | 684 a->ldsb( G5, al1.low10(), G4 ); idx++; |
685 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 686 a->ldsb( G5, I3, G4 ); idx++; |
727 | 687 a->ldsh( G5, al1.low10(), G4 ); idx++; |
688 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 689 a->ldsh( G5, I3, G4 ); idx++; |
727 | 690 a->lduw( G5, al1.low10(), G4 ); idx++; |
691 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 692 a->lduw( G5, I3, G4 ); idx++; |
727 | 693 a->ldub( G5, al1.low10(), G4 ); idx++; |
694 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 695 a->ldub( G5, I3, G4 ); idx++; |
727 | 696 a->lduh( G5, al1.low10(), G4 ); idx++; |
697 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 698 a->lduh( G5, I3, G4 ); idx++; |
727 | 699 a->ldx( G5, al1.low10(), G4 ); idx++; |
700 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 701 a->ldx( G5, I3, G4 ); idx++; |
727 | 702 a->ldd( G5, al1.low10(), G4 ); idx++; |
703 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 704 a->ldd( G5, I3, G4 ); idx++; |
705 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; | |
727 | 706 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
0 | 707 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; |
708 | |
727 | 709 a->stw( G5, G4, al1.low10() ); idx++; |
710 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 711 a->stw( G5, G4, I3 ); idx++; |
727 | 712 a->stb( G5, G4, al1.low10() ); idx++; |
713 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 714 a->stb( G5, G4, I3 ); idx++; |
727 | 715 a->sth( G5, G4, al1.low10() ); idx++; |
716 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 717 a->sth( G5, G4, I3 ); idx++; |
727 | 718 a->stx( G5, G4, al1.low10() ); idx++; |
719 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 720 a->stx( G5, G4, I3 ); idx++; |
727 | 721 a->std( G5, G4, al1.low10() ); idx++; |
722 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); | |
0 | 723 a->std( G5, G4, I3 ); idx++; |
724 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; | |
727 | 725 a->sethi(al2, I3); a->add(I3, al2.low10(), I3); |
0 | 726 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
727 | |
1748 | 728 nm = nativeMovRegMem_at( cb.insts_begin() ); |
0 | 729 nm->print(); |
730 nm->set_offset( low10(0) ); | |
731 nm->print(); | |
732 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
733 nm->print(); | |
734 | |
735 while (--idx) { | |
736 nm = nativeMovRegMem_at( nm->next_instruction_address() ); | |
737 nm->print(); | |
738 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { | |
739 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); | |
740 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), | |
741 "check unit test"); | |
742 nm->print(); | |
743 } | |
744 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
745 nm->print(); | |
746 } | |
747 | |
748 VM_Version::revert(); | |
749 #endif // ASSERT | |
750 } | |
751 | |
752 // End code for unit testing implementation of NativeMovRegMem class | |
753 | |
754 //-------------------------------------------------------------------------------- | |
755 | |
756 | |
757 void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) { | |
758 Untested("copy_instruction_to"); | |
759 int instruction_size = next_instruction_address() - instruction_address(); | |
760 for (int i = 0; i < instruction_size; i += wordSize) { | |
761 *(long*)(new_instruction_address + i) = *(long*)(address(this) + i); | |
762 } | |
763 } | |
764 | |
765 | |
766 void NativeMovRegMemPatching::verify() { | |
767 NativeInstruction::verify(); | |
768 // make sure code pattern is actually a "ld" or "st" of some sort. | |
769 int i0 = long_at(0); | |
770 int op3 = inv_op3(i0); | |
771 | |
772 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
773 | |
774 if (!(is_op(i0, Assembler::ldst_op) && | |
775 inv_immed(i0) && | |
776 0 != (op3 < op3_ldst_int_limit | |
777 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
778 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) { | |
779 int i1 = long_at(ldst_offset); | |
780 Register rd = inv_rd(i0); | |
781 | |
782 op3 = inv_op3(i1); | |
783 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) && | |
784 0 != (op3 < op3_ldst_int_limit | |
785 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st) | |
786 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) { | |
787 fatal("not a ld* or st* op"); | |
788 } | |
789 } | |
790 } | |
791 | |
792 | |
793 void NativeMovRegMemPatching::print() { | |
794 if (is_immediate()) { | |
795 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset()); | |
796 } else { | |
797 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address()); | |
798 } | |
799 } | |
800 | |
801 | |
802 // Code for unit testing implementation of NativeMovRegMemPatching class | |
803 void NativeMovRegMemPatching::test() { | |
804 #ifdef ASSERT | |
805 ResourceMark rm; | |
806 CodeBuffer cb("test", 1000, 1000); | |
807 MacroAssembler* a = new MacroAssembler(&cb); | |
808 NativeMovRegMemPatching* nm; | |
809 uint idx = 0; | |
810 uint idx1; | |
811 int offsets[] = { | |
812 0x0, | |
813 0xffffffff, | |
814 0x7fffffff, | |
815 0x80000000, | |
816 4096, | |
817 4097, | |
818 0x20, | |
819 0x4000, | |
820 }; | |
821 | |
822 VM_Version::allow_all(); | |
823 | |
727 | 824 AddressLiteral al(0xffffffff, relocInfo::external_word_type); |
825 a->ldsw( G5, al.low10(), G4); idx++; | |
826 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 827 a->ldsw( G5, I3, G4 ); idx++; |
727 | 828 a->ldsb( G5, al.low10(), G4); idx++; |
829 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 830 a->ldsb( G5, I3, G4 ); idx++; |
727 | 831 a->ldsh( G5, al.low10(), G4); idx++; |
832 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 833 a->ldsh( G5, I3, G4 ); idx++; |
727 | 834 a->lduw( G5, al.low10(), G4); idx++; |
835 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 836 a->lduw( G5, I3, G4 ); idx++; |
727 | 837 a->ldub( G5, al.low10(), G4); idx++; |
838 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 839 a->ldub( G5, I3, G4 ); idx++; |
727 | 840 a->lduh( G5, al.low10(), G4); idx++; |
841 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 842 a->lduh( G5, I3, G4 ); idx++; |
727 | 843 a->ldx( G5, al.low10(), G4); idx++; |
844 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
845 a->ldx( G5, I3, G4 ); idx++; | |
846 a->ldd( G5, al.low10(), G4); idx++; | |
847 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
848 a->ldd( G5, I3, G4 ); idx++; | |
849 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++; | |
850 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
851 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++; | |
0 | 852 |
727 | 853 a->stw( G5, G4, al.low10()); idx++; |
854 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 855 a->stw( G5, G4, I3 ); idx++; |
727 | 856 a->stb( G5, G4, al.low10()); idx++; |
857 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 858 a->stb( G5, G4, I3 ); idx++; |
727 | 859 a->sth( G5, G4, al.low10()); idx++; |
860 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 861 a->sth( G5, G4, I3 ); idx++; |
727 | 862 a->stx( G5, G4, al.low10()); idx++; |
863 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 864 a->stx( G5, G4, I3 ); idx++; |
727 | 865 a->std( G5, G4, al.low10()); idx++; |
866 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); | |
0 | 867 a->std( G5, G4, I3 ); idx++; |
868 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++; | |
727 | 869 a->sethi(al, I3); a->nop(); a->add(I3, al.low10(), I3); |
0 | 870 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++; |
871 | |
1748 | 872 nm = nativeMovRegMemPatching_at( cb.insts_begin() ); |
0 | 873 nm->print(); |
874 nm->set_offset( low10(0) ); | |
875 nm->print(); | |
876 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
877 nm->print(); | |
878 | |
879 while (--idx) { | |
880 nm = nativeMovRegMemPatching_at( nm->next_instruction_address() ); | |
881 nm->print(); | |
882 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) { | |
883 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] ); | |
884 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]), | |
885 "check unit test"); | |
886 nm->print(); | |
887 } | |
888 nm->add_offset_in_bytes( low10(0xbb) * wordSize ); | |
889 nm->print(); | |
890 } | |
891 | |
892 VM_Version::revert(); | |
893 #endif // ASSERT | |
894 } | |
895 // End code for unit testing implementation of NativeMovRegMemPatching class | |
896 | |
897 | |
898 //-------------------------------------------------------------------------------- | |
899 | |
900 | |
901 void NativeJump::verify() { | |
902 NativeInstruction::verify(); | |
903 int i0 = long_at(sethi_offset); | |
904 int i1 = long_at(jmpl_offset); | |
905 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok"); | |
906 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg" | |
907 Register rd = inv_rd(i0); | |
908 #ifndef _LP64 | |
909 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 && | |
910 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) || | |
911 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) && | |
912 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) && | |
913 rd == inv_rs1(i1))) { | |
914 fatal("not a jump_to instruction"); | |
915 } | |
916 #else | |
917 // In LP64, the jump instruction location varies for non relocatable | |
918 // jumps, for example is could be sethi, xor, jmp instead of the | |
919 // 7 instructions for sethi. So let's check sethi only. | |
920 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) { | |
921 fatal("not a jump_to instruction"); | |
922 } | |
923 #endif | |
924 } | |
925 | |
926 | |
927 void NativeJump::print() { | |
928 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination()); | |
929 } | |
930 | |
931 | |
932 // Code for unit testing implementation of NativeJump class | |
933 void NativeJump::test() { | |
934 #ifdef ASSERT | |
935 ResourceMark rm; | |
936 CodeBuffer cb("test", 100, 100); | |
937 MacroAssembler* a = new MacroAssembler(&cb); | |
938 NativeJump* nj; | |
939 uint idx; | |
940 int offsets[] = { | |
941 0x0, | |
942 0xffffffff, | |
943 0x7fffffff, | |
944 0x80000000, | |
945 4096, | |
946 4097, | |
947 0x20, | |
948 0x4000, | |
949 }; | |
950 | |
951 VM_Version::allow_all(); | |
952 | |
727 | 953 AddressLiteral al(0x7fffbbbb, relocInfo::external_word_type); |
954 a->sethi(al, I3); | |
955 a->jmpl(I3, al.low10(), G0, RelocationHolder::none); | |
0 | 956 a->delayed()->nop(); |
727 | 957 a->sethi(al, I3); |
958 a->jmpl(I3, al.low10(), L3, RelocationHolder::none); | |
0 | 959 a->delayed()->nop(); |
960 | |
1748 | 961 nj = nativeJump_at( cb.insts_begin() ); |
0 | 962 nj->print(); |
963 | |
964 nj = nativeJump_at( nj->next_instruction_address() ); | |
965 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) { | |
966 nj->set_jump_destination( nj->instruction_address() + offsets[idx] ); | |
967 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test"); | |
968 nj->print(); | |
969 } | |
970 | |
971 VM_Version::revert(); | |
972 #endif // ASSERT | |
973 } | |
974 // End code for unit testing implementation of NativeJump class | |
975 | |
976 | |
977 void NativeJump::insert(address code_pos, address entry) { | |
978 Unimplemented(); | |
979 } | |
980 | |
981 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie) | |
982 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot). | |
983 // Atomic write can be only with 1 word. | |
984 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) { | |
985 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere | |
986 // in the header of the nmethod, within a short branch's span of the patch point. | |
987 // Set up the jump sequence using NativeJump::insert, and then use an annulled | |
988 // unconditional branch at the target site (an atomic 1-word update). | |
989 // Limitations: You can only patch nmethods, with any given nmethod patched at | |
990 // most once, and the patch must be in the nmethod's header. | |
991 // It's messy, but you can ask the CodeCache for the nmethod containing the | |
992 // target address. | |
993 | |
994 // %%%%% For now, do something MT-stupid: | |
995 ResourceMark rm; | |
996 int code_size = 1 * BytesPerInstWord; | |
997 CodeBuffer cb(verified_entry, code_size + 1); | |
998 MacroAssembler* a = new MacroAssembler(&cb); | |
10997 | 999 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler |
0 | 1000 ICache::invalidate_range(verified_entry, code_size); |
1001 } | |
1002 | |
1003 | |
1004 void NativeIllegalInstruction::insert(address code_pos) { | |
1005 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos); | |
1006 nii->set_long_at(0, illegal_instruction()); | |
1007 } | |
1008 | |
1009 static int illegal_instruction_bits = 0; | |
1010 | |
1011 int NativeInstruction::illegal_instruction() { | |
1012 if (illegal_instruction_bits == 0) { | |
1013 ResourceMark rm; | |
1014 char buf[40]; | |
1015 CodeBuffer cbuf((address)&buf[0], 20); | |
1016 MacroAssembler* a = new MacroAssembler(&cbuf); | |
1017 address ia = a->pc(); | |
1018 a->trap(ST_RESERVED_FOR_USER_0 + 1); | |
1019 int bits = *(int*)ia; | |
1020 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); | |
1021 illegal_instruction_bits = bits; | |
1022 assert(illegal_instruction_bits != 0, "oops"); | |
1023 } | |
1024 return illegal_instruction_bits; | |
1025 } | |
1026 | |
1027 static int ic_miss_trap_bits = 0; | |
1028 | |
1029 bool NativeInstruction::is_ic_miss_trap() { | |
1030 if (ic_miss_trap_bits == 0) { | |
1031 ResourceMark rm; | |
1032 char buf[40]; | |
1033 CodeBuffer cbuf((address)&buf[0], 20); | |
1034 MacroAssembler* a = new MacroAssembler(&cbuf); | |
1035 address ia = a->pc(); | |
1036 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2); | |
1037 int bits = *(int*)ia; | |
1038 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction"); | |
1039 ic_miss_trap_bits = bits; | |
1040 assert(ic_miss_trap_bits != 0, "oops"); | |
1041 } | |
1042 return long_at(0) == ic_miss_trap_bits; | |
1043 } | |
1044 | |
1045 | |
1046 bool NativeInstruction::is_illegal() { | |
1047 if (illegal_instruction_bits == 0) { | |
1048 return false; | |
1049 } | |
1050 return long_at(0) == illegal_instruction_bits; | |
1051 } | |
1052 | |
1053 | |
1054 void NativeGeneralJump::verify() { | |
1055 assert(((NativeInstruction *)this)->is_jump() || | |
1056 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction"); | |
1057 } | |
1058 | |
1059 | |
1060 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) { | |
1061 Assembler::Condition condition = Assembler::always; | |
1062 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) | | |
1063 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22); | |
1064 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos); | |
1065 ni->set_long_at(0, x); | |
1066 } | |
1067 | |
1068 | |
1069 // MT-safe patching of a jmp instruction (and following word). | |
1070 // First patches the second word, and then atomicly replaces | |
1071 // the first word with the first new instruction word. | |
1072 // Other processors might briefly see the old first word | |
1073 // followed by the new second word. This is OK if the old | |
1074 // second word is harmless, and the new second word may be | |
1075 // harmlessly executed in the delay slot of the call. | |
1076 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) { | |
1077 assert(Patching_lock->is_locked() || | |
1078 SafepointSynchronize::is_at_safepoint(), "concurrent code patching"); | |
1079 assert (instr_addr != NULL, "illegal address for code patching"); | |
1080 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call | |
1081 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8"); | |
1082 int i0 = ((int*)code_buffer)[0]; | |
1083 int i1 = ((int*)code_buffer)[1]; | |
1084 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord); | |
1085 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
10997 | 1086 *contention_addr == nop_instruction(), |
0 | 1087 "must not interfere with original call"); |
1088 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order | |
1089 h_jump->set_long_at(1*BytesPerInstWord, i1); | |
1090 h_jump->set_long_at(0*BytesPerInstWord, i0); | |
1091 // NOTE: It is possible that another thread T will execute | |
1092 // only the second patched word. | |
1093 // In other words, since the original instruction is this | |
1094 // jmp patching_stub; nop (NativeGeneralJump) | |
1095 // and the new sequence from the buffer is this: | |
1096 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg) | |
1097 // what T will execute is this: | |
1098 // jmp patching_stub; add %r, %lo(K), %r | |
1099 // thereby putting garbage into %r before calling the patching stub. | |
1100 // This is OK, because the patching stub ignores the value of %r. | |
1101 | |
1102 // Make sure the first-patched instruction, which may co-exist | |
1103 // briefly with the call, will do something harmless. | |
1104 assert(inv_op(*contention_addr) == Assembler::arith_op || | |
10997 | 1105 *contention_addr == nop_instruction(), |
0 | 1106 "must not interfere with original call"); |
1107 } |