Mercurial > hg > graal-jvmci-8
annotate src/cpu/x86/vm/x86_64.ad @ 24234:ea6f94ab283b default tip
Added tag jvmci-0.36 for changeset 8128b98d4736
| author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
|---|---|
| date | Mon, 18 Sep 2017 18:49:45 +0200 |
| parents | 719853999215 |
| children |
| rev | line source |
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| 0 | 1 // |
| 9154 | 2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // Specify priority of register selection within phases of register | |
| 135 // allocation. Highest priority is first. A useful heuristic is to | |
| 136 // give registers a low priority when they are required by machine | |
| 137 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 138 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 139 // which participate in fixed calling sequences should come last. | |
| 140 // Registers which are used as pairs must fall on an even boundary. | |
| 141 | |
| 142 alloc_class chunk0(R10, R10_H, | |
| 143 R11, R11_H, | |
| 144 R8, R8_H, | |
| 145 R9, R9_H, | |
| 146 R12, R12_H, | |
| 147 RCX, RCX_H, | |
| 148 RBX, RBX_H, | |
| 149 RDI, RDI_H, | |
| 150 RDX, RDX_H, | |
| 151 RSI, RSI_H, | |
| 152 RAX, RAX_H, | |
| 153 RBP, RBP_H, | |
| 154 R13, R13_H, | |
| 155 R14, R14_H, | |
| 156 R15, R15_H, | |
| 157 RSP, RSP_H); | |
| 158 | |
| 159 | |
| 160 //----------Architecture Description Register Classes-------------------------- | |
| 161 // Several register classes are automatically defined based upon information in | |
| 162 // this architecture description. | |
| 163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 167 // | |
| 168 | |
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169 // Empty register class. |
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170 reg_class no_reg(); |
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171 |
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172 // Class for all pointer registers (including RSP and RBP) |
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173 reg_class any_reg_with_rbp(RAX, RAX_H, |
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174 RDX, RDX_H, |
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175 RBP, RBP_H, |
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176 RDI, RDI_H, |
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177 RSI, RSI_H, |
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178 RCX, RCX_H, |
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179 RBX, RBX_H, |
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180 RSP, RSP_H, |
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181 R8, R8_H, |
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182 R9, R9_H, |
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183 R10, R10_H, |
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184 R11, R11_H, |
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185 R12, R12_H, |
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186 R13, R13_H, |
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187 R14, R14_H, |
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188 R15, R15_H); |
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189 |
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190 // Class for all pointer registers (including RSP, but excluding RBP) |
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191 reg_class any_reg_no_rbp(RAX, RAX_H, |
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192 RDX, RDX_H, |
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193 RDI, RDI_H, |
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194 RSI, RSI_H, |
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195 RCX, RCX_H, |
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196 RBX, RBX_H, |
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197 RSP, RSP_H, |
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198 R8, R8_H, |
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199 R9, R9_H, |
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200 R10, R10_H, |
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201 R11, R11_H, |
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202 R12, R12_H, |
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203 R13, R13_H, |
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204 R14, R14_H, |
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205 R15, R15_H); |
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206 |
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207 // Dynamic register class that selects at runtime between register classes |
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208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer). |
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209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp; |
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210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %}); |
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211 |
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212 // Class for all pointer registers (excluding RSP) |
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213 reg_class ptr_reg_with_rbp(RAX, RAX_H, |
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214 RDX, RDX_H, |
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215 RBP, RBP_H, |
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216 RDI, RDI_H, |
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217 RSI, RSI_H, |
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218 RCX, RCX_H, |
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219 RBX, RBX_H, |
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220 R8, R8_H, |
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221 R9, R9_H, |
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222 R10, R10_H, |
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223 R11, R11_H, |
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224 R13, R13_H, |
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225 R14, R14_H); |
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226 |
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227 // Class for all pointer registers (excluding RSP and RBP) |
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228 reg_class ptr_reg_no_rbp(RAX, RAX_H, |
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229 RDX, RDX_H, |
| 0 | 230 RDI, RDI_H, |
| 231 RSI, RSI_H, | |
| 232 RCX, RCX_H, | |
| 233 RBX, RBX_H, | |
| 234 R8, R8_H, | |
| 235 R9, R9_H, | |
| 236 R10, R10_H, | |
| 237 R11, R11_H, | |
| 238 R13, R13_H, | |
| 239 R14, R14_H); | |
| 240 | |
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241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp. |
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242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %}); |
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243 |
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244 // Class for all pointer registers (excluding RAX and RSP) |
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245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H, |
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246 RBP, RBP_H, |
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247 RDI, RDI_H, |
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248 RSI, RSI_H, |
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249 RCX, RCX_H, |
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250 RBX, RBX_H, |
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251 R8, R8_H, |
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252 R9, R9_H, |
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253 R10, R10_H, |
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254 R11, R11_H, |
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255 R13, R13_H, |
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256 R14, R14_H); |
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257 |
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258 // Class for all pointer registers (excluding RAX, RSP, and RBP) |
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259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H, |
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260 RDI, RDI_H, |
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261 RSI, RSI_H, |
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262 RCX, RCX_H, |
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263 RBX, RBX_H, |
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264 R8, R8_H, |
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265 R9, R9_H, |
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266 R10, R10_H, |
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267 R11, R11_H, |
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268 R13, R13_H, |
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269 R14, R14_H); |
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270 |
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271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp. |
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272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %}); |
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273 |
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274 // Class for all pointer registers (excluding RAX, RBX, and RSP) |
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275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H, |
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276 RBP, RBP_H, |
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277 RDI, RDI_H, |
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278 RSI, RSI_H, |
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279 RCX, RCX_H, |
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280 R8, R8_H, |
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281 R9, R9_H, |
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282 R10, R10_H, |
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283 R11, R11_H, |
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284 R13, R13_H, |
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285 R14, R14_H); |
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286 |
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287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP) |
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288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H, |
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289 RDI, RDI_H, |
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290 RSI, RSI_H, |
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291 RCX, RCX_H, |
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292 R8, R8_H, |
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293 R9, R9_H, |
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294 R10, R10_H, |
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295 R11, R11_H, |
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296 R13, R13_H, |
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297 R14, R14_H); |
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298 |
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299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp. |
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300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %}); |
| 0 | 301 |
| 302 // Singleton class for RAX pointer register | |
| 303 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 304 | |
| 305 // Singleton class for RBX pointer register | |
| 306 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 307 | |
| 308 // Singleton class for RSI pointer register | |
| 309 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 310 | |
| 311 // Singleton class for RDI pointer register | |
| 312 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 313 | |
| 314 // Singleton class for stack pointer | |
| 315 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 316 | |
| 317 // Singleton class for TLS pointer | |
| 318 reg_class ptr_r15_reg(R15, R15_H); | |
| 319 | |
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320 // Class for all long registers (excluding RSP) |
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321 reg_class long_reg_with_rbp(RAX, RAX_H, |
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322 RDX, RDX_H, |
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323 RBP, RBP_H, |
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324 RDI, RDI_H, |
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325 RSI, RSI_H, |
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326 RCX, RCX_H, |
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327 RBX, RBX_H, |
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328 R8, R8_H, |
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329 R9, R9_H, |
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330 R10, R10_H, |
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331 R11, R11_H, |
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332 R13, R13_H, |
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333 R14, R14_H); |
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334 |
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335 // Class for all long registers (excluding RSP and RBP) |
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336 reg_class long_reg_no_rbp(RAX, RAX_H, |
| 0 | 337 RDX, RDX_H, |
| 338 RDI, RDI_H, | |
| 339 RSI, RSI_H, | |
| 340 RCX, RCX_H, | |
| 341 RBX, RBX_H, | |
| 342 R8, R8_H, | |
| 343 R9, R9_H, | |
| 344 R10, R10_H, | |
| 345 R11, R11_H, | |
| 346 R13, R13_H, | |
| 347 R14, R14_H); | |
| 348 | |
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349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp. |
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350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %}); |
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351 |
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352 // Class for all long registers (excluding RAX, RDX and RSP) |
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353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H, |
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354 RDI, RDI_H, |
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355 RSI, RSI_H, |
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356 RCX, RCX_H, |
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357 RBX, RBX_H, |
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358 R8, R8_H, |
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359 R9, R9_H, |
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360 R10, R10_H, |
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361 R11, R11_H, |
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362 R13, R13_H, |
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363 R14, R14_H); |
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364 |
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365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP) |
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366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H, |
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367 RSI, RSI_H, |
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368 RCX, RCX_H, |
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369 RBX, RBX_H, |
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370 R8, R8_H, |
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371 R9, R9_H, |
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372 R10, R10_H, |
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373 R11, R11_H, |
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374 R13, R13_H, |
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375 R14, R14_H); |
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376 |
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377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp. |
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378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %}); |
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379 |
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380 // Class for all long registers (excluding RCX and RSP) |
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381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H, |
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382 RDI, RDI_H, |
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383 RSI, RSI_H, |
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384 RAX, RAX_H, |
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385 RDX, RDX_H, |
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386 RBX, RBX_H, |
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387 R8, R8_H, |
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388 R9, R9_H, |
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389 R10, R10_H, |
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390 R11, R11_H, |
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391 R13, R13_H, |
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392 R14, R14_H); |
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393 |
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394 // Class for all long registers (excluding RCX, RSP, and RBP) |
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395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H, |
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396 RSI, RSI_H, |
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397 RAX, RAX_H, |
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398 RDX, RDX_H, |
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399 RBX, RBX_H, |
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400 R8, R8_H, |
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401 R9, R9_H, |
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402 R10, R10_H, |
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403 R11, R11_H, |
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404 R13, R13_H, |
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405 R14, R14_H); |
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406 |
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407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp. |
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408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %}); |
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409 |
| 0 | 410 // Singleton class for RAX long register |
| 411 reg_class long_rax_reg(RAX, RAX_H); | |
| 412 | |
| 413 // Singleton class for RCX long register | |
| 414 reg_class long_rcx_reg(RCX, RCX_H); | |
| 415 | |
| 416 // Singleton class for RDX long register | |
| 417 reg_class long_rdx_reg(RDX, RDX_H); | |
| 418 | |
|
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419 // Class for all int registers (excluding RSP) |
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420 reg_class int_reg_with_rbp(RAX, |
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421 RDX, |
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422 RBP, |
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423 RDI, |
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424 RSI, |
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425 RCX, |
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426 RBX, |
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427 R8, |
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428 R9, |
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429 R10, |
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430 R11, |
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431 R13, |
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432 R14); |
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433 |
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434 // Class for all int registers (excluding RSP and RBP) |
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435 reg_class int_reg_no_rbp(RAX, |
| 0 | 436 RDX, |
| 437 RDI, | |
| 438 RSI, | |
|
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439 RCX, |
| 0 | 440 RBX, |
| 441 R8, | |
| 442 R9, | |
| 443 R10, | |
| 444 R11, | |
| 445 R13, | |
| 446 R14); | |
| 447 | |
|
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448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp. |
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449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %}); |
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450 |
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451 // Class for all int registers (excluding RCX and RSP) |
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452 reg_class int_no_rcx_reg_with_rbp(RAX, |
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453 RDX, |
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454 RBP, |
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455 RDI, |
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456 RSI, |
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457 RBX, |
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458 R8, |
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459 R9, |
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460 R10, |
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461 R11, |
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462 R13, |
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463 R14); |
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464 |
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465 // Class for all int registers (excluding RCX, RSP, and RBP) |
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466 reg_class int_no_rcx_reg_no_rbp(RAX, |
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467 RDX, |
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468 RDI, |
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469 RSI, |
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470 RBX, |
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471 R8, |
|
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472 R9, |
|
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473 R10, |
|
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474 R11, |
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475 R13, |
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476 R14); |
|
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|
477 |
|
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478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp. |
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479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %}); |
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480 |
|
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481 // Class for all int registers (excluding RAX, RDX, and RSP) |
|
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482 reg_class int_no_rax_rdx_reg_with_rbp(RBP, |
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483 RDI, |
|
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484 RSI, |
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485 RCX, |
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486 RBX, |
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487 R8, |
|
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488 R9, |
|
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489 R10, |
|
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490 R11, |
|
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491 R13, |
|
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492 R14); |
|
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|
493 |
|
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494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP) |
|
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495 reg_class int_no_rax_rdx_reg_no_rbp(RDI, |
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496 RSI, |
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497 RCX, |
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498 RBX, |
|
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499 R8, |
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500 R9, |
|
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501 R10, |
|
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502 R11, |
|
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503 R13, |
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|
504 R14); |
|
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505 |
|
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506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp. |
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507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %}); |
| 0 | 508 |
| 509 // Singleton class for RAX int register | |
| 510 reg_class int_rax_reg(RAX); | |
| 511 | |
| 512 // Singleton class for RBX int register | |
| 513 reg_class int_rbx_reg(RBX); | |
| 514 | |
| 515 // Singleton class for RCX int register | |
| 516 reg_class int_rcx_reg(RCX); | |
| 517 | |
| 518 // Singleton class for RCX int register | |
| 519 reg_class int_rdx_reg(RDX); | |
| 520 | |
| 521 // Singleton class for RCX int register | |
| 522 reg_class int_rdi_reg(RDI); | |
| 523 | |
| 524 // Singleton class for instruction pointer | |
| 525 // reg_class ip_reg(RIP); | |
| 526 | |
|
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527 %} |
| 0 | 528 |
| 529 //----------SOURCE BLOCK------------------------------------------------------- | |
| 530 // This is a block of C++ code which provides values, functions, and | |
| 531 // definitions necessary in the rest of the architecture description | |
| 532 source %{ | |
| 304 | 533 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 534 #define RELOC_DISP32 Assembler::disp32_operand |
| 535 | |
| 536 #define __ _masm. | |
| 537 | |
|
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538 static int clear_avx_size() { |
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539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper |
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540 } |
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541 |
| 0 | 542 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 543 // from the start of the call to the point where the return address | |
| 544 // will point. | |
| 545 int MachCallStaticJavaNode::ret_addr_offset() | |
| 546 { | |
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547 int offset = 5; // 5 bytes from start of call to where return address points |
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548 offset += clear_avx_size(); |
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549 return offset; |
| 0 | 550 } |
| 551 | |
| 552 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 553 { | |
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554 int offset = 15; // 15 bytes from start of call to where return address points |
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555 offset += clear_avx_size(); |
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556 return offset; |
| 0 | 557 } |
| 558 | |
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559 int MachCallRuntimeNode::ret_addr_offset() { |
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560 int offset = 13; // movq r10,#addr; callq (r10) |
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561 offset += clear_avx_size(); |
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562 return offset; |
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563 } |
| 0 | 564 |
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565 // Indicate if the safepoint node needs the polling page as an input, |
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566 // it does if the polling page is more than disp32 away. |
| 0 | 567 bool SafePointNode::needs_polling_address_input() |
| 568 { | |
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569 return Assembler::is_polling_page_far(); |
| 0 | 570 } |
| 571 | |
| 572 // | |
| 573 // Compute padding required for nodes which need alignment | |
| 574 // | |
| 575 | |
| 576 // The address of the call instruction needs to be 4-byte aligned to | |
| 577 // ensure that it does not span a cache line so that it can be patched. | |
| 578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 579 { | |
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580 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 581 current_offset += 1; // skip call opcode byte |
| 582 return round_to(current_offset, alignment_required()) - current_offset; | |
| 583 } | |
| 584 | |
| 585 // The address of the call instruction needs to be 4-byte aligned to | |
| 586 // ensure that it does not span a cache line so that it can be patched. | |
| 587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const | |
| 588 { | |
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589 current_offset += clear_avx_size(); // skip vzeroupper |
| 0 | 590 current_offset += 11; // skip movq instruction + call opcode byte |
| 591 return round_to(current_offset, alignment_required()) - current_offset; | |
| 592 } | |
| 593 | |
| 594 // EMIT_RM() | |
| 1748 | 595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 597 cbuf.insts()->emit_int8(c); |
| 0 | 598 } |
| 599 | |
| 600 // EMIT_CC() | |
| 1748 | 601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 602 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 603 cbuf.insts()->emit_int8(c); |
| 0 | 604 } |
| 605 | |
| 606 // EMIT_OPCODE() | |
| 1748 | 607 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 608 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 609 } |
| 610 | |
| 611 // EMIT_OPCODE() w/ relocation information | |
| 612 void emit_opcode(CodeBuffer &cbuf, | |
| 613 int code, relocInfo::relocType reloc, int offset, int format) | |
| 614 { | |
| 1748 | 615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 616 emit_opcode(cbuf, code); |
| 617 } | |
| 618 | |
| 619 // EMIT_D8() | |
| 1748 | 620 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 621 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 622 } |
| 623 | |
| 624 // EMIT_D16() | |
| 1748 | 625 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 626 cbuf.insts()->emit_int16(d16); | |
| 0 | 627 } |
| 628 | |
| 629 // EMIT_D32() | |
| 1748 | 630 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 631 cbuf.insts()->emit_int32(d32); | |
| 0 | 632 } |
| 633 | |
| 634 // EMIT_D64() | |
| 1748 | 635 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 636 cbuf.insts()->emit_int64(d64); | |
| 0 | 637 } |
| 638 | |
| 639 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 640 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 641 int d32, | |
| 642 relocInfo::relocType reloc, | |
| 643 int format) | |
| 644 { | |
| 645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 646 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 647 cbuf.insts()->emit_int32(d32); | |
| 0 | 648 } |
| 649 | |
| 650 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 652 #ifdef ASSERT |
| 653 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop"); |
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656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 657 } |
| 658 #endif | |
| 1748 | 659 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 660 cbuf.insts()->emit_int32(d32); | |
| 0 | 661 } |
| 662 | |
| 663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 664 address next_ip = cbuf.insts_end() + 4; |
| 0 | 665 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 666 external_word_Relocation::spec(addr), | |
| 667 RELOC_DISP32); | |
| 668 } | |
| 669 | |
| 670 | |
| 671 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 673 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 674 cbuf.insts()->emit_int64(d64); | |
| 0 | 675 } |
| 676 | |
| 677 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 679 #ifdef ASSERT |
| 680 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop"); |
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683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()), |
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684 "cannot embed scavengable oops in code"); |
| 0 | 685 } |
| 686 #endif | |
| 1748 | 687 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 688 cbuf.insts()->emit_int64(d64); | |
| 0 | 689 } |
| 690 | |
| 691 // Access stack slot for load or store | |
| 692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 693 { | |
| 694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 695 if (-0x80 <= disp && disp < 0x80) { | |
| 696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 698 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 699 } else { | |
| 700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 702 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 703 } | |
| 704 } | |
| 705 | |
| 706 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 707 void encode_RegMem(CodeBuffer &cbuf, | |
| 708 int reg, | |
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709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) |
| 0 | 710 { |
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711 assert(disp_reloc == relocInfo::none, "cannot have disp"); |
| 0 | 712 int regenc = reg & 7; |
| 713 int baseenc = base & 7; | |
| 714 int indexenc = index & 7; | |
| 715 | |
| 716 // There is no index & no scale, use form without SIB byte | |
| 717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 719 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 720 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
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721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 722 // If 8-bit displacement, mode 0x1 |
| 723 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 724 emit_d8(cbuf, disp); | |
| 725 } else { | |
| 726 // If 32-bit displacement | |
| 727 if (base == -1) { // Special flag for absolute address | |
| 728 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
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729 if (disp_reloc != relocInfo::none) { |
| 0 | 730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 731 } else { | |
| 732 emit_d32(cbuf, disp); | |
| 733 } | |
| 734 } else { | |
| 735 // Normal base + offset | |
| 736 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
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737 if (disp_reloc != relocInfo::none) { |
| 0 | 738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 739 } else { | |
| 740 emit_d32(cbuf, disp); | |
| 741 } | |
| 742 } | |
| 743 } | |
| 744 } else { | |
| 745 // Else, encode with the SIB byte | |
| 746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 747 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 748 // If no displacement | |
| 749 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 750 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 751 } else { | |
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752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) { |
| 0 | 753 // If 8-bit displacement, mode 0x1 |
| 754 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 755 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 756 emit_d8(cbuf, disp); | |
| 757 } else { | |
| 758 // If 32-bit displacement | |
| 759 if (base == 0x04 ) { | |
| 760 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 762 } else { | |
| 763 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 764 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 765 } | |
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766 if (disp_reloc != relocInfo::none) { |
| 0 | 767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); |
| 768 } else { | |
| 769 emit_d32(cbuf, disp); | |
| 770 } | |
| 771 } | |
| 772 } | |
| 773 } | |
| 774 } | |
| 775 | |
| 3457 | 776 // This could be in MacroAssembler but it's fairly C2 specific |
| 777 void emit_cmpfp_fixup(MacroAssembler& _masm) { | |
| 778 Label exit; | |
| 779 __ jccb(Assembler::noParity, exit); | |
| 780 __ pushf(); | |
| 4759 | 781 // |
| 782 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 783 // zero OF,AF,SF for NaN values. | |
| 784 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 785 // values returns 'less than' result (CF is set). | |
| 786 // Leave the rest of flags unchanged. | |
| 787 // | |
| 788 // 7 6 5 4 3 2 1 0 | |
| 789 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 790 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 791 // | |
| 3457 | 792 __ andq(Address(rsp, 0), 0xffffff2b); |
| 793 __ popf(); | |
| 794 __ bind(exit); | |
| 4759 | 795 } |
| 796 | |
| 797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 798 Label done; | |
| 799 __ movl(dst, -1); | |
| 800 __ jcc(Assembler::parity, done); | |
| 801 __ jcc(Assembler::below, done); | |
| 802 __ setb(Assembler::notEqual, dst); | |
| 803 __ movzbl(dst, dst); | |
| 804 __ bind(done); | |
| 3457 | 805 } |
| 806 | |
| 0 | 807 |
| 808 //============================================================================= | |
| 2008 | 809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 810 | |
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811 int Compile::ConstantTable::calculate_table_base_offset() const { |
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812 return 0; // absolute addressing, no offset |
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813 } |
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814 |
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815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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817 ShouldNotReachHere(); |
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818 } |
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819 |
| 2008 | 820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 821 // Empty encoding | |
| 822 } | |
| 823 | |
| 824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 825 return 0; | |
| 826 } | |
| 827 | |
| 828 #ifndef PRODUCT | |
| 829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 830 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 831 } | |
| 832 #endif | |
| 833 | |
| 834 | |
| 835 //============================================================================= | |
| 0 | 836 #ifndef PRODUCT |
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837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 838 Compile* C = ra_->C; |
| 839 | |
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840 int framesize = C->frame_size_in_bytes(); |
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841 int bangsize = C->bang_size_in_bytes(); |
| 0 | 842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
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843 // Remove wordSize for return addr which is already pushed. |
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844 framesize -= wordSize; |
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845 |
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846 if (C->need_stack_bang(bangsize)) { |
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847 framesize -= wordSize; |
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848 st->print("# stack bang (%d bytes)", bangsize); |
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849 st->print("\n\t"); |
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850 st->print("pushq rbp\t# Save rbp"); |
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851 if (PreserveFramePointer) { |
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852 st->print("\n\t"); |
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853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp"); |
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854 } |
|
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855 if (framesize) { |
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856 st->print("\n\t"); |
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857 st->print("subq rsp, #%d\t# Create frame",framesize); |
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858 } |
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859 } else { |
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860 st->print("subq rsp, #%d\t# Create frame",framesize); |
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861 st->print("\n\t"); |
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862 framesize -= wordSize; |
|
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863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize); |
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864 if (PreserveFramePointer) { |
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865 st->print("\n\t"); |
|
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866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp"); |
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867 if (framesize > 0) { |
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868 st->print("\n\t"); |
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869 st->print("addq rbp, #%d", framesize); |
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870 } |
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871 } |
| 0 | 872 } |
| 873 | |
| 874 if (VerifyStackAtCalls) { | |
|
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875 st->print("\n\t"); |
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876 framesize -= wordSize; |
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877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize); |
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878 #ifdef ASSERT |
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879 st->print("\n\t"); |
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880 st->print("# stack alignment check"); |
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881 #endif |
| 0 | 882 } |
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883 st->cr(); |
| 0 | 884 } |
| 885 #endif | |
| 886 | |
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887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 888 Compile* C = ra_->C; |
|
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889 MacroAssembler _masm(&cbuf); |
| 0 | 890 |
|
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891 int framesize = C->frame_size_in_bytes(); |
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892 int bangsize = C->bang_size_in_bytes(); |
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893 |
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894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false); |
| 0 | 895 |
| 1748 | 896 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 897 |
|
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898 if (C->has_mach_constant_base_node()) { |
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899 // NOTE: We set the table base offset here because users might be |
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900 // emitted before MachConstantBaseNode. |
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901 Compile::ConstantTable& constant_table = C->constant_table(); |
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902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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903 } |
| 0 | 904 } |
| 905 | |
| 906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 907 { | |
| 908 return MachNode::size(ra_); // too many variables; just compute it | |
| 909 // the hard way | |
| 910 } | |
| 911 | |
| 912 int MachPrologNode::reloc() const | |
| 913 { | |
| 914 return 0; // a large enough number | |
| 915 } | |
| 916 | |
| 917 //============================================================================= | |
| 918 #ifndef PRODUCT | |
| 919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 920 { | |
| 921 Compile* C = ra_->C; | |
|
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922 if (C->max_vector_size() > 16) { |
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923 st->print("vzeroupper"); |
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924 st->cr(); st->print("\t"); |
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925 } |
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926 |
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927 int framesize = C->frame_size_in_bytes(); |
| 0 | 928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 929 // Remove word for return adr already pushed | |
| 930 // and RBP | |
| 931 framesize -= 2*wordSize; | |
| 932 | |
| 933 if (framesize) { | |
|
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934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize); |
| 0 | 935 st->print("\t"); |
| 936 } | |
| 937 | |
|
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938 st->print_cr("popq rbp"); |
| 0 | 939 if (do_polling() && C->is_method_compilation()) { |
| 940 st->print("\t"); | |
|
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941 if (Assembler::is_polling_page_far()) { |
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942 st->print_cr("movq rscratch1, #polling_page_address\n\t" |
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943 "testl rax, [rscratch1]\t" |
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944 "# Safepoint: poll for GC"); |
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945 } else { |
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946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t" |
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947 "# Safepoint: poll for GC"); |
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948 } |
| 0 | 949 } |
| 950 } | |
| 951 #endif | |
| 952 | |
| 953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 954 { | |
| 955 Compile* C = ra_->C; | |
|
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956 if (C->max_vector_size() > 16) { |
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957 // Clear upper bits of YMM registers when current compiled code uses |
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958 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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959 MacroAssembler _masm(&cbuf); |
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960 __ vzeroupper(); |
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961 } |
|
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962 |
|
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963 int framesize = C->frame_size_in_bytes(); |
| 0 | 964 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 965 // Remove word for return adr already pushed | |
| 966 // and RBP | |
| 967 framesize -= 2*wordSize; | |
| 968 | |
| 969 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 970 | |
| 971 if (framesize) { | |
| 972 emit_opcode(cbuf, Assembler::REX_W); | |
| 973 if (framesize < 0x80) { | |
| 974 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 975 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 976 emit_d8(cbuf, framesize); | |
| 977 } else { | |
| 978 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 979 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 980 emit_d32(cbuf, framesize); | |
| 981 } | |
| 982 } | |
| 983 | |
| 984 // popq rbp | |
| 985 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 986 | |
| 987 if (do_polling() && C->is_method_compilation()) { | |
|
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988 MacroAssembler _masm(&cbuf); |
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989 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type); |
|
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990 if (Assembler::is_polling_page_far()) { |
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991 __ lea(rscratch1, polling_page); |
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992 __ relocate(relocInfo::poll_return_type); |
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993 __ testl(rax, Address(rscratch1, 0)); |
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994 } else { |
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995 __ testl(rax, polling_page); |
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996 } |
| 0 | 997 } |
| 998 } | |
| 999 | |
| 1000 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1001 { | |
|
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1002 return MachNode::size(ra_); // too many variables; just compute it |
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1003 // the hard way |
| 0 | 1004 } |
| 1005 | |
| 1006 int MachEpilogNode::reloc() const | |
| 1007 { | |
| 1008 return 2; // a large enough number | |
| 1009 } | |
| 1010 | |
| 1011 const Pipeline* MachEpilogNode::pipeline() const | |
| 1012 { | |
| 1013 return MachNode::pipeline_class(); | |
| 1014 } | |
| 1015 | |
| 1016 int MachEpilogNode::safepoint_offset() const | |
| 1017 { | |
| 1018 return 0; | |
| 1019 } | |
| 1020 | |
| 1021 //============================================================================= | |
| 1022 | |
| 1023 enum RC { | |
| 1024 rc_bad, | |
| 1025 rc_int, | |
| 1026 rc_float, | |
| 1027 rc_stack | |
| 1028 }; | |
| 1029 | |
| 1030 static enum RC rc_class(OptoReg::Name reg) | |
| 1031 { | |
| 1032 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1033 | |
| 1034 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1035 | |
| 1036 VMReg r = OptoReg::as_VMReg(reg); | |
| 1037 | |
| 1038 if (r->is_Register()) return rc_int; | |
| 1039 | |
| 1040 assert(r->is_XMMRegister(), "must be"); | |
| 1041 return rc_float; | |
| 1042 } | |
| 1043 | |
|
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1044 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
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1045 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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1046 int src_hi, int dst_hi, uint ireg, outputStream* st); |
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1047 |
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1048 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
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1049 int stack_offset, int reg, uint ireg, outputStream* st); |
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1050 |
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1051 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, |
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1052 int dst_offset, uint ireg, outputStream* st) { |
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1053 if (cbuf) { |
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1054 MacroAssembler _masm(cbuf); |
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1055 switch (ireg) { |
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1056 case Op_VecS: |
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1057 __ movq(Address(rsp, -8), rax); |
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1058 __ movl(rax, Address(rsp, src_offset)); |
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1059 __ movl(Address(rsp, dst_offset), rax); |
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1060 __ movq(rax, Address(rsp, -8)); |
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1061 break; |
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1062 case Op_VecD: |
|
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1063 __ pushq(Address(rsp, src_offset)); |
|
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1064 __ popq (Address(rsp, dst_offset)); |
|
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|
1065 break; |
|
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|
1066 case Op_VecX: |
|
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1067 __ pushq(Address(rsp, src_offset)); |
|
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1068 __ popq (Address(rsp, dst_offset)); |
|
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1069 __ pushq(Address(rsp, src_offset+8)); |
|
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1070 __ popq (Address(rsp, dst_offset+8)); |
|
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|
1071 break; |
|
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|
1072 case Op_VecY: |
|
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1073 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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1074 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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1075 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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1076 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
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1077 break; |
|
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|
1078 default: |
|
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1079 ShouldNotReachHere(); |
|
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|
1080 } |
|
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1081 #ifndef PRODUCT |
|
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1082 } else { |
|
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1083 switch (ireg) { |
|
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1084 case Op_VecS: |
|
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1085 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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1086 "movl rax, [rsp + #%d]\n\t" |
|
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1087 "movl [rsp + #%d], rax\n\t" |
|
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1088 "movq rax, [rsp - #8]", |
|
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1089 src_offset, dst_offset); |
|
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1090 break; |
|
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|
1091 case Op_VecD: |
|
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1092 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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1093 "popq [rsp + #%d]", |
|
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1094 src_offset, dst_offset); |
|
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|
1095 break; |
|
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|
1096 case Op_VecX: |
|
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1097 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t" |
|
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1098 "popq [rsp + #%d]\n\t" |
|
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1099 "pushq [rsp + #%d]\n\t" |
|
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1100 "popq [rsp + #%d]", |
|
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1101 src_offset, dst_offset, src_offset+8, dst_offset+8); |
|
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1102 break; |
|
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1103 case Op_VecY: |
|
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1104 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
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1105 "vmovdqu xmm0, [rsp + #%d]\n\t" |
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1106 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
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1107 "vmovdqu xmm0, [rsp - #32]", |
|
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1108 src_offset, dst_offset); |
|
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|
1109 break; |
|
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1110 default: |
|
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1111 ShouldNotReachHere(); |
|
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1112 } |
|
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1113 #endif |
|
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1114 } |
|
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1115 } |
|
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1116 |
| 0 | 1117 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, |
| 1118 PhaseRegAlloc* ra_, | |
| 1119 bool do_size, | |
|
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1120 outputStream* st) const { |
|
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1121 assert(cbuf != NULL || st != NULL, "sanity"); |
| 0 | 1122 // Get registers to move |
| 1123 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1124 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1125 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1126 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1127 | |
| 1128 enum RC src_second_rc = rc_class(src_second); | |
| 1129 enum RC src_first_rc = rc_class(src_first); | |
| 1130 enum RC dst_second_rc = rc_class(dst_second); | |
| 1131 enum RC dst_first_rc = rc_class(dst_first); | |
| 1132 | |
| 1133 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1134 "must move at least 1 register" ); | |
| 1135 | |
| 1136 if (src_first == dst_first && src_second == dst_second) { | |
| 1137 // Self copy, no move | |
| 1138 return 0; | |
|
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1139 } |
|
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1140 if (bottom_type()->isa_vect() != NULL) { |
|
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1141 uint ireg = ideal_reg(); |
|
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1142 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
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1143 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
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1144 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
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1145 // mem -> mem |
|
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1146 int src_offset = ra_->reg2offset(src_first); |
|
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1147 int dst_offset = ra_->reg2offset(dst_first); |
|
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1148 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st); |
|
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1149 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) { |
|
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1150 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st); |
|
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1151 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) { |
|
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1152 int stack_offset = ra_->reg2offset(dst_first); |
|
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1153 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st); |
|
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1154 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) { |
|
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1155 int stack_offset = ra_->reg2offset(src_first); |
|
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1156 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st); |
|
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1157 } else { |
|
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1158 ShouldNotReachHere(); |
|
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|
1159 } |
|
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1160 return 0; |
|
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|
1161 } |
|
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1162 if (src_first_rc == rc_stack) { |
| 0 | 1163 // mem -> |
| 1164 if (dst_first_rc == rc_stack) { | |
| 1165 // mem -> mem | |
| 1166 assert(src_second != dst_first, "overlap"); | |
| 1167 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1168 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1169 // 64-bit | |
| 1170 int src_offset = ra_->reg2offset(src_first); | |
| 1171 int dst_offset = ra_->reg2offset(dst_first); | |
| 1172 if (cbuf) { | |
|
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1173 MacroAssembler _masm(cbuf); |
|
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1174 __ pushq(Address(rsp, src_offset)); |
|
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1175 __ popq (Address(rsp, dst_offset)); |
| 0 | 1176 #ifndef PRODUCT |
|
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1177 } else { |
| 0 | 1178 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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1179 "popq [rsp + #%d]", |
|
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1180 src_offset, dst_offset); |
| 0 | 1181 #endif |
| 1182 } | |
| 1183 } else { | |
| 1184 // 32-bit | |
| 1185 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1186 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1187 // No pushl/popl, so: | |
| 1188 int src_offset = ra_->reg2offset(src_first); | |
| 1189 int dst_offset = ra_->reg2offset(dst_first); | |
| 1190 if (cbuf) { | |
|
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1191 MacroAssembler _masm(cbuf); |
|
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1192 __ movq(Address(rsp, -8), rax); |
|
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1193 __ movl(rax, Address(rsp, src_offset)); |
|
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1194 __ movl(Address(rsp, dst_offset), rax); |
|
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1195 __ movq(rax, Address(rsp, -8)); |
| 0 | 1196 #ifndef PRODUCT |
|
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1197 } else { |
| 0 | 1198 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" |
|
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1199 "movl rax, [rsp + #%d]\n\t" |
|
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1200 "movl [rsp + #%d], rax\n\t" |
|
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1201 "movq rax, [rsp - #8]", |
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1202 src_offset, dst_offset); |
| 0 | 1203 #endif |
| 1204 } | |
| 1205 } | |
|
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1206 return 0; |
| 0 | 1207 } else if (dst_first_rc == rc_int) { |
| 1208 // mem -> gpr | |
| 1209 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1210 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1211 // 64-bit | |
| 1212 int offset = ra_->reg2offset(src_first); | |
| 1213 if (cbuf) { | |
|
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1214 MacroAssembler _masm(cbuf); |
|
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1215 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1216 #ifndef PRODUCT |
|
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1217 } else { |
| 0 | 1218 st->print("movq %s, [rsp + #%d]\t# spill", |
| 1219 Matcher::regName[dst_first], | |
| 1220 offset); | |
| 1221 #endif | |
| 1222 } | |
| 1223 } else { | |
| 1224 // 32-bit | |
| 1225 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1226 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1227 int offset = ra_->reg2offset(src_first); | |
| 1228 if (cbuf) { | |
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1229 MacroAssembler _masm(cbuf); |
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1230 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset)); |
| 0 | 1231 #ifndef PRODUCT |
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1232 } else { |
| 0 | 1233 st->print("movl %s, [rsp + #%d]\t# spill", |
| 1234 Matcher::regName[dst_first], | |
| 1235 offset); | |
| 1236 #endif | |
| 1237 } | |
| 1238 } | |
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1239 return 0; |
| 0 | 1240 } else if (dst_first_rc == rc_float) { |
| 1241 // mem-> xmm | |
| 1242 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1243 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1244 // 64-bit | |
| 1245 int offset = ra_->reg2offset(src_first); | |
| 1246 if (cbuf) { | |
| 4759 | 1247 MacroAssembler _masm(cbuf); |
| 1248 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1249 #ifndef PRODUCT |
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1250 } else { |
| 0 | 1251 st->print("%s %s, [rsp + #%d]\t# spill", |
| 1252 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1253 Matcher::regName[dst_first], | |
| 1254 offset); | |
| 1255 #endif | |
| 1256 } | |
| 1257 } else { | |
| 1258 // 32-bit | |
| 1259 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1260 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1261 int offset = ra_->reg2offset(src_first); | |
| 1262 if (cbuf) { | |
| 4759 | 1263 MacroAssembler _masm(cbuf); |
| 1264 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset)); | |
| 0 | 1265 #ifndef PRODUCT |
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1266 } else { |
| 0 | 1267 st->print("movss %s, [rsp + #%d]\t# spill", |
| 1268 Matcher::regName[dst_first], | |
| 1269 offset); | |
| 1270 #endif | |
| 1271 } | |
| 1272 } | |
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1273 return 0; |
| 0 | 1274 } |
| 1275 } else if (src_first_rc == rc_int) { | |
| 1276 // gpr -> | |
| 1277 if (dst_first_rc == rc_stack) { | |
| 1278 // gpr -> mem | |
| 1279 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1280 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1281 // 64-bit | |
| 1282 int offset = ra_->reg2offset(dst_first); | |
| 1283 if (cbuf) { | |
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1284 MacroAssembler _masm(cbuf); |
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1285 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1286 #ifndef PRODUCT |
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1287 } else { |
| 0 | 1288 st->print("movq [rsp + #%d], %s\t# spill", |
| 1289 offset, | |
| 1290 Matcher::regName[src_first]); | |
| 1291 #endif | |
| 1292 } | |
| 1293 } else { | |
| 1294 // 32-bit | |
| 1295 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1296 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1297 int offset = ra_->reg2offset(dst_first); | |
| 1298 if (cbuf) { | |
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1299 MacroAssembler _masm(cbuf); |
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1300 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1301 #ifndef PRODUCT |
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1302 } else { |
| 0 | 1303 st->print("movl [rsp + #%d], %s\t# spill", |
| 1304 offset, | |
| 1305 Matcher::regName[src_first]); | |
| 1306 #endif | |
| 1307 } | |
| 1308 } | |
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1309 return 0; |
| 0 | 1310 } else if (dst_first_rc == rc_int) { |
| 1311 // gpr -> gpr | |
| 1312 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1313 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1314 // 64-bit | |
| 1315 if (cbuf) { | |
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1316 MacroAssembler _masm(cbuf); |
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1317 __ movq(as_Register(Matcher::_regEncode[dst_first]), |
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1318 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1319 #ifndef PRODUCT |
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1320 } else { |
| 0 | 1321 st->print("movq %s, %s\t# spill", |
| 1322 Matcher::regName[dst_first], | |
| 1323 Matcher::regName[src_first]); | |
| 1324 #endif | |
| 1325 } | |
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1326 return 0; |
| 0 | 1327 } else { |
| 1328 // 32-bit | |
| 1329 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1330 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1331 if (cbuf) { | |
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1332 MacroAssembler _masm(cbuf); |
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1333 __ movl(as_Register(Matcher::_regEncode[dst_first]), |
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1334 as_Register(Matcher::_regEncode[src_first])); |
| 0 | 1335 #ifndef PRODUCT |
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1336 } else { |
| 0 | 1337 st->print("movl %s, %s\t# spill", |
| 1338 Matcher::regName[dst_first], | |
| 1339 Matcher::regName[src_first]); | |
| 1340 #endif | |
| 1341 } | |
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1342 return 0; |
| 0 | 1343 } |
| 1344 } else if (dst_first_rc == rc_float) { | |
| 1345 // gpr -> xmm | |
| 1346 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1347 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1348 // 64-bit | |
| 1349 if (cbuf) { | |
| 4759 | 1350 MacroAssembler _masm(cbuf); |
| 1351 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1352 #ifndef PRODUCT |
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1353 } else { |
| 0 | 1354 st->print("movdq %s, %s\t# spill", |
| 1355 Matcher::regName[dst_first], | |
| 1356 Matcher::regName[src_first]); | |
| 1357 #endif | |
| 1358 } | |
| 1359 } else { | |
| 1360 // 32-bit | |
| 1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1363 if (cbuf) { | |
| 4759 | 1364 MacroAssembler _masm(cbuf); |
| 1365 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first])); | |
| 0 | 1366 #ifndef PRODUCT |
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1367 } else { |
| 0 | 1368 st->print("movdl %s, %s\t# spill", |
| 1369 Matcher::regName[dst_first], | |
| 1370 Matcher::regName[src_first]); | |
| 1371 #endif | |
| 1372 } | |
| 1373 } | |
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1374 return 0; |
| 0 | 1375 } |
| 1376 } else if (src_first_rc == rc_float) { | |
| 1377 // xmm -> | |
| 1378 if (dst_first_rc == rc_stack) { | |
| 1379 // xmm -> mem | |
| 1380 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1381 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1382 // 64-bit | |
| 1383 int offset = ra_->reg2offset(dst_first); | |
| 1384 if (cbuf) { | |
| 4759 | 1385 MacroAssembler _masm(cbuf); |
| 1386 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1387 #ifndef PRODUCT |
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1388 } else { |
| 0 | 1389 st->print("movsd [rsp + #%d], %s\t# spill", |
| 1390 offset, | |
| 1391 Matcher::regName[src_first]); | |
| 1392 #endif | |
| 1393 } | |
| 1394 } else { | |
| 1395 // 32-bit | |
| 1396 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1397 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1398 int offset = ra_->reg2offset(dst_first); | |
| 1399 if (cbuf) { | |
| 4759 | 1400 MacroAssembler _masm(cbuf); |
| 1401 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1402 #ifndef PRODUCT |
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1403 } else { |
| 0 | 1404 st->print("movss [rsp + #%d], %s\t# spill", |
| 1405 offset, | |
| 1406 Matcher::regName[src_first]); | |
| 1407 #endif | |
| 1408 } | |
| 1409 } | |
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1410 return 0; |
| 0 | 1411 } else if (dst_first_rc == rc_int) { |
| 1412 // xmm -> gpr | |
| 1413 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1414 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1415 // 64-bit | |
| 1416 if (cbuf) { | |
| 4759 | 1417 MacroAssembler _masm(cbuf); |
| 1418 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1419 #ifndef PRODUCT |
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1420 } else { |
| 0 | 1421 st->print("movdq %s, %s\t# spill", |
| 1422 Matcher::regName[dst_first], | |
| 1423 Matcher::regName[src_first]); | |
| 1424 #endif | |
| 1425 } | |
| 1426 } else { | |
| 1427 // 32-bit | |
| 1428 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1429 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1430 if (cbuf) { | |
| 4759 | 1431 MacroAssembler _masm(cbuf); |
| 1432 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1433 #ifndef PRODUCT |
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1434 } else { |
| 0 | 1435 st->print("movdl %s, %s\t# spill", |
| 1436 Matcher::regName[dst_first], | |
| 1437 Matcher::regName[src_first]); | |
| 1438 #endif | |
| 1439 } | |
| 1440 } | |
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1441 return 0; |
| 0 | 1442 } else if (dst_first_rc == rc_float) { |
| 1443 // xmm -> xmm | |
| 1444 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1445 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1446 // 64-bit | |
| 1447 if (cbuf) { | |
| 4759 | 1448 MacroAssembler _masm(cbuf); |
| 1449 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1450 #ifndef PRODUCT |
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1451 } else { |
| 0 | 1452 st->print("%s %s, %s\t# spill", |
| 1453 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1454 Matcher::regName[dst_first], | |
| 1455 Matcher::regName[src_first]); | |
| 1456 #endif | |
| 1457 } | |
| 1458 } else { | |
| 1459 // 32-bit | |
| 1460 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1461 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1462 if (cbuf) { | |
| 4759 | 1463 MacroAssembler _masm(cbuf); |
| 1464 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first])); | |
| 0 | 1465 #ifndef PRODUCT |
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1466 } else { |
| 0 | 1467 st->print("%s %s, %s\t# spill", |
| 1468 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1469 Matcher::regName[dst_first], | |
| 1470 Matcher::regName[src_first]); | |
| 1471 #endif | |
| 1472 } | |
| 1473 } | |
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1474 return 0; |
| 0 | 1475 } |
| 1476 } | |
| 1477 | |
| 1478 assert(0," foo "); | |
| 1479 Unimplemented(); | |
| 1480 return 0; | |
| 1481 } | |
| 1482 | |
| 1483 #ifndef PRODUCT | |
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1484 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1485 implementation(NULL, ra_, false, st); |
| 1486 } | |
| 1487 #endif | |
| 1488 | |
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1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { |
| 0 | 1490 implementation(&cbuf, ra_, false, NULL); |
| 1491 } | |
| 1492 | |
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1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { |
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1494 return MachNode::size(ra_); |
| 0 | 1495 } |
| 1496 | |
| 1497 //============================================================================= | |
| 1498 #ifndef PRODUCT | |
| 1499 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1500 { | |
| 1501 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1502 int reg = ra_->get_reg_first(this); | |
| 1503 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1504 Matcher::regName[reg], offset); | |
| 1505 } | |
| 1506 #endif | |
| 1507 | |
| 1508 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1509 { | |
| 1510 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1511 int reg = ra_->get_encode(this); | |
| 1512 if (offset >= 0x80) { | |
| 1513 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1514 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1515 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1516 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1517 emit_d32(cbuf, offset); | |
| 1518 } else { | |
| 1519 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1520 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1521 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1522 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1523 emit_d8(cbuf, offset); | |
| 1524 } | |
| 1525 } | |
| 1526 | |
| 1527 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1528 { | |
| 1529 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1530 return (offset < 0x80) ? 5 : 8; // REX | |
| 1531 } | |
| 1532 | |
| 1533 //============================================================================= | |
| 1534 #ifndef PRODUCT | |
| 1535 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1536 { | |
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1537 if (UseCompressedClassPointers) { |
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1538 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1539 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1"); |
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1540 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
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1541 } else { |
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1542 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1543 "# Inline cache check"); |
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1544 } |
| 0 | 1545 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
|
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|
1546 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1547 } |
| 1548 #endif | |
| 1549 | |
| 1550 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1551 { | |
| 1552 MacroAssembler masm(&cbuf); | |
| 1748 | 1553 uint insts_size = cbuf.insts_size(); |
|
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|
1554 if (UseCompressedClassPointers) { |
|
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|
1555 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1556 masm.cmpptr(rax, rscratch1); |
|
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|
1557 } else { |
| 304 | 1558 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
|
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|
1559 } |
| 0 | 1560 |
| 1561 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1562 | |
| 1563 /* WARNING these NOPs are critical so that verified entry point is properly | |
|
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|
1564 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1565 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
|
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|
1566 if (OptoBreakpoint) { |
| 0 | 1567 // Leave space for int3 |
|
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|
1568 nops_cnt -= 1; |
| 0 | 1569 } |
|
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|
1570 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
|
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|
1571 if (nops_cnt > 0) |
|
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|
1572 masm.nop(nops_cnt); |
| 0 | 1573 } |
| 1574 | |
| 1575 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1576 { | |
|
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|
1577 return MachNode::size(ra_); // too many variables; just compute it |
|
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|
1578 // the hard way |
| 0 | 1579 } |
|
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|
1580 |
| 0 | 1581 |
| 1582 //============================================================================= | |
| 1583 | |
| 1584 int Matcher::regnum_to_fpu_offset(int regnum) | |
| 1585 { | |
| 1586 return regnum - 32; // The FP registers are in the second chunk | |
| 1587 } | |
| 1588 | |
| 1589 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1590 const bool Matcher::convL2FSupported(void) { | |
| 1591 return true; | |
| 1592 } | |
| 1593 | |
| 1594 // Is this branch offset short enough that a short branch can be used? | |
| 1595 // | |
| 1596 // NOTE: If the platform does not provide any short branch variants, then | |
| 1597 // this method should return false for offset 0. | |
| 3851 | 1598 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1599 // The passed offset is relative to address of the branch. | |
| 1600 // On 86 a branch displacement is calculated relative to address | |
| 1601 // of a next instruction. | |
| 1602 offset -= br_size; | |
| 1603 | |
|
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|
1604 // the short version of jmpConUCF2 contains multiple branches, |
|
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|
1605 // making the reach slightly less |
|
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|
1606 if (rule == jmpConUCF2_rule) |
|
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|
1607 return (-126 <= offset && offset <= 125); |
|
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|
1608 return (-128 <= offset && offset <= 127); |
| 0 | 1609 } |
| 1610 | |
| 1611 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1612 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1613 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1614 | |
| 1615 // Probably always true, even if a temp register is required. | |
| 1616 return true; | |
| 1617 } | |
| 1618 | |
| 1619 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1620 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1621 | |
| 1622 // Threshold size for cleararray. | |
| 1623 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1624 | |
| 4047 | 1625 // No additional cost for CMOVL. |
| 1626 const int Matcher::long_cmove_cost() { return 0; } | |
| 1627 | |
| 1628 // No CMOVF/CMOVD with SSE2 | |
| 1629 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 1630 | |
|
14428
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|
1631 // Does the CPU require late expand (see block.cpp for description of late expand)? |
|
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|
1632 const bool Matcher::require_postalloc_expand = false; |
|
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|
1633 |
| 0 | 1634 // Should the Matcher clone shifts on addressing modes, expecting them |
| 1635 // to be subsumed into complex addressing expressions or compute them | |
| 1636 // into registers? True for Intel but false for most RISCs | |
| 1637 const bool Matcher::clone_shift_expressions = true; | |
| 1638 | |
|
2401
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|
1639 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
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|
1640 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1641 const bool Matcher::need_masked_shift_count = false; |
|
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|
1642 |
|
1575
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|
1643 bool Matcher::narrow_oop_use_complex_address() { |
|
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|
1644 assert(UseCompressedOops, "only for compressed oops code"); |
|
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|
1645 return (LogMinObjAlignmentInBytes <= 3); |
|
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|
1646 } |
|
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|
1647 |
|
6848
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|
1648 bool Matcher::narrow_klass_use_complex_address() { |
|
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|
1649 assert(UseCompressedClassPointers, "only for compressed klass code"); |
|
6848
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|
1650 return (LogKlassAlignmentInBytes <= 3); |
|
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|
1651 } |
|
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|
1652 |
| 0 | 1653 // Is it better to copy float constants, or load them directly from |
| 1654 // memory? Intel can load a float constant from a direct address, | |
| 1655 // requiring no extra registers. Most RISCs will have to materialize | |
| 1656 // an address into a register first, so they would do better to copy | |
| 1657 // the constant from stack. | |
| 1658 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 1659 | |
| 1660 // If CPU can load and store mis-aligned doubles directly then no | |
| 1661 // fixup is needed. Else we split the double into 2 integer pieces | |
| 1662 // and move it piece-by-piece. Only happens when passing doubles into | |
| 1663 // C code as the Java calling convention forces doubles to be aligned. | |
| 1664 const bool Matcher::misaligned_doubles_ok = true; | |
| 1665 | |
| 1666 // No-op on amd64 | |
| 1667 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 1668 | |
| 1669 // Advertise here if the CPU requires explicit rounding operations to | |
| 1670 // implement the UseStrictFP mode. | |
| 1671 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1672 | |
|
1274
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6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
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|
1673 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
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|
1674 // On x64 it is stored without convertion so we can use normal access. |
|
2883969d09e7
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|
1675 bool Matcher::float_in_double() { return false; } |
|
2883969d09e7
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|
1676 |
| 0 | 1677 // Do ints take an entire long register or just half? |
| 1678 const bool Matcher::int_in_long = true; | |
| 1679 | |
| 1680 // Return whether or not this register is ever used as an argument. | |
| 1681 // This function is used on startup to build the trampoline stubs in | |
| 1682 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 1683 // call in the trampoline, and arguments in those registers not be | |
| 1684 // available to the callee. | |
| 1685 bool Matcher::can_be_java_arg(int reg) | |
| 1686 { | |
| 1687 return | |
|
6179
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|
1688 reg == RDI_num || reg == RDI_H_num || |
|
8c92982cbbc4
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|
1689 reg == RSI_num || reg == RSI_H_num || |
|
8c92982cbbc4
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|
1690 reg == RDX_num || reg == RDX_H_num || |
|
8c92982cbbc4
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|
1691 reg == RCX_num || reg == RCX_H_num || |
|
8c92982cbbc4
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|
1692 reg == R8_num || reg == R8_H_num || |
|
8c92982cbbc4
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|
1693 reg == R9_num || reg == R9_H_num || |
|
8c92982cbbc4
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|
1694 reg == R12_num || reg == R12_H_num || |
|
8c92982cbbc4
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|
1695 reg == XMM0_num || reg == XMM0b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
1696 reg == XMM1_num || reg == XMM1b_num || |
|
8c92982cbbc4
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|
1697 reg == XMM2_num || reg == XMM2b_num || |
|
8c92982cbbc4
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|
1698 reg == XMM3_num || reg == XMM3b_num || |
|
8c92982cbbc4
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|
1699 reg == XMM4_num || reg == XMM4b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
1700 reg == XMM5_num || reg == XMM5b_num || |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
1701 reg == XMM6_num || reg == XMM6b_num || |
|
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|
1702 reg == XMM7_num || reg == XMM7b_num; |
| 0 | 1703 } |
| 1704 | |
| 1705 bool Matcher::is_spillable_arg(int reg) | |
| 1706 { | |
| 1707 return can_be_java_arg(reg); | |
| 1708 } | |
| 1709 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1710 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
1711 // In 64 bit mode a code which use multiply when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
1712 // devisor is constant is faster than hardware |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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diff
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|
1713 // DIV instruction (it uses MulHiL). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
1714 return false; |
|
ae065c367d93
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diff
changeset
|
1715 } |
|
ae065c367d93
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|
1716 |
| 0 | 1717 // Register for DIVI projection of divmodI |
| 1718 RegMask Matcher::divI_proj_mask() { | |
|
4121
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7090968: Allow adlc register class to depend on runtime conditions
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|
1719 return INT_RAX_REG_mask(); |
| 0 | 1720 } |
| 1721 | |
| 1722 // Register for MODI projection of divmodI | |
| 1723 RegMask Matcher::modI_proj_mask() { | |
|
4121
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|
1724 return INT_RDX_REG_mask(); |
| 0 | 1725 } |
| 1726 | |
| 1727 // Register for DIVL projection of divmodL | |
| 1728 RegMask Matcher::divL_proj_mask() { | |
|
4121
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7090968: Allow adlc register class to depend on runtime conditions
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diff
changeset
|
1729 return LONG_RAX_REG_mask(); |
| 0 | 1730 } |
| 1731 | |
| 1732 // Register for MODL projection of divmodL | |
| 1733 RegMask Matcher::modL_proj_mask() { | |
|
4121
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|
1734 return LONG_RDX_REG_mask(); |
| 0 | 1735 } |
| 1736 | |
|
23050
e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
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diff
changeset
|
1737 // Register for saving SP into on method handle invokes. Not used on x86_64. |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
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diff
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|
1738 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
23050
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|
1739 return NO_REG_mask(); |
|
1137
97125851f396
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|
1740 } |
|
97125851f396
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diff
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|
1741 |
| 0 | 1742 %} |
| 1743 | |
| 1744 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1745 // This block specifies the encoding classes used by the compiler to | |
| 1746 // output byte streams. Encoding classes are parameterized macros | |
| 1747 // used by Machine Instruction Nodes in order to generate the bit | |
| 1748 // encoding of the instruction. Operands specify their base encoding | |
| 1749 // interface with the interface keyword. There are currently | |
| 1750 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 1751 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 1752 // which returns its register number when queried. CONST_INTER causes | |
| 1753 // an operand to generate a function which returns the value of the | |
| 1754 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 1755 // four functions which return the Base Register, the Index Register, | |
| 1756 // the Scale Value, and the Offset Value of the operand when queried. | |
| 1757 // COND_INTER causes an operand to generate six functions which return | |
| 1758 // the encoding code (ie - encoding bits for the instruction) | |
| 1759 // associated with each basic boolean condition for a conditional | |
| 1760 // instruction. | |
| 1761 // | |
| 1762 // Instructions specify two basic values for encoding. Again, a | |
| 1763 // function is available to check if the constant displacement is an | |
| 1764 // oop. They use the ins_encode keyword to specify their encoding | |
| 1765 // classes (which must be a sequence of enc_class names, and their | |
| 1766 // parameters, specified in the encoding block), and they use the | |
| 1767 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1768 // tertiary opcode. Only the opcode sections which a particular | |
| 1769 // instruction needs for encoding need to be specified. | |
| 1770 encode %{ | |
| 1771 // Build emit functions for each basic byte or larger field in the | |
| 1772 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 1773 // from C++ code in the enc_class source block. Emit functions will | |
| 1774 // live in the main source block for now. In future, we can | |
| 1775 // generalize this by adding a syntax that specifies the sizes of | |
| 1776 // fields in an order, so that the adlc can build the emit functions | |
| 1777 // automagically | |
| 1778 | |
| 1779 // Emit primary opcode | |
| 1780 enc_class OpcP | |
| 1781 %{ | |
| 1782 emit_opcode(cbuf, $primary); | |
| 1783 %} | |
| 1784 | |
| 1785 // Emit secondary opcode | |
| 1786 enc_class OpcS | |
| 1787 %{ | |
| 1788 emit_opcode(cbuf, $secondary); | |
| 1789 %} | |
| 1790 | |
| 1791 // Emit tertiary opcode | |
| 1792 enc_class OpcT | |
| 1793 %{ | |
| 1794 emit_opcode(cbuf, $tertiary); | |
| 1795 %} | |
| 1796 | |
| 1797 // Emit opcode directly | |
| 1798 enc_class Opcode(immI d8) | |
| 1799 %{ | |
| 1800 emit_opcode(cbuf, $d8$$constant); | |
| 1801 %} | |
| 1802 | |
| 1803 // Emit size prefix | |
| 1804 enc_class SizePrefix | |
| 1805 %{ | |
| 1806 emit_opcode(cbuf, 0x66); | |
| 1807 %} | |
| 1808 | |
| 1809 enc_class reg(rRegI reg) | |
| 1810 %{ | |
| 1811 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 1812 %} | |
| 1813 | |
| 1814 enc_class reg_reg(rRegI dst, rRegI src) | |
| 1815 %{ | |
| 1816 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1817 %} | |
| 1818 | |
| 1819 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 1820 %{ | |
| 1821 emit_opcode(cbuf, $opcode$$constant); | |
| 1822 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 1823 %} | |
| 1824 | |
| 1825 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 1826 %{ | |
| 1827 // Full implementation of Java idiv and irem; checks for | |
| 1828 // special case as described in JVM spec., p.243 & p.271. | |
| 1829 // | |
| 1830 // normal case special case | |
| 1831 // | |
| 1832 // input : rax: dividend min_int | |
| 1833 // reg: divisor -1 | |
| 1834 // | |
| 1835 // output: rax: quotient (= rax idiv reg) min_int | |
| 1836 // rdx: remainder (= rax irem reg) 0 | |
| 1837 // | |
| 1838 // Code sequnce: | |
| 1839 // | |
| 1840 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 1841 // 5: 75 07/08 jne e <normal> | |
| 1842 // 7: 33 d2 xor %edx,%edx | |
| 1843 // [div >= 8 -> offset + 1] | |
| 1844 // [REX_B] | |
| 1845 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1846 // c: 74 03/04 je 11 <done> | |
| 1847 // 000000000000000e <normal>: | |
| 1848 // e: 99 cltd | |
| 1849 // [div >= 8 -> offset + 1] | |
| 1850 // [REX_B] | |
| 1851 // f: f7 f9 idiv $div | |
| 1852 // 0000000000000011 <done>: | |
| 1853 | |
| 1854 // cmp $0x80000000,%eax | |
| 1855 emit_opcode(cbuf, 0x3d); | |
| 1856 emit_d8(cbuf, 0x00); | |
| 1857 emit_d8(cbuf, 0x00); | |
| 1858 emit_d8(cbuf, 0x00); | |
| 1859 emit_d8(cbuf, 0x80); | |
| 1860 | |
| 1861 // jne e <normal> | |
| 1862 emit_opcode(cbuf, 0x75); | |
| 1863 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 1864 | |
| 1865 // xor %edx,%edx | |
| 1866 emit_opcode(cbuf, 0x33); | |
| 1867 emit_d8(cbuf, 0xD2); | |
| 1868 | |
| 1869 // cmp $0xffffffffffffffff,%ecx | |
| 1870 if ($div$$reg >= 8) { | |
| 1871 emit_opcode(cbuf, Assembler::REX_B); | |
| 1872 } | |
| 1873 emit_opcode(cbuf, 0x83); | |
| 1874 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1875 emit_d8(cbuf, 0xFF); | |
| 1876 | |
| 1877 // je 11 <done> | |
| 1878 emit_opcode(cbuf, 0x74); | |
| 1879 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 1880 | |
| 1881 // <normal> | |
| 1882 // cltd | |
| 1883 emit_opcode(cbuf, 0x99); | |
| 1884 | |
| 1885 // idivl (note: must be emitted by the user of this rule) | |
| 1886 // <done> | |
| 1887 %} | |
| 1888 | |
| 1889 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 1890 %{ | |
| 1891 // Full implementation of Java ldiv and lrem; checks for | |
| 1892 // special case as described in JVM spec., p.243 & p.271. | |
| 1893 // | |
| 1894 // normal case special case | |
| 1895 // | |
| 1896 // input : rax: dividend min_long | |
| 1897 // reg: divisor -1 | |
| 1898 // | |
| 1899 // output: rax: quotient (= rax idiv reg) min_long | |
| 1900 // rdx: remainder (= rax irem reg) 0 | |
| 1901 // | |
| 1902 // Code sequnce: | |
| 1903 // | |
| 1904 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 1905 // 7: 00 00 80 | |
| 1906 // a: 48 39 d0 cmp %rdx,%rax | |
| 1907 // d: 75 08 jne 17 <normal> | |
| 1908 // f: 33 d2 xor %edx,%edx | |
| 1909 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 1910 // 15: 74 05 je 1c <done> | |
| 1911 // 0000000000000017 <normal>: | |
| 1912 // 17: 48 99 cqto | |
| 1913 // 19: 48 f7 f9 idiv $div | |
| 1914 // 000000000000001c <done>: | |
| 1915 | |
| 1916 // mov $0x8000000000000000,%rdx | |
| 1917 emit_opcode(cbuf, Assembler::REX_W); | |
| 1918 emit_opcode(cbuf, 0xBA); | |
| 1919 emit_d8(cbuf, 0x00); | |
| 1920 emit_d8(cbuf, 0x00); | |
| 1921 emit_d8(cbuf, 0x00); | |
| 1922 emit_d8(cbuf, 0x00); | |
| 1923 emit_d8(cbuf, 0x00); | |
| 1924 emit_d8(cbuf, 0x00); | |
| 1925 emit_d8(cbuf, 0x00); | |
| 1926 emit_d8(cbuf, 0x80); | |
| 1927 | |
| 1928 // cmp %rdx,%rax | |
| 1929 emit_opcode(cbuf, Assembler::REX_W); | |
| 1930 emit_opcode(cbuf, 0x39); | |
| 1931 emit_d8(cbuf, 0xD0); | |
| 1932 | |
| 1933 // jne 17 <normal> | |
| 1934 emit_opcode(cbuf, 0x75); | |
| 1935 emit_d8(cbuf, 0x08); | |
| 1936 | |
| 1937 // xor %edx,%edx | |
| 1938 emit_opcode(cbuf, 0x33); | |
| 1939 emit_d8(cbuf, 0xD2); | |
| 1940 | |
| 1941 // cmp $0xffffffffffffffff,$div | |
| 1942 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 1943 emit_opcode(cbuf, 0x83); | |
| 1944 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 1945 emit_d8(cbuf, 0xFF); | |
| 1946 | |
| 1947 // je 1e <done> | |
| 1948 emit_opcode(cbuf, 0x74); | |
| 1949 emit_d8(cbuf, 0x05); | |
| 1950 | |
| 1951 // <normal> | |
| 1952 // cqto | |
| 1953 emit_opcode(cbuf, Assembler::REX_W); | |
| 1954 emit_opcode(cbuf, 0x99); | |
| 1955 | |
| 1956 // idivq (note: must be emitted by the user of this rule) | |
| 1957 // <done> | |
| 1958 %} | |
| 1959 | |
| 1960 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1961 enc_class OpcSE(immI imm) | |
| 1962 %{ | |
| 1963 // Emit primary opcode and set sign-extend bit | |
| 1964 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1965 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1966 emit_opcode(cbuf, $primary | 0x02); | |
| 1967 } else { | |
| 1968 // 32-bit immediate | |
| 1969 emit_opcode(cbuf, $primary); | |
| 1970 } | |
| 1971 %} | |
| 1972 | |
| 1973 enc_class OpcSErm(rRegI dst, immI imm) | |
| 1974 %{ | |
| 1975 // OpcSEr/m | |
| 1976 int dstenc = $dst$$reg; | |
| 1977 if (dstenc >= 8) { | |
| 1978 emit_opcode(cbuf, Assembler::REX_B); | |
| 1979 dstenc -= 8; | |
| 1980 } | |
| 1981 // Emit primary opcode and set sign-extend bit | |
| 1982 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1983 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 1984 emit_opcode(cbuf, $primary | 0x02); | |
| 1985 } else { | |
| 1986 // 32-bit immediate | |
| 1987 emit_opcode(cbuf, $primary); | |
| 1988 } | |
| 1989 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1990 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 1991 %} | |
| 1992 | |
| 1993 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 1994 %{ | |
| 1995 // OpcSEr/m | |
| 1996 int dstenc = $dst$$reg; | |
| 1997 if (dstenc < 8) { | |
| 1998 emit_opcode(cbuf, Assembler::REX_W); | |
| 1999 } else { | |
| 2000 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2001 dstenc -= 8; | |
| 2002 } | |
| 2003 // Emit primary opcode and set sign-extend bit | |
| 2004 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2005 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2006 emit_opcode(cbuf, $primary | 0x02); | |
| 2007 } else { | |
| 2008 // 32-bit immediate | |
| 2009 emit_opcode(cbuf, $primary); | |
| 2010 } | |
| 2011 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2012 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2013 %} | |
| 2014 | |
| 2015 enc_class Con8or32(immI imm) | |
| 2016 %{ | |
| 2017 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2018 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2019 $$$emit8$imm$$constant; | |
| 2020 } else { | |
| 2021 // 32-bit immediate | |
| 2022 $$$emit32$imm$$constant; | |
| 2023 } | |
| 2024 %} | |
| 2025 | |
| 2026 enc_class opc2_reg(rRegI dst) | |
| 2027 %{ | |
| 2028 // BSWAP | |
| 2029 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2030 %} | |
| 2031 | |
| 2032 enc_class opc3_reg(rRegI dst) | |
| 2033 %{ | |
| 2034 // BSWAP | |
| 2035 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2036 %} | |
| 2037 | |
| 2038 enc_class reg_opc(rRegI div) | |
| 2039 %{ | |
| 2040 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2041 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2042 %} | |
| 2043 | |
| 2044 enc_class enc_cmov(cmpOp cop) | |
| 2045 %{ | |
| 2046 // CMOV | |
| 2047 $$$emit8$primary; | |
| 2048 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2049 %} | |
| 2050 | |
| 2051 enc_class enc_PartialSubtypeCheck() | |
| 2052 %{ | |
| 2053 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2054 Register Rrax = as_Register(RAX_enc); // super class | |
| 2055 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2056 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
644
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2057 Label miss; |
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2058 const bool set_cond_codes = true; |
| 0 | 2059 |
| 2060 MacroAssembler _masm(&cbuf); | |
|
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2061 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
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2062 NULL, &miss, |
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2063 /*set_cond_codes:*/ true); |
| 0 | 2064 if ($primary) { |
| 304 | 2065 __ xorptr(Rrdi, Rrdi); |
| 0 | 2066 } |
| 2067 __ bind(miss); | |
| 2068 %} | |
| 2069 | |
|
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2070 enc_class clear_avx %{ |
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2071 debug_only(int off0 = cbuf.insts_size()); |
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2072 if (ra_->C->max_vector_size() > 16) { |
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2073 // Clear upper bits of YMM registers when current compiled code uses |
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2074 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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2075 MacroAssembler _masm(&cbuf); |
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2076 __ vzeroupper(); |
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2077 } |
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2078 debug_only(int off1 = cbuf.insts_size()); |
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2079 assert(off1 - off0 == clear_avx_size(), "correct size prediction"); |
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2080 %} |
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2081 |
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2082 enc_class Java_To_Runtime(method meth) %{ |
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2083 // No relocation needed |
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2084 MacroAssembler _masm(&cbuf); |
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2085 __ mov64(r10, (int64_t) $meth$$method); |
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2086 __ call(r10); |
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2087 %} |
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2088 |
| 0 | 2089 enc_class Java_To_Interpreter(method meth) |
| 2090 %{ | |
| 2091 // CALL Java_To_Interpreter | |
| 2092 // This is the instruction starting address for relocation info. | |
| 1748 | 2093 cbuf.set_insts_mark(); |
| 0 | 2094 $$$emit8$primary; |
| 2095 // CALL directly to the runtime | |
| 2096 emit_d32_reloc(cbuf, | |
| 1748 | 2097 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2098 runtime_call_Relocation::spec(), |
| 2099 RELOC_DISP32); | |
| 2100 %} | |
| 2101 | |
| 2102 enc_class Java_Static_Call(method meth) | |
| 2103 %{ | |
| 2104 // JAVA STATIC CALL | |
| 2105 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2106 // determine who we intended to call. | |
| 1748 | 2107 cbuf.set_insts_mark(); |
| 0 | 2108 $$$emit8$primary; |
| 2109 | |
| 2110 if (!_method) { | |
| 2111 emit_d32_reloc(cbuf, | |
| 1748 | 2112 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2113 runtime_call_Relocation::spec(), |
| 2114 RELOC_DISP32); | |
| 2115 } else if (_optimized_virtual) { | |
| 2116 emit_d32_reloc(cbuf, | |
| 1748 | 2117 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2118 opt_virtual_call_Relocation::spec(), |
| 2119 RELOC_DISP32); | |
| 2120 } else { | |
| 2121 emit_d32_reloc(cbuf, | |
| 1748 | 2122 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2123 static_call_Relocation::spec(), |
| 2124 RELOC_DISP32); | |
| 2125 } | |
| 2126 if (_method) { | |
|
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2127 // Emit stub for static call. |
|
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2128 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); |
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2129 if (stub == NULL) { |
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2130 ciEnv::current()->record_failure("CodeCache is full"); |
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2131 return; |
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2132 } |
| 0 | 2133 } |
| 2134 %} | |
| 2135 | |
|
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2136 enc_class Java_Dynamic_Call(method meth) %{ |
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2137 MacroAssembler _masm(&cbuf); |
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2138 __ ic_call((address)$meth$$method); |
| 0 | 2139 %} |
| 2140 | |
| 2141 enc_class Java_Compiled_Call(method meth) | |
| 2142 %{ | |
| 2143 // JAVA COMPILED CALL | |
|
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2144 int disp = in_bytes(Method:: from_compiled_offset()); |
| 0 | 2145 |
| 2146 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2147 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2148 | |
| 2149 // callq *disp(%rax) | |
| 1748 | 2150 cbuf.set_insts_mark(); |
| 0 | 2151 $$$emit8$primary; |
| 2152 if (disp < 0x80) { | |
| 2153 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2154 emit_d8(cbuf, disp); // Displacement | |
| 2155 } else { | |
| 2156 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2157 emit_d32(cbuf, disp); // Displacement | |
| 2158 } | |
| 2159 %} | |
| 2160 | |
| 2161 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2162 %{ | |
| 2163 // SAL, SAR, SHR | |
| 2164 int dstenc = $dst$$reg; | |
| 2165 if (dstenc >= 8) { | |
| 2166 emit_opcode(cbuf, Assembler::REX_B); | |
| 2167 dstenc -= 8; | |
| 2168 } | |
| 2169 $$$emit8$primary; | |
| 2170 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2171 $$$emit8$shift$$constant; | |
| 2172 %} | |
| 2173 | |
| 2174 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2175 %{ | |
| 2176 // SAL, SAR, SHR | |
| 2177 int dstenc = $dst$$reg; | |
| 2178 if (dstenc < 8) { | |
| 2179 emit_opcode(cbuf, Assembler::REX_W); | |
| 2180 } else { | |
| 2181 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2182 dstenc -= 8; | |
| 2183 } | |
| 2184 $$$emit8$primary; | |
| 2185 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2186 $$$emit8$shift$$constant; | |
| 2187 %} | |
| 2188 | |
| 2189 enc_class load_immI(rRegI dst, immI src) | |
| 2190 %{ | |
| 2191 int dstenc = $dst$$reg; | |
| 2192 if (dstenc >= 8) { | |
| 2193 emit_opcode(cbuf, Assembler::REX_B); | |
| 2194 dstenc -= 8; | |
| 2195 } | |
| 2196 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2197 $$$emit32$src$$constant; | |
| 2198 %} | |
| 2199 | |
| 2200 enc_class load_immL(rRegL dst, immL src) | |
| 2201 %{ | |
| 2202 int dstenc = $dst$$reg; | |
| 2203 if (dstenc < 8) { | |
| 2204 emit_opcode(cbuf, Assembler::REX_W); | |
| 2205 } else { | |
| 2206 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2207 dstenc -= 8; | |
| 2208 } | |
| 2209 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2210 emit_d64(cbuf, $src$$constant); | |
| 2211 %} | |
| 2212 | |
| 2213 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2214 %{ | |
| 2215 // same as load_immI, but this time we care about zeroes in the high word | |
| 2216 int dstenc = $dst$$reg; | |
| 2217 if (dstenc >= 8) { | |
| 2218 emit_opcode(cbuf, Assembler::REX_B); | |
| 2219 dstenc -= 8; | |
| 2220 } | |
| 2221 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2222 $$$emit32$src$$constant; | |
| 2223 %} | |
| 2224 | |
| 2225 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2226 %{ | |
| 2227 int dstenc = $dst$$reg; | |
| 2228 if (dstenc < 8) { | |
| 2229 emit_opcode(cbuf, Assembler::REX_W); | |
| 2230 } else { | |
| 2231 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2232 dstenc -= 8; | |
| 2233 } | |
| 2234 emit_opcode(cbuf, 0xC7); | |
| 2235 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2236 $$$emit32$src$$constant; | |
| 2237 %} | |
| 2238 | |
| 2239 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2240 %{ | |
| 2241 // same as load_immI, but this time we care about zeroes in the high word | |
| 2242 int dstenc = $dst$$reg; | |
| 2243 if (dstenc >= 8) { | |
| 2244 emit_opcode(cbuf, Assembler::REX_B); | |
| 2245 dstenc -= 8; | |
| 2246 } | |
| 2247 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2248 $$$emit32$src$$constant; | |
| 2249 %} | |
| 2250 | |
| 2251 enc_class load_immP(rRegP dst, immP src) | |
| 2252 %{ | |
| 2253 int dstenc = $dst$$reg; | |
| 2254 if (dstenc < 8) { | |
| 2255 emit_opcode(cbuf, Assembler::REX_W); | |
| 2256 } else { | |
| 2257 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2258 dstenc -= 8; | |
| 2259 } | |
| 2260 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2261 // This next line should be generated from ADLC | |
|
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2262 if ($src->constant_reloc() != relocInfo::none) { |
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2263 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64); |
| 0 | 2264 } else { |
| 2265 emit_d64(cbuf, $src$$constant); | |
| 2266 } | |
| 2267 %} | |
| 2268 | |
| 2269 enc_class Con32(immI src) | |
| 2270 %{ | |
| 2271 // Output immediate | |
| 2272 $$$emit32$src$$constant; | |
| 2273 %} | |
| 2274 | |
| 2275 enc_class Con32F_as_bits(immF src) | |
| 2276 %{ | |
| 2277 // Output Float immediate bits | |
| 2278 jfloat jf = $src$$constant; | |
| 2279 jint jf_as_bits = jint_cast(jf); | |
| 2280 emit_d32(cbuf, jf_as_bits); | |
| 2281 %} | |
| 2282 | |
| 2283 enc_class Con16(immI src) | |
| 2284 %{ | |
| 2285 // Output immediate | |
| 2286 $$$emit16$src$$constant; | |
| 2287 %} | |
| 2288 | |
| 2289 // How is this different from Con32??? XXX | |
| 2290 enc_class Con_d32(immI src) | |
| 2291 %{ | |
| 2292 emit_d32(cbuf,$src$$constant); | |
| 2293 %} | |
| 2294 | |
| 2295 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2296 // Output immediate memory reference | |
| 2297 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2298 emit_d32(cbuf, 0x00); | |
| 2299 %} | |
| 2300 | |
| 2301 enc_class lock_prefix() | |
| 2302 %{ | |
| 2303 if (os::is_MP()) { | |
| 2304 emit_opcode(cbuf, 0xF0); // lock | |
| 2305 } | |
| 2306 %} | |
| 2307 | |
| 2308 enc_class REX_mem(memory mem) | |
| 2309 %{ | |
| 2310 if ($mem$$base >= 8) { | |
| 2311 if ($mem$$index < 8) { | |
| 2312 emit_opcode(cbuf, Assembler::REX_B); | |
| 2313 } else { | |
| 2314 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2315 } | |
| 2316 } else { | |
| 2317 if ($mem$$index >= 8) { | |
| 2318 emit_opcode(cbuf, Assembler::REX_X); | |
| 2319 } | |
| 2320 } | |
| 2321 %} | |
| 2322 | |
| 2323 enc_class REX_mem_wide(memory mem) | |
| 2324 %{ | |
| 2325 if ($mem$$base >= 8) { | |
| 2326 if ($mem$$index < 8) { | |
| 2327 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2328 } else { | |
| 2329 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2330 } | |
| 2331 } else { | |
| 2332 if ($mem$$index < 8) { | |
| 2333 emit_opcode(cbuf, Assembler::REX_W); | |
| 2334 } else { | |
| 2335 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2336 } | |
| 2337 } | |
| 2338 %} | |
| 2339 | |
| 2340 // for byte regs | |
| 2341 enc_class REX_breg(rRegI reg) | |
| 2342 %{ | |
| 2343 if ($reg$$reg >= 4) { | |
| 2344 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2345 } | |
| 2346 %} | |
| 2347 | |
| 2348 // for byte regs | |
| 2349 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 2350 %{ | |
| 2351 if ($dst$$reg < 8) { | |
| 2352 if ($src$$reg >= 4) { | |
| 2353 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2354 } | |
| 2355 } else { | |
| 2356 if ($src$$reg < 8) { | |
| 2357 emit_opcode(cbuf, Assembler::REX_R); | |
| 2358 } else { | |
| 2359 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2360 } | |
| 2361 } | |
| 2362 %} | |
| 2363 | |
| 2364 // for byte regs | |
| 2365 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 2366 %{ | |
| 2367 if ($reg$$reg < 8) { | |
| 2368 if ($mem$$base < 8) { | |
| 2369 if ($mem$$index >= 8) { | |
| 2370 emit_opcode(cbuf, Assembler::REX_X); | |
| 2371 } else if ($reg$$reg >= 4) { | |
| 2372 emit_opcode(cbuf, Assembler::REX); | |
| 2373 } | |
| 2374 } else { | |
| 2375 if ($mem$$index < 8) { | |
| 2376 emit_opcode(cbuf, Assembler::REX_B); | |
| 2377 } else { | |
| 2378 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2379 } | |
| 2380 } | |
| 2381 } else { | |
| 2382 if ($mem$$base < 8) { | |
| 2383 if ($mem$$index < 8) { | |
| 2384 emit_opcode(cbuf, Assembler::REX_R); | |
| 2385 } else { | |
| 2386 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2387 } | |
| 2388 } else { | |
| 2389 if ($mem$$index < 8) { | |
| 2390 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2391 } else { | |
| 2392 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2393 } | |
| 2394 } | |
| 2395 } | |
| 2396 %} | |
| 2397 | |
| 2398 enc_class REX_reg(rRegI reg) | |
| 2399 %{ | |
| 2400 if ($reg$$reg >= 8) { | |
| 2401 emit_opcode(cbuf, Assembler::REX_B); | |
| 2402 } | |
| 2403 %} | |
| 2404 | |
| 2405 enc_class REX_reg_wide(rRegI reg) | |
| 2406 %{ | |
| 2407 if ($reg$$reg < 8) { | |
| 2408 emit_opcode(cbuf, Assembler::REX_W); | |
| 2409 } else { | |
| 2410 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2411 } | |
| 2412 %} | |
| 2413 | |
| 2414 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 2415 %{ | |
| 2416 if ($dst$$reg < 8) { | |
| 2417 if ($src$$reg >= 8) { | |
| 2418 emit_opcode(cbuf, Assembler::REX_B); | |
| 2419 } | |
| 2420 } else { | |
| 2421 if ($src$$reg < 8) { | |
| 2422 emit_opcode(cbuf, Assembler::REX_R); | |
| 2423 } else { | |
| 2424 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2425 } | |
| 2426 } | |
| 2427 %} | |
| 2428 | |
| 2429 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 2430 %{ | |
| 2431 if ($dst$$reg < 8) { | |
| 2432 if ($src$$reg < 8) { | |
| 2433 emit_opcode(cbuf, Assembler::REX_W); | |
| 2434 } else { | |
| 2435 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2436 } | |
| 2437 } else { | |
| 2438 if ($src$$reg < 8) { | |
| 2439 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2440 } else { | |
| 2441 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2442 } | |
| 2443 } | |
| 2444 %} | |
| 2445 | |
| 2446 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 2447 %{ | |
| 2448 if ($reg$$reg < 8) { | |
| 2449 if ($mem$$base < 8) { | |
| 2450 if ($mem$$index >= 8) { | |
| 2451 emit_opcode(cbuf, Assembler::REX_X); | |
| 2452 } | |
| 2453 } else { | |
| 2454 if ($mem$$index < 8) { | |
| 2455 emit_opcode(cbuf, Assembler::REX_B); | |
| 2456 } else { | |
| 2457 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2458 } | |
| 2459 } | |
| 2460 } else { | |
| 2461 if ($mem$$base < 8) { | |
| 2462 if ($mem$$index < 8) { | |
| 2463 emit_opcode(cbuf, Assembler::REX_R); | |
| 2464 } else { | |
| 2465 emit_opcode(cbuf, Assembler::REX_RX); | |
| 2466 } | |
| 2467 } else { | |
| 2468 if ($mem$$index < 8) { | |
| 2469 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2470 } else { | |
| 2471 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 2472 } | |
| 2473 } | |
| 2474 } | |
| 2475 %} | |
| 2476 | |
| 2477 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 2478 %{ | |
| 2479 if ($reg$$reg < 8) { | |
| 2480 if ($mem$$base < 8) { | |
| 2481 if ($mem$$index < 8) { | |
| 2482 emit_opcode(cbuf, Assembler::REX_W); | |
| 2483 } else { | |
| 2484 emit_opcode(cbuf, Assembler::REX_WX); | |
| 2485 } | |
| 2486 } else { | |
| 2487 if ($mem$$index < 8) { | |
| 2488 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2489 } else { | |
| 2490 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 2491 } | |
| 2492 } | |
| 2493 } else { | |
| 2494 if ($mem$$base < 8) { | |
| 2495 if ($mem$$index < 8) { | |
| 2496 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2497 } else { | |
| 2498 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 2499 } | |
| 2500 } else { | |
| 2501 if ($mem$$index < 8) { | |
| 2502 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2503 } else { | |
| 2504 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 2505 } | |
| 2506 } | |
| 2507 } | |
| 2508 %} | |
| 2509 | |
| 2510 enc_class reg_mem(rRegI ereg, memory mem) | |
| 2511 %{ | |
| 2512 // High registers handle in encode_RegMem | |
| 2513 int reg = $ereg$$reg; | |
| 2514 int base = $mem$$base; | |
| 2515 int index = $mem$$index; | |
| 2516 int scale = $mem$$scale; | |
| 2517 int disp = $mem$$disp; | |
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2518 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2519 |
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2520 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc); |
| 0 | 2521 %} |
| 2522 | |
| 2523 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 2524 %{ | |
| 2525 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2526 | |
| 2527 // High registers handle in encode_RegMem | |
| 2528 int base = $mem$$base; | |
| 2529 int index = $mem$$index; | |
| 2530 int scale = $mem$$scale; | |
| 2531 int displace = $mem$$disp; | |
| 2532 | |
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2533 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when |
| 0 | 2534 // working with static |
| 2535 // globals | |
| 2536 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
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2537 disp_reloc); |
| 0 | 2538 %} |
| 2539 | |
| 2540 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 2541 %{ | |
| 2542 int reg_encoding = $dst$$reg; | |
| 2543 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2544 int index = 0x04; // 0x04 indicates no index | |
| 2545 int scale = 0x00; // 0x00 indicates no scale | |
| 2546 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2547 relocInfo::relocType disp_reloc = relocInfo::none; |
| 0 | 2548 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, |
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2549 disp_reloc); |
| 0 | 2550 %} |
| 2551 | |
| 2552 enc_class neg_reg(rRegI dst) | |
| 2553 %{ | |
| 2554 int dstenc = $dst$$reg; | |
| 2555 if (dstenc >= 8) { | |
| 2556 emit_opcode(cbuf, Assembler::REX_B); | |
| 2557 dstenc -= 8; | |
| 2558 } | |
| 2559 // NEG $dst | |
| 2560 emit_opcode(cbuf, 0xF7); | |
| 2561 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2562 %} | |
| 2563 | |
| 2564 enc_class neg_reg_wide(rRegI dst) | |
| 2565 %{ | |
| 2566 int dstenc = $dst$$reg; | |
| 2567 if (dstenc < 8) { | |
| 2568 emit_opcode(cbuf, Assembler::REX_W); | |
| 2569 } else { | |
| 2570 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2571 dstenc -= 8; | |
| 2572 } | |
| 2573 // NEG $dst | |
| 2574 emit_opcode(cbuf, 0xF7); | |
| 2575 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 2576 %} | |
| 2577 | |
| 2578 enc_class setLT_reg(rRegI dst) | |
| 2579 %{ | |
| 2580 int dstenc = $dst$$reg; | |
| 2581 if (dstenc >= 8) { | |
| 2582 emit_opcode(cbuf, Assembler::REX_B); | |
| 2583 dstenc -= 8; | |
| 2584 } else if (dstenc >= 4) { | |
| 2585 emit_opcode(cbuf, Assembler::REX); | |
| 2586 } | |
| 2587 // SETLT $dst | |
| 2588 emit_opcode(cbuf, 0x0F); | |
| 2589 emit_opcode(cbuf, 0x9C); | |
| 2590 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2591 %} | |
| 2592 | |
| 2593 enc_class setNZ_reg(rRegI dst) | |
| 2594 %{ | |
| 2595 int dstenc = $dst$$reg; | |
| 2596 if (dstenc >= 8) { | |
| 2597 emit_opcode(cbuf, Assembler::REX_B); | |
| 2598 dstenc -= 8; | |
| 2599 } else if (dstenc >= 4) { | |
| 2600 emit_opcode(cbuf, Assembler::REX); | |
| 2601 } | |
| 2602 // SETNZ $dst | |
| 2603 emit_opcode(cbuf, 0x0F); | |
| 2604 emit_opcode(cbuf, 0x95); | |
| 2605 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 2606 %} | |
| 2607 | |
| 2608 | |
| 2609 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 2610 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 2611 %{ | |
| 2612 int src1enc = $src1$$reg; | |
| 2613 int src2enc = $src2$$reg; | |
| 2614 int dstenc = $dst$$reg; | |
| 2615 | |
| 2616 // cmpq $src1, $src2 | |
| 2617 if (src1enc < 8) { | |
| 2618 if (src2enc < 8) { | |
| 2619 emit_opcode(cbuf, Assembler::REX_W); | |
| 2620 } else { | |
| 2621 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2622 } | |
| 2623 } else { | |
| 2624 if (src2enc < 8) { | |
| 2625 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2626 } else { | |
| 2627 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2628 } | |
| 2629 } | |
| 2630 emit_opcode(cbuf, 0x3B); | |
| 2631 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 2632 | |
| 2633 // movl $dst, -1 | |
| 2634 if (dstenc >= 8) { | |
| 2635 emit_opcode(cbuf, Assembler::REX_B); | |
| 2636 } | |
| 2637 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2638 emit_d32(cbuf, -1); | |
| 2639 | |
| 2640 // jl,s done | |
| 2641 emit_opcode(cbuf, 0x7C); | |
| 2642 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2643 | |
| 2644 // setne $dst | |
| 2645 if (dstenc >= 4) { | |
| 2646 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2647 } | |
| 2648 emit_opcode(cbuf, 0x0F); | |
| 2649 emit_opcode(cbuf, 0x95); | |
| 2650 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2651 | |
| 2652 // movzbl $dst, $dst | |
| 2653 if (dstenc >= 4) { | |
| 2654 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2655 } | |
| 2656 emit_opcode(cbuf, 0x0F); | |
| 2657 emit_opcode(cbuf, 0xB6); | |
| 2658 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2659 %} | |
| 2660 | |
| 2661 enc_class Push_ResultXD(regD dst) %{ | |
| 4759 | 2662 MacroAssembler _masm(&cbuf); |
| 2663 __ fstp_d(Address(rsp, 0)); | |
| 2664 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2665 __ addptr(rsp, 8); | |
| 0 | 2666 %} |
| 2667 | |
| 2668 enc_class Push_SrcXD(regD src) %{ | |
| 2669 MacroAssembler _masm(&cbuf); | |
| 4759 | 2670 __ subptr(rsp, 8); |
| 2671 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2672 __ fld_d(Address(rsp, 0)); | |
| 2673 %} | |
| 2674 | |
| 0 | 2675 |
| 2676 enc_class enc_rethrow() | |
| 2677 %{ | |
| 1748 | 2678 cbuf.set_insts_mark(); |
| 0 | 2679 emit_opcode(cbuf, 0xE9); // jmp entry |
| 2680 emit_d32_reloc(cbuf, | |
| 1748 | 2681 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 2682 runtime_call_Relocation::spec(), |
| 2683 RELOC_DISP32); | |
| 2684 %} | |
| 2685 | |
| 2686 %} | |
| 2687 | |
| 2688 | |
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2689 |
| 0 | 2690 //----------FRAME-------------------------------------------------------------- |
| 2691 // Definition of frame structure and management information. | |
| 2692 // | |
| 2693 // S T A C K L A Y O U T Allocators stack-slot number | |
| 2694 // | (to get allocators register number | |
| 2695 // G Owned by | | v add OptoReg::stack0()) | |
| 2696 // r CALLER | | | |
| 2697 // o | +--------+ pad to even-align allocators stack-slot | |
| 2698 // w V | pad0 | numbers; owned by CALLER | |
| 2699 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 2700 // h ^ | in | 5 | |
| 2701 // | | args | 4 Holes in incoming args owned by SELF | |
| 2702 // | | | | 3 | |
| 2703 // | | +--------+ | |
| 2704 // V | | old out| Empty on Intel, window on Sparc | |
| 2705 // | old |preserve| Must be even aligned. | |
| 2706 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 2707 // | | in | 3 area for Intel ret address | |
| 2708 // Owned by |preserve| Empty on Sparc. | |
| 2709 // SELF +--------+ | |
| 2710 // | | pad2 | 2 pad to align old SP | |
| 2711 // | +--------+ 1 | |
| 2712 // | | locks | 0 | |
| 2713 // | +--------+----> OptoReg::stack0(), even aligned | |
| 2714 // | | pad1 | 11 pad to align new SP | |
| 2715 // | +--------+ | |
| 2716 // | | | 10 | |
| 2717 // | | spills | 9 spills | |
| 2718 // V | | 8 (pad0 slot for callee) | |
| 2719 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 2720 // ^ | out | 7 | |
| 2721 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 2722 // Owned by +--------+ | |
| 2723 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 2724 // | new |preserve| Must be even-aligned. | |
| 2725 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 2726 // | | | | |
| 2727 // | |
| 2728 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 2729 // known from SELF's arguments and the Java calling convention. | |
| 2730 // Region 6-7 is determined per call site. | |
| 2731 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 2732 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 2733 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 2734 // incoming area, as the Java calling convention is completely under | |
| 2735 // the control of the AD file. Doubles can be sorted and packed to | |
| 2736 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 2737 // varargs C calling conventions. | |
| 2738 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 2739 // even aligned with pad0 as needed. | |
| 2740 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 2741 // region 6-11 is even aligned; it may be padded out more so that | |
| 2742 // the region from SP to FP meets the minimum stack alignment. | |
| 2743 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 2744 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 2745 // SP meets the minimum alignment. | |
| 2746 | |
| 2747 frame | |
| 2748 %{ | |
| 2749 // What direction does stack grow in (assumed to be same for C & Java) | |
| 2750 stack_direction(TOWARDS_LOW); | |
| 2751 | |
| 2752 // These three registers define part of the calling convention | |
| 2753 // between compiled code and the interpreter. | |
| 2754 inline_cache_reg(RAX); // Inline Cache Register | |
| 2755 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 2756 // calling interpreter | |
| 2757 | |
| 2758 // Optional: name the operand used by cisc-spilling to access | |
| 2759 // [stack_pointer + offset] | |
| 2760 cisc_spilling_operand_name(indOffset32); | |
| 2761 | |
| 2762 // Number of stack slots consumed by locking an object | |
| 2763 sync_stack_slots(2); | |
| 2764 | |
| 2765 // Compiled code's Frame Pointer | |
| 2766 frame_pointer(RSP); | |
| 2767 | |
| 2768 // Interpreter stores its frame pointer in a register which is | |
| 2769 // stored to the stack by I2CAdaptors. | |
| 2770 // I2CAdaptors convert from interpreted java to compiled java. | |
| 2771 interpreter_frame_pointer(RBP); | |
| 2772 | |
| 2773 // Stack alignment requirement | |
| 2774 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 2775 | |
| 2776 // Number of stack slots between incoming argument block and the start of | |
| 2777 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 2778 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 2779 // return address. | |
| 2780 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 2781 | |
| 2782 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 2783 // for calls to C. Supports the var-args backing area for register parms. | |
| 2784 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 2785 | |
| 2786 // The after-PROLOG location of the return address. Location of | |
| 2787 // return address specifies a type (REG or STACK) and a number | |
| 2788 // representing the register number (i.e. - use a register name) or | |
| 2789 // stack slot. | |
| 2790 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 2791 // Otherwise, it is above the locks and verification slot and alignment word | |
| 2792 return_addr(STACK - 2 + | |
| 4950 | 2793 round_to((Compile::current()->in_preserve_stack_slots() + |
| 2794 Compile::current()->fixed_slots()), | |
| 2795 stack_alignment_in_slots())); | |
| 0 | 2796 |
| 2797 // Body of function which returns an integer array locating | |
| 2798 // arguments either in registers or in stack slots. Passed an array | |
| 2799 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 2800 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 2801 // arguments for a CALLEE. Incoming stack arguments are | |
| 2802 // automatically biased by the preserve_stack_slots field above. | |
| 2803 | |
| 2804 calling_convention | |
| 2805 %{ | |
| 2806 // No difference between ingoing/outgoing just pass false | |
| 2807 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 2808 %} | |
| 2809 | |
| 2810 c_calling_convention | |
| 2811 %{ | |
| 2812 // This is obviously always outgoing | |
|
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2813 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 2814 %} |
| 2815 | |
| 2816 // Location of compiled Java return values. Same as C for now. | |
| 2817 return_value | |
| 2818 %{ | |
| 2819 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 2820 "only return normal values"); | |
| 2821 | |
| 2822 static const int lo[Op_RegL + 1] = { | |
| 2823 0, | |
| 2824 0, | |
|
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2825 RAX_num, // Op_RegN |
| 0 | 2826 RAX_num, // Op_RegI |
| 2827 RAX_num, // Op_RegP | |
| 2828 XMM0_num, // Op_RegF | |
| 2829 XMM0_num, // Op_RegD | |
| 2830 RAX_num // Op_RegL | |
| 2831 }; | |
| 2832 static const int hi[Op_RegL + 1] = { | |
| 2833 0, | |
| 2834 0, | |
|
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2835 OptoReg::Bad, // Op_RegN |
| 0 | 2836 OptoReg::Bad, // Op_RegI |
| 2837 RAX_H_num, // Op_RegP | |
| 2838 OptoReg::Bad, // Op_RegF | |
|
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2839 XMM0b_num, // Op_RegD |
| 0 | 2840 RAX_H_num // Op_RegL |
| 2841 }; | |
|
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2842 // Excluded flags and vector registers. |
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2843 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type"); |
| 0 | 2844 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 2845 %} | |
| 2846 %} | |
| 2847 | |
| 2848 //----------ATTRIBUTES--------------------------------------------------------- | |
| 2849 //----------Operand Attributes------------------------------------------------- | |
| 2850 op_attrib op_cost(0); // Required cost attribute | |
| 2851 | |
| 2852 //----------Instruction Attributes--------------------------------------------- | |
| 2853 ins_attrib ins_cost(100); // Required cost attribute | |
| 2854 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 2855 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 2856 // a non-matching short branch variant | |
| 2857 // of some long branch? | |
| 2858 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 2859 // be a power of 2) specifies the | |
| 2860 // alignment that some part of the | |
| 2861 // instruction (not necessarily the | |
| 2862 // start) requires. If > 1, a | |
| 2863 // compute_padding() function must be | |
| 2864 // provided for the instruction | |
| 2865 | |
| 2866 //----------OPERANDS----------------------------------------------------------- | |
| 2867 // Operand definitions must precede instruction definitions for correct parsing | |
| 2868 // in the ADLC because operands constitute user defined types which are used in | |
| 2869 // instruction definitions. | |
| 2870 | |
| 2871 //----------Simple Operands---------------------------------------------------- | |
| 2872 // Immediate Operands | |
| 2873 // Integer Immediate | |
| 2874 operand immI() | |
| 2875 %{ | |
| 2876 match(ConI); | |
| 2877 | |
| 2878 op_cost(10); | |
| 2879 format %{ %} | |
| 2880 interface(CONST_INTER); | |
| 2881 %} | |
| 2882 | |
| 2883 // Constant for test vs zero | |
| 2884 operand immI0() | |
| 2885 %{ | |
| 2886 predicate(n->get_int() == 0); | |
| 2887 match(ConI); | |
| 2888 | |
| 2889 op_cost(0); | |
| 2890 format %{ %} | |
| 2891 interface(CONST_INTER); | |
| 2892 %} | |
| 2893 | |
| 2894 // Constant for increment | |
| 2895 operand immI1() | |
| 2896 %{ | |
| 2897 predicate(n->get_int() == 1); | |
| 2898 match(ConI); | |
| 2899 | |
| 2900 op_cost(0); | |
| 2901 format %{ %} | |
| 2902 interface(CONST_INTER); | |
| 2903 %} | |
| 2904 | |
| 2905 // Constant for decrement | |
| 2906 operand immI_M1() | |
| 2907 %{ | |
| 2908 predicate(n->get_int() == -1); | |
| 2909 match(ConI); | |
| 2910 | |
| 2911 op_cost(0); | |
| 2912 format %{ %} | |
| 2913 interface(CONST_INTER); | |
| 2914 %} | |
| 2915 | |
| 2916 // Valid scale values for addressing modes | |
| 2917 operand immI2() | |
| 2918 %{ | |
| 2919 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 2920 match(ConI); | |
| 2921 | |
| 2922 format %{ %} | |
| 2923 interface(CONST_INTER); | |
| 2924 %} | |
| 2925 | |
| 2926 operand immI8() | |
| 2927 %{ | |
| 2928 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 2929 match(ConI); | |
| 2930 | |
| 2931 op_cost(5); | |
| 2932 format %{ %} | |
| 2933 interface(CONST_INTER); | |
| 2934 %} | |
| 2935 | |
| 2936 operand immI16() | |
| 2937 %{ | |
| 2938 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 2939 match(ConI); | |
| 2940 | |
| 2941 op_cost(10); | |
| 2942 format %{ %} | |
| 2943 interface(CONST_INTER); | |
| 2944 %} | |
| 2945 | |
|
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2946 // Int Immediate non-negative |
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2947 operand immU31() |
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2948 %{ |
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2949 predicate(n->get_int() >= 0); |
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2950 match(ConI); |
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2951 |
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2952 op_cost(0); |
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2953 format %{ %} |
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2954 interface(CONST_INTER); |
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2955 %} |
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2956 |
| 0 | 2957 // Constant for long shifts |
| 2958 operand immI_32() | |
| 2959 %{ | |
| 2960 predicate( n->get_int() == 32 ); | |
| 2961 match(ConI); | |
| 2962 | |
| 2963 op_cost(0); | |
| 2964 format %{ %} | |
| 2965 interface(CONST_INTER); | |
| 2966 %} | |
| 2967 | |
| 2968 // Constant for long shifts | |
| 2969 operand immI_64() | |
| 2970 %{ | |
| 2971 predicate( n->get_int() == 64 ); | |
| 2972 match(ConI); | |
| 2973 | |
| 2974 op_cost(0); | |
| 2975 format %{ %} | |
| 2976 interface(CONST_INTER); | |
| 2977 %} | |
| 2978 | |
| 2979 // Pointer Immediate | |
| 2980 operand immP() | |
| 2981 %{ | |
| 2982 match(ConP); | |
| 2983 | |
| 2984 op_cost(10); | |
| 2985 format %{ %} | |
| 2986 interface(CONST_INTER); | |
| 2987 %} | |
| 2988 | |
| 2989 // NULL Pointer Immediate | |
| 2990 operand immP0() | |
| 2991 %{ | |
| 2992 predicate(n->get_ptr() == 0); | |
| 2993 match(ConP); | |
| 2994 | |
| 2995 op_cost(5); | |
| 2996 format %{ %} | |
| 2997 interface(CONST_INTER); | |
| 2998 %} | |
| 2999 | |
|
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3000 // Pointer Immediate |
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3001 operand immN() %{ |
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3002 match(ConN); |
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3003 |
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3004 op_cost(10); |
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3005 format %{ %} |
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3006 interface(CONST_INTER); |
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3007 %} |
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3008 |
|
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3009 operand immNKlass() %{ |
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3010 match(ConNKlass); |
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3011 |
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3012 op_cost(10); |
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3013 format %{ %} |
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3014 interface(CONST_INTER); |
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3015 %} |
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3016 |
|
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3017 // NULL Pointer Immediate |
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3018 operand immN0() %{ |
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3019 predicate(n->get_narrowcon() == 0); |
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3020 match(ConN); |
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3021 |
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3022 op_cost(5); |
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3023 format %{ %} |
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3024 interface(CONST_INTER); |
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3025 %} |
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3026 |
| 0 | 3027 operand immP31() |
| 3028 %{ | |
|
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3029 predicate(n->as_Type()->type()->reloc() == relocInfo::none |
| 0 | 3030 && (n->get_ptr() >> 31) == 0); |
| 3031 match(ConP); | |
| 3032 | |
| 3033 op_cost(5); | |
| 3034 format %{ %} | |
| 3035 interface(CONST_INTER); | |
| 3036 %} | |
| 3037 | |
|
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3038 |
| 0 | 3039 // Long Immediate |
| 3040 operand immL() | |
| 3041 %{ | |
| 3042 match(ConL); | |
| 3043 | |
| 3044 op_cost(20); | |
| 3045 format %{ %} | |
| 3046 interface(CONST_INTER); | |
| 3047 %} | |
| 3048 | |
| 3049 // Long Immediate 8-bit | |
| 3050 operand immL8() | |
| 3051 %{ | |
| 3052 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 3053 match(ConL); | |
| 3054 | |
| 3055 op_cost(5); | |
| 3056 format %{ %} | |
| 3057 interface(CONST_INTER); | |
| 3058 %} | |
| 3059 | |
| 3060 // Long Immediate 32-bit unsigned | |
| 3061 operand immUL32() | |
| 3062 %{ | |
| 3063 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 3064 match(ConL); | |
| 3065 | |
| 3066 op_cost(10); | |
| 3067 format %{ %} | |
| 3068 interface(CONST_INTER); | |
| 3069 %} | |
| 3070 | |
| 3071 // Long Immediate 32-bit signed | |
| 3072 operand immL32() | |
| 3073 %{ | |
| 3074 predicate(n->get_long() == (int) (n->get_long())); | |
| 3075 match(ConL); | |
| 3076 | |
| 3077 op_cost(15); | |
| 3078 format %{ %} | |
| 3079 interface(CONST_INTER); | |
| 3080 %} | |
| 3081 | |
| 3082 // Long Immediate zero | |
| 3083 operand immL0() | |
| 3084 %{ | |
| 3085 predicate(n->get_long() == 0L); | |
| 3086 match(ConL); | |
| 3087 | |
| 3088 op_cost(10); | |
| 3089 format %{ %} | |
| 3090 interface(CONST_INTER); | |
| 3091 %} | |
| 3092 | |
| 3093 // Constant for increment | |
| 3094 operand immL1() | |
| 3095 %{ | |
| 3096 predicate(n->get_long() == 1); | |
| 3097 match(ConL); | |
| 3098 | |
| 3099 format %{ %} | |
| 3100 interface(CONST_INTER); | |
| 3101 %} | |
| 3102 | |
| 3103 // Constant for decrement | |
| 3104 operand immL_M1() | |
| 3105 %{ | |
| 3106 predicate(n->get_long() == -1); | |
| 3107 match(ConL); | |
| 3108 | |
| 3109 format %{ %} | |
| 3110 interface(CONST_INTER); | |
| 3111 %} | |
| 3112 | |
| 3113 // Long Immediate: the value 10 | |
| 3114 operand immL10() | |
| 3115 %{ | |
| 3116 predicate(n->get_long() == 10); | |
| 3117 match(ConL); | |
| 3118 | |
| 3119 format %{ %} | |
| 3120 interface(CONST_INTER); | |
| 3121 %} | |
| 3122 | |
| 3123 // Long immediate from 0 to 127. | |
| 3124 // Used for a shorter form of long mul by 10. | |
| 3125 operand immL_127() | |
| 3126 %{ | |
| 3127 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 3128 match(ConL); | |
| 3129 | |
| 3130 op_cost(10); | |
| 3131 format %{ %} | |
| 3132 interface(CONST_INTER); | |
| 3133 %} | |
| 3134 | |
| 3135 // Long Immediate: low 32-bit mask | |
| 3136 operand immL_32bits() | |
| 3137 %{ | |
| 3138 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3139 match(ConL); | |
| 3140 op_cost(20); | |
| 3141 | |
| 3142 format %{ %} | |
| 3143 interface(CONST_INTER); | |
| 3144 %} | |
| 3145 | |
| 3146 // Float Immediate zero | |
| 3147 operand immF0() | |
| 3148 %{ | |
| 3149 predicate(jint_cast(n->getf()) == 0); | |
| 3150 match(ConF); | |
| 3151 | |
| 3152 op_cost(5); | |
| 3153 format %{ %} | |
| 3154 interface(CONST_INTER); | |
| 3155 %} | |
| 3156 | |
| 3157 // Float Immediate | |
| 3158 operand immF() | |
| 3159 %{ | |
| 3160 match(ConF); | |
| 3161 | |
| 3162 op_cost(15); | |
| 3163 format %{ %} | |
| 3164 interface(CONST_INTER); | |
| 3165 %} | |
| 3166 | |
| 3167 // Double Immediate zero | |
| 3168 operand immD0() | |
| 3169 %{ | |
| 3170 predicate(jlong_cast(n->getd()) == 0); | |
| 3171 match(ConD); | |
| 3172 | |
| 3173 op_cost(5); | |
| 3174 format %{ %} | |
| 3175 interface(CONST_INTER); | |
| 3176 %} | |
| 3177 | |
| 3178 // Double Immediate | |
| 3179 operand immD() | |
| 3180 %{ | |
| 3181 match(ConD); | |
| 3182 | |
| 3183 op_cost(15); | |
| 3184 format %{ %} | |
| 3185 interface(CONST_INTER); | |
| 3186 %} | |
| 3187 | |
| 3188 // Immediates for special shifts (sign extend) | |
| 3189 | |
| 3190 // Constants for increment | |
| 3191 operand immI_16() | |
| 3192 %{ | |
| 3193 predicate(n->get_int() == 16); | |
| 3194 match(ConI); | |
| 3195 | |
| 3196 format %{ %} | |
| 3197 interface(CONST_INTER); | |
| 3198 %} | |
| 3199 | |
| 3200 operand immI_24() | |
| 3201 %{ | |
| 3202 predicate(n->get_int() == 24); | |
| 3203 match(ConI); | |
| 3204 | |
| 3205 format %{ %} | |
| 3206 interface(CONST_INTER); | |
| 3207 %} | |
| 3208 | |
| 3209 // Constant for byte-wide masking | |
| 3210 operand immI_255() | |
| 3211 %{ | |
| 3212 predicate(n->get_int() == 255); | |
| 3213 match(ConI); | |
| 3214 | |
| 3215 format %{ %} | |
| 3216 interface(CONST_INTER); | |
| 3217 %} | |
| 3218 | |
| 3219 // Constant for short-wide masking | |
| 3220 operand immI_65535() | |
| 3221 %{ | |
| 3222 predicate(n->get_int() == 65535); | |
| 3223 match(ConI); | |
| 3224 | |
| 3225 format %{ %} | |
| 3226 interface(CONST_INTER); | |
| 3227 %} | |
| 3228 | |
| 3229 // Constant for byte-wide masking | |
| 3230 operand immL_255() | |
| 3231 %{ | |
| 3232 predicate(n->get_long() == 255); | |
| 3233 match(ConL); | |
| 3234 | |
| 3235 format %{ %} | |
| 3236 interface(CONST_INTER); | |
| 3237 %} | |
| 3238 | |
| 3239 // Constant for short-wide masking | |
| 3240 operand immL_65535() | |
| 3241 %{ | |
| 3242 predicate(n->get_long() == 65535); | |
| 3243 match(ConL); | |
| 3244 | |
| 3245 format %{ %} | |
| 3246 interface(CONST_INTER); | |
| 3247 %} | |
| 3248 | |
| 3249 // Register Operands | |
| 3250 // Integer Register | |
| 3251 operand rRegI() | |
| 3252 %{ | |
| 3253 constraint(ALLOC_IN_RC(int_reg)); | |
| 3254 match(RegI); | |
| 3255 | |
| 3256 match(rax_RegI); | |
| 3257 match(rbx_RegI); | |
| 3258 match(rcx_RegI); | |
| 3259 match(rdx_RegI); | |
| 3260 match(rdi_RegI); | |
| 3261 | |
| 3262 format %{ %} | |
| 3263 interface(REG_INTER); | |
| 3264 %} | |
| 3265 | |
| 3266 // Special Registers | |
| 3267 operand rax_RegI() | |
| 3268 %{ | |
| 3269 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 3270 match(RegI); | |
| 3271 match(rRegI); | |
| 3272 | |
| 3273 format %{ "RAX" %} | |
| 3274 interface(REG_INTER); | |
| 3275 %} | |
| 3276 | |
| 3277 // Special Registers | |
| 3278 operand rbx_RegI() | |
| 3279 %{ | |
| 3280 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 3281 match(RegI); | |
| 3282 match(rRegI); | |
| 3283 | |
| 3284 format %{ "RBX" %} | |
| 3285 interface(REG_INTER); | |
| 3286 %} | |
| 3287 | |
| 3288 operand rcx_RegI() | |
| 3289 %{ | |
| 3290 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 3291 match(RegI); | |
| 3292 match(rRegI); | |
| 3293 | |
| 3294 format %{ "RCX" %} | |
| 3295 interface(REG_INTER); | |
| 3296 %} | |
| 3297 | |
| 3298 operand rdx_RegI() | |
| 3299 %{ | |
| 3300 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 3301 match(RegI); | |
| 3302 match(rRegI); | |
| 3303 | |
| 3304 format %{ "RDX" %} | |
| 3305 interface(REG_INTER); | |
| 3306 %} | |
| 3307 | |
| 3308 operand rdi_RegI() | |
| 3309 %{ | |
| 3310 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 3311 match(RegI); | |
| 3312 match(rRegI); | |
| 3313 | |
| 3314 format %{ "RDI" %} | |
| 3315 interface(REG_INTER); | |
| 3316 %} | |
| 3317 | |
| 3318 operand no_rcx_RegI() | |
| 3319 %{ | |
| 3320 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 3321 match(RegI); | |
| 3322 match(rax_RegI); | |
| 3323 match(rbx_RegI); | |
| 3324 match(rdx_RegI); | |
| 3325 match(rdi_RegI); | |
| 3326 | |
| 3327 format %{ %} | |
| 3328 interface(REG_INTER); | |
| 3329 %} | |
| 3330 | |
| 3331 operand no_rax_rdx_RegI() | |
| 3332 %{ | |
| 3333 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 3334 match(RegI); | |
| 3335 match(rbx_RegI); | |
| 3336 match(rcx_RegI); | |
| 3337 match(rdi_RegI); | |
| 3338 | |
| 3339 format %{ %} | |
| 3340 interface(REG_INTER); | |
| 3341 %} | |
| 3342 | |
| 3343 // Pointer Register | |
| 3344 operand any_RegP() | |
| 3345 %{ | |
|
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3346 constraint(ALLOC_IN_RC(any_reg)); |
| 0 | 3347 match(RegP); |
| 3348 match(rax_RegP); | |
| 3349 match(rbx_RegP); | |
| 3350 match(rdi_RegP); | |
| 3351 match(rsi_RegP); | |
| 3352 match(rbp_RegP); | |
| 3353 match(r15_RegP); | |
| 3354 match(rRegP); | |
| 3355 | |
| 3356 format %{ %} | |
| 3357 interface(REG_INTER); | |
| 3358 %} | |
| 3359 | |
| 3360 operand rRegP() | |
| 3361 %{ | |
| 3362 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3363 match(RegP); | |
| 3364 match(rax_RegP); | |
| 3365 match(rbx_RegP); | |
| 3366 match(rdi_RegP); | |
| 3367 match(rsi_RegP); | |
|
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|
3368 match(rbp_RegP); // See Q&A below about |
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|
3369 match(r15_RegP); // r15_RegP and rbp_RegP. |
| 0 | 3370 |
| 3371 format %{ %} | |
| 3372 interface(REG_INTER); | |
| 3373 %} | |
| 3374 | |
|
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3375 operand rRegN() %{ |
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3376 constraint(ALLOC_IN_RC(int_reg)); |
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3377 match(RegN); |
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3378 |
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3379 format %{ %} |
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3380 interface(REG_INTER); |
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3381 %} |
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|
3382 |
| 0 | 3383 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 3384 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
|
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3385 // It's fine for an instruction input that expects rRegP to match a r15_RegP. |
| 0 | 3386 // The output of an instruction is controlled by the allocator, which respects |
| 3387 // register class masks, not match rules. Unless an instruction mentions | |
| 3388 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 3389 // by the allocator as an input. | |
|
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3390 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true, |
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3391 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a |
|
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|
3392 // result, RBP is not included in the output of the instruction either. |
| 0 | 3393 |
| 3394 operand no_rax_RegP() | |
| 3395 %{ | |
| 3396 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 3397 match(RegP); | |
| 3398 match(rbx_RegP); | |
| 3399 match(rsi_RegP); | |
| 3400 match(rdi_RegP); | |
| 3401 | |
| 3402 format %{ %} | |
| 3403 interface(REG_INTER); | |
| 3404 %} | |
| 3405 | |
|
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3406 // This operand is not allowed to use RBP even if |
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|
3407 // RBP is not used to hold the frame pointer. |
| 0 | 3408 operand no_rbp_RegP() |
| 3409 %{ | |
|
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|
3410 constraint(ALLOC_IN_RC(ptr_reg_no_rbp)); |
| 0 | 3411 match(RegP); |
| 3412 match(rbx_RegP); | |
| 3413 match(rsi_RegP); | |
| 3414 match(rdi_RegP); | |
| 3415 | |
| 3416 format %{ %} | |
| 3417 interface(REG_INTER); | |
| 3418 %} | |
| 3419 | |
| 3420 operand no_rax_rbx_RegP() | |
| 3421 %{ | |
| 3422 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 3423 match(RegP); | |
| 3424 match(rsi_RegP); | |
| 3425 match(rdi_RegP); | |
| 3426 | |
| 3427 format %{ %} | |
| 3428 interface(REG_INTER); | |
| 3429 %} | |
| 3430 | |
| 3431 // Special Registers | |
| 3432 // Return a pointer value | |
| 3433 operand rax_RegP() | |
| 3434 %{ | |
| 3435 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 3436 match(RegP); | |
| 3437 match(rRegP); | |
| 3438 | |
| 3439 format %{ %} | |
| 3440 interface(REG_INTER); | |
| 3441 %} | |
| 3442 | |
|
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3443 // Special Registers |
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3444 // Return a compressed pointer value |
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3445 operand rax_RegN() |
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3446 %{ |
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3447 constraint(ALLOC_IN_RC(int_rax_reg)); |
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3448 match(RegN); |
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3449 match(rRegN); |
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|
3450 |
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|
3451 format %{ %} |
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3452 interface(REG_INTER); |
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3453 %} |
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|
3454 |
| 0 | 3455 // Used in AtomicAdd |
| 3456 operand rbx_RegP() | |
| 3457 %{ | |
| 3458 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 3459 match(RegP); | |
| 3460 match(rRegP); | |
| 3461 | |
| 3462 format %{ %} | |
| 3463 interface(REG_INTER); | |
| 3464 %} | |
| 3465 | |
| 3466 operand rsi_RegP() | |
| 3467 %{ | |
| 3468 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 3469 match(RegP); | |
| 3470 match(rRegP); | |
| 3471 | |
| 3472 format %{ %} | |
| 3473 interface(REG_INTER); | |
| 3474 %} | |
| 3475 | |
| 3476 // Used in rep stosq | |
| 3477 operand rdi_RegP() | |
| 3478 %{ | |
| 3479 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 3480 match(RegP); | |
| 3481 match(rRegP); | |
| 3482 | |
| 3483 format %{ %} | |
| 3484 interface(REG_INTER); | |
| 3485 %} | |
| 3486 | |
| 3487 operand r15_RegP() | |
| 3488 %{ | |
| 3489 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 3490 match(RegP); | |
| 3491 match(rRegP); | |
| 3492 | |
| 3493 format %{ %} | |
| 3494 interface(REG_INTER); | |
| 3495 %} | |
| 3496 | |
| 3497 operand rRegL() | |
| 3498 %{ | |
| 3499 constraint(ALLOC_IN_RC(long_reg)); | |
| 3500 match(RegL); | |
| 3501 match(rax_RegL); | |
| 3502 match(rdx_RegL); | |
| 3503 | |
| 3504 format %{ %} | |
| 3505 interface(REG_INTER); | |
| 3506 %} | |
| 3507 | |
| 3508 // Special Registers | |
| 3509 operand no_rax_rdx_RegL() | |
| 3510 %{ | |
| 3511 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3512 match(RegL); | |
| 3513 match(rRegL); | |
| 3514 | |
| 3515 format %{ %} | |
| 3516 interface(REG_INTER); | |
| 3517 %} | |
| 3518 | |
| 3519 operand no_rax_RegL() | |
| 3520 %{ | |
| 3521 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 3522 match(RegL); | |
| 3523 match(rRegL); | |
| 3524 match(rdx_RegL); | |
| 3525 | |
| 3526 format %{ %} | |
| 3527 interface(REG_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 operand no_rcx_RegL() | |
| 3531 %{ | |
| 3532 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 3533 match(RegL); | |
| 3534 match(rRegL); | |
| 3535 | |
| 3536 format %{ %} | |
| 3537 interface(REG_INTER); | |
| 3538 %} | |
| 3539 | |
| 3540 operand rax_RegL() | |
| 3541 %{ | |
| 3542 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 3543 match(RegL); | |
| 3544 match(rRegL); | |
| 3545 | |
| 3546 format %{ "RAX" %} | |
| 3547 interface(REG_INTER); | |
| 3548 %} | |
| 3549 | |
| 3550 operand rcx_RegL() | |
| 3551 %{ | |
| 3552 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 3553 match(RegL); | |
| 3554 match(rRegL); | |
| 3555 | |
| 3556 format %{ %} | |
| 3557 interface(REG_INTER); | |
| 3558 %} | |
| 3559 | |
| 3560 operand rdx_RegL() | |
| 3561 %{ | |
| 3562 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 3563 match(RegL); | |
| 3564 match(rRegL); | |
| 3565 | |
| 3566 format %{ %} | |
| 3567 interface(REG_INTER); | |
| 3568 %} | |
| 3569 | |
| 3570 // Flags register, used as output of compare instructions | |
| 3571 operand rFlagsReg() | |
| 3572 %{ | |
| 3573 constraint(ALLOC_IN_RC(int_flags)); | |
| 3574 match(RegFlags); | |
| 3575 | |
| 3576 format %{ "RFLAGS" %} | |
| 3577 interface(REG_INTER); | |
| 3578 %} | |
| 3579 | |
| 3580 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3581 operand rFlagsRegU() | |
| 3582 %{ | |
| 3583 constraint(ALLOC_IN_RC(int_flags)); | |
| 3584 match(RegFlags); | |
| 3585 | |
| 3586 format %{ "RFLAGS_U" %} | |
| 3587 interface(REG_INTER); | |
| 3588 %} | |
| 3589 | |
|
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3590 operand rFlagsRegUCF() %{ |
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3591 constraint(ALLOC_IN_RC(int_flags)); |
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3592 match(RegFlags); |
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|
3593 predicate(false); |
|
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|
3594 |
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|
3595 format %{ "RFLAGS_U_CF" %} |
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3596 interface(REG_INTER); |
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|
3597 %} |
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|
3598 |
| 0 | 3599 // Float register operands |
| 3600 operand regF() | |
| 3601 %{ | |
| 3602 constraint(ALLOC_IN_RC(float_reg)); | |
| 3603 match(RegF); | |
| 3604 | |
| 3605 format %{ %} | |
| 3606 interface(REG_INTER); | |
| 3607 %} | |
| 3608 | |
| 3609 // Double register operands | |
|
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3610 operand regD() |
| 0 | 3611 %{ |
| 3612 constraint(ALLOC_IN_RC(double_reg)); | |
| 3613 match(RegD); | |
| 3614 | |
| 3615 format %{ %} | |
| 3616 interface(REG_INTER); | |
| 3617 %} | |
| 3618 | |
| 3619 //----------Memory Operands---------------------------------------------------- | |
| 3620 // Direct Memory Operand | |
| 3621 // operand direct(immP addr) | |
| 3622 // %{ | |
| 3623 // match(addr); | |
| 3624 | |
| 3625 // format %{ "[$addr]" %} | |
| 3626 // interface(MEMORY_INTER) %{ | |
| 3627 // base(0xFFFFFFFF); | |
| 3628 // index(0x4); | |
| 3629 // scale(0x0); | |
| 3630 // disp($addr); | |
| 3631 // %} | |
| 3632 // %} | |
| 3633 | |
| 3634 // Indirect Memory Operand | |
| 3635 operand indirect(any_RegP reg) | |
| 3636 %{ | |
| 3637 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3638 match(reg); | |
| 3639 | |
| 3640 format %{ "[$reg]" %} | |
| 3641 interface(MEMORY_INTER) %{ | |
| 3642 base($reg); | |
| 3643 index(0x4); | |
| 3644 scale(0x0); | |
| 3645 disp(0x0); | |
| 3646 %} | |
| 3647 %} | |
| 3648 | |
| 3649 // Indirect Memory Plus Short Offset Operand | |
| 3650 operand indOffset8(any_RegP reg, immL8 off) | |
| 3651 %{ | |
| 3652 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3653 match(AddP reg off); | |
| 3654 | |
| 3655 format %{ "[$reg + $off (8-bit)]" %} | |
| 3656 interface(MEMORY_INTER) %{ | |
| 3657 base($reg); | |
| 3658 index(0x4); | |
| 3659 scale(0x0); | |
| 3660 disp($off); | |
| 3661 %} | |
| 3662 %} | |
| 3663 | |
| 3664 // Indirect Memory Plus Long Offset Operand | |
| 3665 operand indOffset32(any_RegP reg, immL32 off) | |
| 3666 %{ | |
| 3667 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3668 match(AddP reg off); | |
| 3669 | |
| 3670 format %{ "[$reg + $off (32-bit)]" %} | |
| 3671 interface(MEMORY_INTER) %{ | |
| 3672 base($reg); | |
| 3673 index(0x4); | |
| 3674 scale(0x0); | |
| 3675 disp($off); | |
| 3676 %} | |
| 3677 %} | |
| 3678 | |
| 3679 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3680 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 3681 %{ | |
| 3682 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3683 match(AddP (AddP reg lreg) off); | |
| 3684 | |
| 3685 op_cost(10); | |
| 3686 format %{"[$reg + $off + $lreg]" %} | |
| 3687 interface(MEMORY_INTER) %{ | |
| 3688 base($reg); | |
| 3689 index($lreg); | |
| 3690 scale(0x0); | |
| 3691 disp($off); | |
| 3692 %} | |
| 3693 %} | |
| 3694 | |
| 3695 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 3696 operand indIndex(any_RegP reg, rRegL lreg) | |
| 3697 %{ | |
| 3698 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3699 match(AddP reg lreg); | |
| 3700 | |
| 3701 op_cost(10); | |
| 3702 format %{"[$reg + $lreg]" %} | |
| 3703 interface(MEMORY_INTER) %{ | |
| 3704 base($reg); | |
| 3705 index($lreg); | |
| 3706 scale(0x0); | |
| 3707 disp(0x0); | |
| 3708 %} | |
| 3709 %} | |
| 3710 | |
| 3711 // Indirect Memory Times Scale Plus Index Register | |
| 3712 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 3713 %{ | |
| 3714 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3715 match(AddP reg (LShiftL lreg scale)); | |
| 3716 | |
| 3717 op_cost(10); | |
| 3718 format %{"[$reg + $lreg << $scale]" %} | |
| 3719 interface(MEMORY_INTER) %{ | |
| 3720 base($reg); | |
| 3721 index($lreg); | |
| 3722 scale($scale); | |
| 3723 disp(0x0); | |
| 3724 %} | |
| 3725 %} | |
| 3726 | |
| 3727 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 3728 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 3729 %{ | |
| 3730 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3731 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 3732 | |
| 3733 op_cost(10); | |
| 3734 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 3735 interface(MEMORY_INTER) %{ | |
| 3736 base($reg); | |
| 3737 index($lreg); | |
| 3738 scale($scale); | |
| 3739 disp($off); | |
| 3740 %} | |
| 3741 %} | |
| 3742 | |
| 3743 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 3744 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 3745 %{ | |
| 3746 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3747 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 3748 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 3749 | |
| 3750 op_cost(10); | |
| 3751 format %{"[$reg + $off + $idx << $scale]" %} | |
| 3752 interface(MEMORY_INTER) %{ | |
| 3753 base($reg); | |
| 3754 index($idx); | |
| 3755 scale($scale); | |
| 3756 disp($off); | |
| 3757 %} | |
| 3758 %} | |
| 3759 | |
|
642
660978a2a31a
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diff
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|
3760 // Indirect Narrow Oop Plus Offset Operand |
|
660978a2a31a
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diff
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|
3761 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
|
660978a2a31a
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|
3762 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
660978a2a31a
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|
3763 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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parents:
1567
diff
changeset
|
3764 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
642
660978a2a31a
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|
3765 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
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diff
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|
3766 match(AddP (DecodeN reg) off); |
|
660978a2a31a
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624
diff
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|
3767 |
|
660978a2a31a
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624
diff
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|
3768 op_cost(10); |
|
660978a2a31a
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624
diff
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|
3769 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
660978a2a31a
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624
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|
3770 interface(MEMORY_INTER) %{ |
|
660978a2a31a
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kvn
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624
diff
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|
3771 base(0xc); // R12 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3772 index($reg); |
|
660978a2a31a
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parents:
624
diff
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|
3773 scale(0x3); |
|
660978a2a31a
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parents:
624
diff
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|
3774 disp($off); |
|
660978a2a31a
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parents:
624
diff
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|
3775 %} |
|
660978a2a31a
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624
diff
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|
3776 %} |
|
660978a2a31a
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624
diff
changeset
|
3777 |
|
660978a2a31a
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624
diff
changeset
|
3778 // Indirect Memory Operand |
|
660978a2a31a
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624
diff
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|
3779 operand indirectNarrow(rRegN reg) |
|
660978a2a31a
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624
diff
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|
3780 %{ |
|
660978a2a31a
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624
diff
changeset
|
3781 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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624
diff
changeset
|
3782 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3783 match(DecodeN reg); |
|
660978a2a31a
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parents:
624
diff
changeset
|
3784 |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3785 format %{ "[$reg]" %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3786 interface(MEMORY_INTER) %{ |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3787 base($reg); |
|
660978a2a31a
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parents:
624
diff
changeset
|
3788 index(0x4); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3789 scale(0x0); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3790 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3791 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3792 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3793 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3794 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3795 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3796 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3797 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3798 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3799 match(AddP (DecodeN reg) off); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3800 |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3801 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3802 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3803 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3804 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3805 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3806 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3807 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3808 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3809 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3810 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3811 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3812 %{ |
|
660978a2a31a
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624
diff
changeset
|
3813 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3814 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3815 match(AddP (DecodeN reg) off); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3816 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3817 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3818 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3819 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3820 index(0x4); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3821 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3822 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3823 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3824 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3825 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3826 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
3827 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
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kvn
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624
diff
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|
3828 %{ |
|
660978a2a31a
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624
diff
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|
3829 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3830 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
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624
diff
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|
3831 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3832 |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3833 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3834 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
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624
diff
changeset
|
3835 interface(MEMORY_INTER) %{ |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3836 base($reg); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3837 index($lreg); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3838 scale(0x0); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3839 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3840 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3841 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3842 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3843 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
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624
diff
changeset
|
3844 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3845 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3846 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3847 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3848 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3849 |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3850 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3851 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3852 interface(MEMORY_INTER) %{ |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3853 base($reg); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
3854 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3855 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3856 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3857 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3858 %} |
|
660978a2a31a
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kvn
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624
diff
changeset
|
3859 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3860 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3861 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3862 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3863 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3864 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3865 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3866 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3867 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3868 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3869 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3870 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3871 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3872 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3873 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3874 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3875 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3876 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3877 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3878 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3879 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3880 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3881 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3882 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3883 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3884 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3885 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3886 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3887 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3888 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3889 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3890 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3891 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3892 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3893 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3894 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3895 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3896 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3897 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3898 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3899 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3900 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3901 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3902 format %{"[$reg + $off + $idx << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3903 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3904 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3905 index($idx); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3906 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3907 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3908 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3909 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3910 |
| 0 | 3911 //----------Special Memory Operands-------------------------------------------- |
| 3912 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 3913 // values on the stack where a match requires a value to | |
| 3914 // flow through memory. | |
| 3915 operand stackSlotP(sRegP reg) | |
| 3916 %{ | |
| 3917 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3918 // No match rule because this operand is only generated in matching | |
| 3919 | |
| 3920 format %{ "[$reg]" %} | |
| 3921 interface(MEMORY_INTER) %{ | |
| 3922 base(0x4); // RSP | |
| 3923 index(0x4); // No Index | |
| 3924 scale(0x0); // No Scale | |
| 3925 disp($reg); // Stack Offset | |
| 3926 %} | |
| 3927 %} | |
| 3928 | |
| 3929 operand stackSlotI(sRegI reg) | |
| 3930 %{ | |
| 3931 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3932 // No match rule because this operand is only generated in matching | |
| 3933 | |
| 3934 format %{ "[$reg]" %} | |
| 3935 interface(MEMORY_INTER) %{ | |
| 3936 base(0x4); // RSP | |
| 3937 index(0x4); // No Index | |
| 3938 scale(0x0); // No Scale | |
| 3939 disp($reg); // Stack Offset | |
| 3940 %} | |
| 3941 %} | |
| 3942 | |
| 3943 operand stackSlotF(sRegF reg) | |
| 3944 %{ | |
| 3945 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3946 // No match rule because this operand is only generated in matching | |
| 3947 | |
| 3948 format %{ "[$reg]" %} | |
| 3949 interface(MEMORY_INTER) %{ | |
| 3950 base(0x4); // RSP | |
| 3951 index(0x4); // No Index | |
| 3952 scale(0x0); // No Scale | |
| 3953 disp($reg); // Stack Offset | |
| 3954 %} | |
| 3955 %} | |
| 3956 | |
| 3957 operand stackSlotD(sRegD reg) | |
| 3958 %{ | |
| 3959 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3960 // No match rule because this operand is only generated in matching | |
| 3961 | |
| 3962 format %{ "[$reg]" %} | |
| 3963 interface(MEMORY_INTER) %{ | |
| 3964 base(0x4); // RSP | |
| 3965 index(0x4); // No Index | |
| 3966 scale(0x0); // No Scale | |
| 3967 disp($reg); // Stack Offset | |
| 3968 %} | |
| 3969 %} | |
| 3970 operand stackSlotL(sRegL reg) | |
| 3971 %{ | |
| 3972 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3973 // No match rule because this operand is only generated in matching | |
| 3974 | |
| 3975 format %{ "[$reg]" %} | |
| 3976 interface(MEMORY_INTER) %{ | |
| 3977 base(0x4); // RSP | |
| 3978 index(0x4); // No Index | |
| 3979 scale(0x0); // No Scale | |
| 3980 disp($reg); // Stack Offset | |
| 3981 %} | |
| 3982 %} | |
| 3983 | |
| 3984 //----------Conditional Branch Operands---------------------------------------- | |
| 3985 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 3986 // the following set of codes: | |
| 3987 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 3988 // | |
| 3989 // Other attributes of the comparison, such as unsignedness, are specified | |
| 3990 // by the comparison instruction that sets a condition code flags register. | |
| 3991 // That result is represented by a flags operand whose subtype is appropriate | |
| 3992 // to the unsignedness (etc.) of the comparison. | |
| 3993 // | |
| 3994 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 3995 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 3996 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 3997 | |
| 3998 // Comparision Code | |
| 3999 operand cmpOp() | |
| 4000 %{ | |
| 4001 match(Bool); | |
| 4002 | |
| 4003 format %{ "" %} | |
| 4004 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4005 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4006 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4007 less(0xC, "l"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4008 greater_equal(0xD, "ge"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4009 less_equal(0xE, "le"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4010 greater(0xF, "g"); |
| 12323 | 4011 overflow(0x0, "o"); |
| 4012 no_overflow(0x1, "no"); | |
| 0 | 4013 %} |
| 4014 %} | |
| 4015 | |
| 4016 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4017 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4018 // C0 and C3 are turned into Carry & Zero flags. | |
| 4019 operand cmpOpU() | |
| 4020 %{ | |
| 4021 match(Bool); | |
| 4022 | |
| 4023 format %{ "" %} | |
| 4024 interface(COND_INTER) %{ | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4025 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4026 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4027 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4028 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4029 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4030 greater(0x7, "nbe"); |
| 12323 | 4031 overflow(0x0, "o"); |
| 4032 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4033 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4034 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4035 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4036 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4037 // Floating comparisons that don't require any fixup for the unordered case |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4038 operand cmpOpUCF() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4039 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4040 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4041 n->as_Bool()->_test._test == BoolTest::ge || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4042 n->as_Bool()->_test._test == BoolTest::le || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4043 n->as_Bool()->_test._test == BoolTest::gt); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4044 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4045 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4046 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4047 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4048 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4049 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4050 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4051 greater(0x7, "nbe"); |
| 12323 | 4052 overflow(0x0, "o"); |
| 4053 no_overflow(0x1, "no"); | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4054 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4055 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4056 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4057 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4058 // Floating comparisons that can be fixed up with extra conditional jumps |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4059 operand cmpOpUCF2() %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4060 match(Bool); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4061 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4062 n->as_Bool()->_test._test == BoolTest::eq); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4063 format %{ "" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4064 interface(COND_INTER) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4065 equal(0x4, "e"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4066 not_equal(0x5, "ne"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4067 less(0x2, "b"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4068 greater_equal(0x3, "nb"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
4069 less_equal(0x6, "be"); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
4070 greater(0x7, "nbe"); |
| 12323 | 4071 overflow(0x0, "o"); |
| 4072 no_overflow(0x1, "no"); | |
| 0 | 4073 %} |
| 4074 %} | |
| 4075 | |
| 4076 | |
| 4077 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4078 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4079 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4080 // instructions for every form of operand when the instruction accepts |
| 4081 // multiple operand types with the same basic encoding and format. The classic | |
| 4082 // case of this is memory operands. | |
| 4083 | |
| 4084 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
4085 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4086 indCompressedOopOffset, |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4087 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
4088 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
4089 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 4090 |
| 4091 //----------PIPELINE----------------------------------------------------------- | |
| 4092 // Rules which define the behavior of the target architectures pipeline. | |
| 4093 pipeline %{ | |
| 4094 | |
| 4095 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4096 attributes %{ | |
| 4097 variable_size_instructions; // Fixed size instructions | |
| 4098 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4099 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4100 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4101 instruction_fetch_units = 1; // of 16 bytes | |
| 4102 | |
| 4103 // List of nop instructions | |
| 4104 nops( MachNop ); | |
| 4105 %} | |
| 4106 | |
| 4107 //----------RESOURCES---------------------------------------------------------- | |
| 4108 // Resources are the functional units available to the machine | |
| 4109 | |
| 4110 // Generic P2/P3 pipeline | |
| 4111 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4112 // 3 instructions decoded per cycle. | |
| 4113 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4114 // 3 ALU op, only ALU0 handles mul instructions. | |
| 4115 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4116 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 4117 BR, FPU, | |
| 4118 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 4119 | |
| 4120 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4121 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4122 | |
| 4123 // Generic P2/P3 pipeline | |
| 4124 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4125 | |
| 4126 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4127 // Pipeline Classes describe the stages in which input and output are | |
| 4128 // referenced by the hardware pipeline. | |
| 4129 | |
| 4130 // Naming convention: ialu or fpu | |
| 4131 // Then: _reg | |
| 4132 // Then: _reg if there is a 2nd register | |
| 4133 // Then: _long if it's a pair of instructions implementing a long | |
| 4134 // Then: _fat if it requires the big decoder | |
| 4135 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4136 | |
| 4137 // Integer ALU reg operation | |
| 4138 pipe_class ialu_reg(rRegI dst) | |
| 4139 %{ | |
| 4140 single_instruction; | |
| 4141 dst : S4(write); | |
| 4142 dst : S3(read); | |
| 4143 DECODE : S0; // any decoder | |
| 4144 ALU : S3; // any alu | |
| 4145 %} | |
| 4146 | |
| 4147 // Long ALU reg operation | |
| 4148 pipe_class ialu_reg_long(rRegL dst) | |
| 4149 %{ | |
| 4150 instruction_count(2); | |
| 4151 dst : S4(write); | |
| 4152 dst : S3(read); | |
| 4153 DECODE : S0(2); // any 2 decoders | |
| 4154 ALU : S3(2); // both alus | |
| 4155 %} | |
| 4156 | |
| 4157 // Integer ALU reg operation using big decoder | |
| 4158 pipe_class ialu_reg_fat(rRegI dst) | |
| 4159 %{ | |
| 4160 single_instruction; | |
| 4161 dst : S4(write); | |
| 4162 dst : S3(read); | |
| 4163 D0 : S0; // big decoder only | |
| 4164 ALU : S3; // any alu | |
| 4165 %} | |
| 4166 | |
| 4167 // Long ALU reg operation using big decoder | |
| 4168 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 4169 %{ | |
| 4170 instruction_count(2); | |
| 4171 dst : S4(write); | |
| 4172 dst : S3(read); | |
| 4173 D0 : S0(2); // big decoder only; twice | |
| 4174 ALU : S3(2); // any 2 alus | |
| 4175 %} | |
| 4176 | |
| 4177 // Integer ALU reg-reg operation | |
| 4178 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 4179 %{ | |
| 4180 single_instruction; | |
| 4181 dst : S4(write); | |
| 4182 src : S3(read); | |
| 4183 DECODE : S0; // any decoder | |
| 4184 ALU : S3; // any alu | |
| 4185 %} | |
| 4186 | |
| 4187 // Long ALU reg-reg operation | |
| 4188 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 4189 %{ | |
| 4190 instruction_count(2); | |
| 4191 dst : S4(write); | |
| 4192 src : S3(read); | |
| 4193 DECODE : S0(2); // any 2 decoders | |
| 4194 ALU : S3(2); // both alus | |
| 4195 %} | |
| 4196 | |
| 4197 // Integer ALU reg-reg operation | |
| 4198 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 4199 %{ | |
| 4200 single_instruction; | |
| 4201 dst : S4(write); | |
| 4202 src : S3(read); | |
| 4203 D0 : S0; // big decoder only | |
| 4204 ALU : S3; // any alu | |
| 4205 %} | |
| 4206 | |
| 4207 // Long ALU reg-reg operation | |
| 4208 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 4209 %{ | |
| 4210 instruction_count(2); | |
| 4211 dst : S4(write); | |
| 4212 src : S3(read); | |
| 4213 D0 : S0(2); // big decoder only; twice | |
| 4214 ALU : S3(2); // both alus | |
| 4215 %} | |
| 4216 | |
| 4217 // Integer ALU reg-mem operation | |
| 4218 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 4219 %{ | |
| 4220 single_instruction; | |
| 4221 dst : S5(write); | |
| 4222 mem : S3(read); | |
| 4223 D0 : S0; // big decoder only | |
| 4224 ALU : S4; // any alu | |
| 4225 MEM : S3; // any mem | |
| 4226 %} | |
| 4227 | |
| 4228 // Integer mem operation (prefetch) | |
| 4229 pipe_class ialu_mem(memory mem) | |
| 4230 %{ | |
| 4231 single_instruction; | |
| 4232 mem : S3(read); | |
| 4233 D0 : S0; // big decoder only | |
| 4234 MEM : S3; // any mem | |
| 4235 %} | |
| 4236 | |
| 4237 // Integer Store to Memory | |
| 4238 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 4239 %{ | |
| 4240 single_instruction; | |
| 4241 mem : S3(read); | |
| 4242 src : S5(read); | |
| 4243 D0 : S0; // big decoder only | |
| 4244 ALU : S4; // any alu | |
| 4245 MEM : S3; | |
| 4246 %} | |
| 4247 | |
| 4248 // // Long Store to Memory | |
| 4249 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 4250 // %{ | |
| 4251 // instruction_count(2); | |
| 4252 // mem : S3(read); | |
| 4253 // src : S5(read); | |
| 4254 // D0 : S0(2); // big decoder only; twice | |
| 4255 // ALU : S4(2); // any 2 alus | |
| 4256 // MEM : S3(2); // Both mems | |
| 4257 // %} | |
| 4258 | |
| 4259 // Integer Store to Memory | |
| 4260 pipe_class ialu_mem_imm(memory mem) | |
| 4261 %{ | |
| 4262 single_instruction; | |
| 4263 mem : S3(read); | |
| 4264 D0 : S0; // big decoder only | |
| 4265 ALU : S4; // any alu | |
| 4266 MEM : S3; | |
| 4267 %} | |
| 4268 | |
| 4269 // Integer ALU0 reg-reg operation | |
| 4270 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 4271 %{ | |
| 4272 single_instruction; | |
| 4273 dst : S4(write); | |
| 4274 src : S3(read); | |
| 4275 D0 : S0; // Big decoder only | |
| 4276 ALU0 : S3; // only alu0 | |
| 4277 %} | |
| 4278 | |
| 4279 // Integer ALU0 reg-mem operation | |
| 4280 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 4281 %{ | |
| 4282 single_instruction; | |
| 4283 dst : S5(write); | |
| 4284 mem : S3(read); | |
| 4285 D0 : S0; // big decoder only | |
| 4286 ALU0 : S4; // ALU0 only | |
| 4287 MEM : S3; // any mem | |
| 4288 %} | |
| 4289 | |
| 4290 // Integer ALU reg-reg operation | |
| 4291 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 4292 %{ | |
| 4293 single_instruction; | |
| 4294 cr : S4(write); | |
| 4295 src1 : S3(read); | |
| 4296 src2 : S3(read); | |
| 4297 DECODE : S0; // any decoder | |
| 4298 ALU : S3; // any alu | |
| 4299 %} | |
| 4300 | |
| 4301 // Integer ALU reg-imm operation | |
| 4302 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 4303 %{ | |
| 4304 single_instruction; | |
| 4305 cr : S4(write); | |
| 4306 src1 : S3(read); | |
| 4307 DECODE : S0; // any decoder | |
| 4308 ALU : S3; // any alu | |
| 4309 %} | |
| 4310 | |
| 4311 // Integer ALU reg-mem operation | |
| 4312 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 4313 %{ | |
| 4314 single_instruction; | |
| 4315 cr : S4(write); | |
| 4316 src1 : S3(read); | |
| 4317 src2 : S3(read); | |
| 4318 D0 : S0; // big decoder only | |
| 4319 ALU : S4; // any alu | |
| 4320 MEM : S3; | |
| 4321 %} | |
| 4322 | |
| 4323 // Conditional move reg-reg | |
| 4324 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 4325 %{ | |
| 4326 instruction_count(4); | |
| 4327 y : S4(read); | |
| 4328 q : S3(read); | |
| 4329 p : S3(read); | |
| 4330 DECODE : S0(4); // any decoder | |
| 4331 %} | |
| 4332 | |
| 4333 // Conditional move reg-reg | |
| 4334 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 4335 %{ | |
| 4336 single_instruction; | |
| 4337 dst : S4(write); | |
| 4338 src : S3(read); | |
| 4339 cr : S3(read); | |
| 4340 DECODE : S0; // any decoder | |
| 4341 %} | |
| 4342 | |
| 4343 // Conditional move reg-mem | |
| 4344 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 4345 %{ | |
| 4346 single_instruction; | |
| 4347 dst : S4(write); | |
| 4348 src : S3(read); | |
| 4349 cr : S3(read); | |
| 4350 DECODE : S0; // any decoder | |
| 4351 MEM : S3; | |
| 4352 %} | |
| 4353 | |
| 4354 // Conditional move reg-reg long | |
| 4355 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 4356 %{ | |
| 4357 single_instruction; | |
| 4358 dst : S4(write); | |
| 4359 src : S3(read); | |
| 4360 cr : S3(read); | |
| 4361 DECODE : S0(2); // any 2 decoders | |
| 4362 %} | |
| 4363 | |
| 4364 // XXX | |
| 4365 // // Conditional move double reg-reg | |
| 4366 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 4367 // %{ | |
| 4368 // single_instruction; | |
| 4369 // dst : S4(write); | |
| 4370 // src : S3(read); | |
| 4371 // cr : S3(read); | |
| 4372 // DECODE : S0; // any decoder | |
| 4373 // %} | |
| 4374 | |
| 4375 // Float reg-reg operation | |
| 4376 pipe_class fpu_reg(regD dst) | |
| 4377 %{ | |
| 4378 instruction_count(2); | |
| 4379 dst : S3(read); | |
| 4380 DECODE : S0(2); // any 2 decoders | |
| 4381 FPU : S3; | |
| 4382 %} | |
| 4383 | |
| 4384 // Float reg-reg operation | |
| 4385 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 4386 %{ | |
| 4387 instruction_count(2); | |
| 4388 dst : S4(write); | |
| 4389 src : S3(read); | |
| 4390 DECODE : S0(2); // any 2 decoders | |
| 4391 FPU : S3; | |
| 4392 %} | |
| 4393 | |
| 4394 // Float reg-reg operation | |
| 4395 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 4396 %{ | |
| 4397 instruction_count(3); | |
| 4398 dst : S4(write); | |
| 4399 src1 : S3(read); | |
| 4400 src2 : S3(read); | |
| 4401 DECODE : S0(3); // any 3 decoders | |
| 4402 FPU : S3(2); | |
| 4403 %} | |
| 4404 | |
| 4405 // Float reg-reg operation | |
| 4406 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 4407 %{ | |
| 4408 instruction_count(4); | |
| 4409 dst : S4(write); | |
| 4410 src1 : S3(read); | |
| 4411 src2 : S3(read); | |
| 4412 src3 : S3(read); | |
| 4413 DECODE : S0(4); // any 3 decoders | |
| 4414 FPU : S3(2); | |
| 4415 %} | |
| 4416 | |
| 4417 // Float reg-reg operation | |
| 4418 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 4419 %{ | |
| 4420 instruction_count(4); | |
| 4421 dst : S4(write); | |
| 4422 src1 : S3(read); | |
| 4423 src2 : S3(read); | |
| 4424 src3 : S3(read); | |
| 4425 DECODE : S1(3); // any 3 decoders | |
| 4426 D0 : S0; // Big decoder only | |
| 4427 FPU : S3(2); | |
| 4428 MEM : S3; | |
| 4429 %} | |
| 4430 | |
| 4431 // Float reg-mem operation | |
| 4432 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 4433 %{ | |
| 4434 instruction_count(2); | |
| 4435 dst : S5(write); | |
| 4436 mem : S3(read); | |
| 4437 D0 : S0; // big decoder only | |
| 4438 DECODE : S1; // any decoder for FPU POP | |
| 4439 FPU : S4; | |
| 4440 MEM : S3; // any mem | |
| 4441 %} | |
| 4442 | |
| 4443 // Float reg-mem operation | |
| 4444 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 4445 %{ | |
| 4446 instruction_count(3); | |
| 4447 dst : S5(write); | |
| 4448 src1 : S3(read); | |
| 4449 mem : S3(read); | |
| 4450 D0 : S0; // big decoder only | |
| 4451 DECODE : S1(2); // any decoder for FPU POP | |
| 4452 FPU : S4; | |
| 4453 MEM : S3; // any mem | |
| 4454 %} | |
| 4455 | |
| 4456 // Float mem-reg operation | |
| 4457 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 4458 %{ | |
| 4459 instruction_count(2); | |
| 4460 src : S5(read); | |
| 4461 mem : S3(read); | |
| 4462 DECODE : S0; // any decoder for FPU PUSH | |
| 4463 D0 : S1; // big decoder only | |
| 4464 FPU : S4; | |
| 4465 MEM : S3; // any mem | |
| 4466 %} | |
| 4467 | |
| 4468 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 4469 %{ | |
| 4470 instruction_count(3); | |
| 4471 src1 : S3(read); | |
| 4472 src2 : S3(read); | |
| 4473 mem : S3(read); | |
| 4474 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4475 D0 : S1; // big decoder only | |
| 4476 FPU : S4; | |
| 4477 MEM : S3; // any mem | |
| 4478 %} | |
| 4479 | |
| 4480 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 4481 %{ | |
| 4482 instruction_count(3); | |
| 4483 src1 : S3(read); | |
| 4484 src2 : S3(read); | |
| 4485 mem : S4(read); | |
| 4486 DECODE : S0; // any decoder for FPU PUSH | |
| 4487 D0 : S0(2); // big decoder only | |
| 4488 FPU : S4; | |
| 4489 MEM : S3(2); // any mem | |
| 4490 %} | |
| 4491 | |
| 4492 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 4493 %{ | |
| 4494 instruction_count(2); | |
| 4495 src1 : S3(read); | |
| 4496 dst : S4(read); | |
| 4497 D0 : S0(2); // big decoder only | |
| 4498 MEM : S3(2); // any mem | |
| 4499 %} | |
| 4500 | |
| 4501 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 4502 %{ | |
| 4503 instruction_count(3); | |
| 4504 src1 : S3(read); | |
| 4505 src2 : S3(read); | |
| 4506 dst : S4(read); | |
| 4507 D0 : S0(3); // big decoder only | |
| 4508 FPU : S4; | |
| 4509 MEM : S3(3); // any mem | |
| 4510 %} | |
| 4511 | |
| 4512 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 4513 %{ | |
| 4514 instruction_count(3); | |
| 4515 src1 : S4(read); | |
| 4516 mem : S4(read); | |
| 4517 DECODE : S0; // any decoder for FPU PUSH | |
| 4518 D0 : S0(2); // big decoder only | |
| 4519 FPU : S4; | |
| 4520 MEM : S3(2); // any mem | |
| 4521 %} | |
| 4522 | |
| 4523 // Float load constant | |
| 4524 pipe_class fpu_reg_con(regD dst) | |
| 4525 %{ | |
| 4526 instruction_count(2); | |
| 4527 dst : S5(write); | |
| 4528 D0 : S0; // big decoder only for the load | |
| 4529 DECODE : S1; // any decoder for FPU POP | |
| 4530 FPU : S4; | |
| 4531 MEM : S3; // any mem | |
| 4532 %} | |
| 4533 | |
| 4534 // Float load constant | |
| 4535 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 4536 %{ | |
| 4537 instruction_count(3); | |
| 4538 dst : S5(write); | |
| 4539 src : S3(read); | |
| 4540 D0 : S0; // big decoder only for the load | |
| 4541 DECODE : S1(2); // any decoder for FPU POP | |
| 4542 FPU : S4; | |
| 4543 MEM : S3; // any mem | |
| 4544 %} | |
| 4545 | |
| 4546 // UnConditional branch | |
| 4547 pipe_class pipe_jmp(label labl) | |
| 4548 %{ | |
| 4549 single_instruction; | |
| 4550 BR : S3; | |
| 4551 %} | |
| 4552 | |
| 4553 // Conditional branch | |
| 4554 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 4555 %{ | |
| 4556 single_instruction; | |
| 4557 cr : S1(read); | |
| 4558 BR : S3; | |
| 4559 %} | |
| 4560 | |
| 4561 // Allocation idiom | |
| 4562 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 4563 %{ | |
| 4564 instruction_count(1); force_serialization; | |
| 4565 fixed_latency(6); | |
| 4566 heap_ptr : S3(read); | |
| 4567 DECODE : S0(3); | |
| 4568 D0 : S2; | |
| 4569 MEM : S3; | |
| 4570 ALU : S3(2); | |
| 4571 dst : S5(write); | |
| 4572 BR : S5; | |
| 4573 %} | |
| 4574 | |
| 4575 // Generic big/slow expanded idiom | |
| 4576 pipe_class pipe_slow() | |
| 4577 %{ | |
| 4578 instruction_count(10); multiple_bundles; force_serialization; | |
| 4579 fixed_latency(100); | |
| 4580 D0 : S0(2); | |
| 4581 MEM : S3(2); | |
| 4582 %} | |
| 4583 | |
| 4584 // The real do-nothing guy | |
| 4585 pipe_class empty() | |
| 4586 %{ | |
| 4587 instruction_count(0); | |
| 4588 %} | |
| 4589 | |
| 4590 // Define the class for the Nop node | |
| 4591 define | |
| 4592 %{ | |
| 4593 MachNop = empty; | |
| 4594 %} | |
| 4595 | |
| 4596 %} | |
| 4597 | |
| 4598 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4599 // | |
| 4600 // match -- States which machine-independent subtree may be replaced | |
| 4601 // by this instruction. | |
| 4602 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4603 // selection to identify a minimum cost tree of machine | |
| 4604 // instructions that matches a tree of machine-independent | |
| 4605 // instructions. | |
| 4606 // format -- A string providing the disassembly for this instruction. | |
| 4607 // The value of an instruction's operand may be inserted | |
| 4608 // by referring to it with a '$' prefix. | |
| 4609 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4610 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4611 // rrspectively. The primary opcode is commonly used to | |
| 4612 // indicate the type of machine instruction, while secondary | |
| 4613 // and tertiary are often used for prefix options or addressing | |
| 4614 // modes. | |
| 4615 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4616 // name must have been defined in an 'enc_class' specification | |
| 4617 // in the encode section of the architecture description. | |
| 4618 | |
| 4619 | |
| 4620 //----------Load/Store/Move Instructions--------------------------------------- | |
| 4621 //----------Load Instructions-------------------------------------------------- | |
| 4622 | |
| 4623 // Load Byte (8 bit signed) | |
| 4624 instruct loadB(rRegI dst, memory mem) | |
| 4625 %{ | |
| 4626 match(Set dst (LoadB mem)); | |
| 4627 | |
| 4628 ins_cost(125); | |
| 4629 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 4630 |
| 4631 ins_encode %{ | |
| 4632 __ movsbl($dst$$Register, $mem$$Address); | |
| 4633 %} | |
| 4634 | |
| 0 | 4635 ins_pipe(ialu_reg_mem); |
| 4636 %} | |
| 4637 | |
| 624 | 4638 // Load Byte (8 bit signed) into Long Register |
| 4639 instruct loadB2L(rRegL dst, memory mem) | |
| 4640 %{ | |
| 4641 match(Set dst (ConvI2L (LoadB mem))); | |
| 4642 | |
| 4643 ins_cost(125); | |
| 4644 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 4645 | |
| 4646 ins_encode %{ | |
| 4647 __ movsbq($dst$$Register, $mem$$Address); | |
| 4648 %} | |
| 4649 | |
| 4650 ins_pipe(ialu_reg_mem); | |
| 4651 %} | |
| 4652 | |
| 4653 // Load Unsigned Byte (8 bit UNsigned) | |
| 4654 instruct loadUB(rRegI dst, memory mem) | |
| 4655 %{ | |
| 4656 match(Set dst (LoadUB mem)); | |
| 0 | 4657 |
| 4658 ins_cost(125); | |
| 4659 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 4660 |
| 4661 ins_encode %{ | |
| 4662 __ movzbl($dst$$Register, $mem$$Address); | |
| 4663 %} | |
| 4664 | |
| 0 | 4665 ins_pipe(ialu_reg_mem); |
| 4666 %} | |
| 4667 | |
| 624 | 4668 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 4669 instruct loadUB2L(rRegL dst, memory mem) | |
| 4670 %{ | |
| 4671 match(Set dst (ConvI2L (LoadUB mem))); | |
| 4672 | |
| 4673 ins_cost(125); | |
| 4674 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 4675 | |
| 4676 ins_encode %{ | |
| 4677 __ movzbq($dst$$Register, $mem$$Address); | |
| 4678 %} | |
| 4679 | |
| 4680 ins_pipe(ialu_reg_mem); | |
| 4681 %} | |
| 0 | 4682 |
| 824 | 4683 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 4684 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 4685 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 4686 effect(KILL cr); | |
| 4687 | |
| 4688 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 4689 "andl $dst, $mask" %} | |
| 4690 ins_encode %{ | |
| 4691 Register Rdst = $dst$$Register; | |
| 4692 __ movzbq(Rdst, $mem$$Address); | |
| 4693 __ andl(Rdst, $mask$$constant); | |
| 4694 %} | |
| 4695 ins_pipe(ialu_reg_mem); | |
| 4696 %} | |
| 4697 | |
| 0 | 4698 // Load Short (16 bit signed) |
| 4699 instruct loadS(rRegI dst, memory mem) | |
| 4700 %{ | |
| 4701 match(Set dst (LoadS mem)); | |
| 4702 | |
| 624 | 4703 ins_cost(125); |
| 0 | 4704 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 4705 |
| 4706 ins_encode %{ | |
| 4707 __ movswl($dst$$Register, $mem$$Address); | |
| 4708 %} | |
| 4709 | |
| 0 | 4710 ins_pipe(ialu_reg_mem); |
| 4711 %} | |
| 4712 | |
| 785 | 4713 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 4714 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4715 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 4716 | |
| 4717 ins_cost(125); | |
| 4718 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 4719 ins_encode %{ | |
| 4720 __ movsbl($dst$$Register, $mem$$Address); | |
| 4721 %} | |
| 4722 ins_pipe(ialu_reg_mem); | |
| 4723 %} | |
| 4724 | |
| 624 | 4725 // Load Short (16 bit signed) into Long Register |
| 4726 instruct loadS2L(rRegL dst, memory mem) | |
| 4727 %{ | |
| 4728 match(Set dst (ConvI2L (LoadS mem))); | |
| 4729 | |
| 4730 ins_cost(125); | |
| 4731 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 4732 | |
| 4733 ins_encode %{ | |
| 4734 __ movswq($dst$$Register, $mem$$Address); | |
| 4735 %} | |
| 4736 | |
| 4737 ins_pipe(ialu_reg_mem); | |
| 4738 %} | |
| 0 | 4739 |
|
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|
4740 // Load Unsigned Short/Char (16 bit UNsigned) |
|
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|
4741 instruct loadUS(rRegI dst, memory mem) |
|
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|
4742 %{ |
|
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|
4743 match(Set dst (LoadUS mem)); |
| 0 | 4744 |
| 4745 ins_cost(125); | |
|
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|
4746 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 4747 |
| 4748 ins_encode %{ | |
| 4749 __ movzwl($dst$$Register, $mem$$Address); | |
| 4750 %} | |
| 4751 | |
| 0 | 4752 ins_pipe(ialu_reg_mem); |
| 4753 %} | |
| 4754 | |
| 785 | 4755 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 4756 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4757 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 4758 | |
| 4759 ins_cost(125); | |
| 4760 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 4761 ins_encode %{ | |
| 4762 __ movsbl($dst$$Register, $mem$$Address); | |
| 4763 %} | |
| 4764 ins_pipe(ialu_reg_mem); | |
| 4765 %} | |
| 4766 | |
| 624 | 4767 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 4768 instruct loadUS2L(rRegL dst, memory mem) | |
| 4769 %{ | |
| 4770 match(Set dst (ConvI2L (LoadUS mem))); | |
| 4771 | |
| 4772 ins_cost(125); | |
| 4773 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 4774 | |
| 4775 ins_encode %{ | |
| 4776 __ movzwq($dst$$Register, $mem$$Address); | |
| 4777 %} | |
| 4778 | |
| 4779 ins_pipe(ialu_reg_mem); | |
| 4780 %} | |
| 0 | 4781 |
| 824 | 4782 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 4783 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4784 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4785 | |
| 4786 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 4787 ins_encode %{ | |
| 4788 __ movzbq($dst$$Register, $mem$$Address); | |
| 4789 %} | |
| 4790 ins_pipe(ialu_reg_mem); | |
| 4791 %} | |
| 4792 | |
| 4793 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 4794 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 4795 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 4796 effect(KILL cr); | |
| 4797 | |
| 4798 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 4799 "andl $dst, $mask" %} | |
| 4800 ins_encode %{ | |
| 4801 Register Rdst = $dst$$Register; | |
| 4802 __ movzwq(Rdst, $mem$$Address); | |
| 4803 __ andl(Rdst, $mask$$constant); | |
| 4804 %} | |
| 4805 ins_pipe(ialu_reg_mem); | |
| 4806 %} | |
| 4807 | |
| 0 | 4808 // Load Integer |
| 4809 instruct loadI(rRegI dst, memory mem) | |
| 4810 %{ | |
| 4811 match(Set dst (LoadI mem)); | |
| 4812 | |
| 624 | 4813 ins_cost(125); |
| 0 | 4814 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 4815 |
| 4816 ins_encode %{ | |
| 4817 __ movl($dst$$Register, $mem$$Address); | |
| 4818 %} | |
| 4819 | |
| 4820 ins_pipe(ialu_reg_mem); | |
| 4821 %} | |
| 4822 | |
| 785 | 4823 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 4824 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 4825 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 4826 | |
| 4827 ins_cost(125); | |
| 4828 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 4829 ins_encode %{ | |
| 4830 __ movsbl($dst$$Register, $mem$$Address); | |
| 4831 %} | |
| 4832 ins_pipe(ialu_reg_mem); | |
| 4833 %} | |
| 4834 | |
| 4835 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 4836 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 4837 match(Set dst (AndI (LoadI mem) mask)); | |
| 4838 | |
| 4839 ins_cost(125); | |
| 4840 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 4841 ins_encode %{ | |
| 4842 __ movzbl($dst$$Register, $mem$$Address); | |
| 4843 %} | |
| 4844 ins_pipe(ialu_reg_mem); | |
| 4845 %} | |
| 4846 | |
| 4847 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 4848 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 4849 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 4850 | |
| 4851 ins_cost(125); | |
| 4852 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 4853 ins_encode %{ | |
| 4854 __ movswl($dst$$Register, $mem$$Address); | |
| 4855 %} | |
| 4856 ins_pipe(ialu_reg_mem); | |
| 4857 %} | |
| 4858 | |
| 4859 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 4860 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 4861 match(Set dst (AndI (LoadI mem) mask)); | |
| 4862 | |
| 4863 ins_cost(125); | |
| 4864 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 4865 ins_encode %{ | |
| 4866 __ movzwl($dst$$Register, $mem$$Address); | |
| 4867 %} | |
| 4868 ins_pipe(ialu_reg_mem); | |
| 4869 %} | |
| 4870 | |
| 624 | 4871 // Load Integer into Long Register |
| 4872 instruct loadI2L(rRegL dst, memory mem) | |
| 4873 %{ | |
| 4874 match(Set dst (ConvI2L (LoadI mem))); | |
| 4875 | |
| 4876 ins_cost(125); | |
| 4877 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 4878 | |
| 4879 ins_encode %{ | |
| 4880 __ movslq($dst$$Register, $mem$$Address); | |
| 4881 %} | |
| 4882 | |
| 4883 ins_pipe(ialu_reg_mem); | |
| 4884 %} | |
| 4885 | |
| 824 | 4886 // Load Integer with mask 0xFF into Long Register |
| 4887 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 4888 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4889 | |
| 4890 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 4891 ins_encode %{ | |
| 4892 __ movzbq($dst$$Register, $mem$$Address); | |
| 4893 %} | |
| 4894 ins_pipe(ialu_reg_mem); | |
| 4895 %} | |
| 4896 | |
| 4897 // Load Integer with mask 0xFFFF into Long Register | |
| 4898 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 4899 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 4900 | |
| 4901 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 4902 ins_encode %{ | |
| 4903 __ movzwq($dst$$Register, $mem$$Address); | |
| 4904 %} | |
| 4905 ins_pipe(ialu_reg_mem); | |
| 4906 %} | |
| 4907 | |
|
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|
4908 // Load Integer with a 31-bit mask into Long Register |
|
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|
4909 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{ |
| 824 | 4910 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 4911 effect(KILL cr); | |
| 4912 | |
|
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|
4913 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 4914 "andl $dst, $mask" %} |
| 4915 ins_encode %{ | |
| 4916 Register Rdst = $dst$$Register; | |
| 4917 __ movl(Rdst, $mem$$Address); | |
| 4918 __ andl(Rdst, $mask$$constant); | |
| 4919 %} | |
| 4920 ins_pipe(ialu_reg_mem); | |
| 4921 %} | |
| 4922 | |
| 624 | 4923 // Load Unsigned Integer into Long Register |
| 6849 | 4924 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask) |
| 4925 %{ | |
| 4926 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 624 | 4927 |
| 4928 ins_cost(125); | |
| 4929 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 4930 | |
| 4931 ins_encode %{ | |
| 4932 __ movl($dst$$Register, $mem$$Address); | |
| 4933 %} | |
| 4934 | |
| 0 | 4935 ins_pipe(ialu_reg_mem); |
| 4936 %} | |
| 4937 | |
| 4938 // Load Long | |
| 4939 instruct loadL(rRegL dst, memory mem) | |
| 4940 %{ | |
| 4941 match(Set dst (LoadL mem)); | |
| 4942 | |
| 624 | 4943 ins_cost(125); |
| 0 | 4944 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 4945 |
| 4946 ins_encode %{ | |
| 4947 __ movq($dst$$Register, $mem$$Address); | |
| 4948 %} | |
| 4949 | |
| 0 | 4950 ins_pipe(ialu_reg_mem); // XXX |
| 4951 %} | |
| 4952 | |
| 4953 // Load Range | |
| 4954 instruct loadRange(rRegI dst, memory mem) | |
| 4955 %{ | |
| 4956 match(Set dst (LoadRange mem)); | |
| 4957 | |
| 4958 ins_cost(125); // XXX | |
| 4959 format %{ "movl $dst, $mem\t# range" %} | |
| 4960 opcode(0x8B); | |
| 4961 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4962 ins_pipe(ialu_reg_mem); | |
| 4963 %} | |
| 4964 | |
| 4965 // Load Pointer | |
| 4966 instruct loadP(rRegP dst, memory mem) | |
| 4967 %{ | |
| 4968 match(Set dst (LoadP mem)); | |
| 4969 | |
| 4970 ins_cost(125); // XXX | |
| 4971 format %{ "movq $dst, $mem\t# ptr" %} | |
| 4972 opcode(0x8B); | |
| 4973 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 4974 ins_pipe(ialu_reg_mem); // XXX | |
| 4975 %} | |
| 4976 | |
|
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4977 // Load Compressed Pointer |
| 163 | 4978 instruct loadN(rRegN dst, memory mem) |
|
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4979 %{ |
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4980 match(Set dst (LoadN mem)); |
|
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4981 |
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|
4982 ins_cost(125); // XXX |
|
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4983 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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4984 ins_encode %{ |
|
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4985 __ movl($dst$$Register, $mem$$Address); |
|
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4986 %} |
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4987 ins_pipe(ialu_reg_mem); // XXX |
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4988 %} |
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4989 |
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4990 |
| 0 | 4991 // Load Klass Pointer |
| 4992 instruct loadKlass(rRegP dst, memory mem) | |
| 4993 %{ | |
| 4994 match(Set dst (LoadKlass mem)); | |
| 4995 | |
| 4996 ins_cost(125); // XXX | |
| 4997 format %{ "movq $dst, $mem\t# class" %} | |
| 4998 opcode(0x8B); | |
| 4999 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5000 ins_pipe(ialu_reg_mem); // XXX | |
| 5001 %} | |
| 5002 | |
|
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|
5003 // Load narrow Klass Pointer |
|
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5004 instruct loadNKlass(rRegN dst, memory mem) |
|
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5005 %{ |
|
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|
5006 match(Set dst (LoadNKlass mem)); |
|
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5007 |
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5008 ins_cost(125); // XXX |
|
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5009 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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5010 ins_encode %{ |
|
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5011 __ movl($dst$$Register, $mem$$Address); |
|
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5012 %} |
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5013 ins_pipe(ialu_reg_mem); // XXX |
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5014 %} |
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5015 |
| 0 | 5016 // Load Float |
| 5017 instruct loadF(regF dst, memory mem) | |
| 5018 %{ | |
| 5019 match(Set dst (LoadF mem)); | |
| 5020 | |
| 5021 ins_cost(145); // XXX | |
| 5022 format %{ "movss $dst, $mem\t# float" %} | |
| 4759 | 5023 ins_encode %{ |
| 5024 __ movflt($dst$$XMMRegister, $mem$$Address); | |
| 5025 %} | |
| 0 | 5026 ins_pipe(pipe_slow); // XXX |
| 5027 %} | |
| 5028 | |
| 5029 // Load Double | |
| 5030 instruct loadD_partial(regD dst, memory mem) | |
| 5031 %{ | |
| 5032 predicate(!UseXmmLoadAndClearUpper); | |
| 5033 match(Set dst (LoadD mem)); | |
| 5034 | |
| 5035 ins_cost(145); // XXX | |
| 5036 format %{ "movlpd $dst, $mem\t# double" %} | |
| 4759 | 5037 ins_encode %{ |
| 5038 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5039 %} | |
| 0 | 5040 ins_pipe(pipe_slow); // XXX |
| 5041 %} | |
| 5042 | |
| 5043 instruct loadD(regD dst, memory mem) | |
| 5044 %{ | |
| 5045 predicate(UseXmmLoadAndClearUpper); | |
| 5046 match(Set dst (LoadD mem)); | |
| 5047 | |
| 5048 ins_cost(145); // XXX | |
| 5049 format %{ "movsd $dst, $mem\t# double" %} | |
| 4759 | 5050 ins_encode %{ |
| 5051 __ movdbl($dst$$XMMRegister, $mem$$Address); | |
| 5052 %} | |
| 0 | 5053 ins_pipe(pipe_slow); // XXX |
| 5054 %} | |
| 5055 | |
| 5056 // Load Effective Address | |
| 5057 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 5058 %{ | |
| 5059 match(Set dst mem); | |
| 5060 | |
| 5061 ins_cost(110); // XXX | |
| 5062 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 5063 opcode(0x8D); | |
| 5064 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5065 ins_pipe(ialu_reg_reg_fat); | |
| 5066 %} | |
| 5067 | |
| 5068 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 5069 %{ | |
| 5070 match(Set dst mem); | |
| 5071 | |
| 5072 ins_cost(110); | |
| 5073 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 5074 opcode(0x8D); | |
| 5075 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5076 ins_pipe(ialu_reg_reg_fat); | |
| 5077 %} | |
| 5078 | |
| 5079 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 5080 // %{ | |
| 5081 // match(Set dst mem); | |
| 5082 | |
| 5083 // ins_cost(110); | |
| 5084 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 5085 // opcode(0x8D); | |
| 5086 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5087 // ins_pipe(ialu_reg_reg_fat); | |
| 5088 // %} | |
| 5089 | |
| 5090 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 5091 %{ | |
| 5092 match(Set dst mem); | |
| 5093 | |
| 5094 ins_cost(110); | |
| 5095 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 5096 opcode(0x8D); | |
| 5097 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5098 ins_pipe(ialu_reg_reg_fat); | |
| 5099 %} | |
| 5100 | |
| 5101 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 5102 %{ | |
| 5103 match(Set dst mem); | |
| 5104 | |
| 5105 ins_cost(110); | |
| 5106 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 5107 opcode(0x8D); | |
| 5108 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5109 ins_pipe(ialu_reg_reg_fat); | |
| 5110 %} | |
| 5111 | |
| 5112 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 5113 %{ | |
| 5114 match(Set dst mem); | |
| 5115 | |
| 5116 ins_cost(110); | |
| 5117 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 5118 opcode(0x8D); | |
| 5119 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 5120 ins_pipe(ialu_reg_reg_fat); | |
| 5121 %} | |
| 5122 | |
|
642
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|
5123 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
|
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|
5124 %{ |
|
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|
5125 match(Set dst mem); |
|
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|
5126 |
|
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|
5127 ins_cost(110); |
|
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|
5128 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
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|
5129 opcode(0x8D); |
|
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|
5130 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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|
5131 ins_pipe(ialu_reg_reg_fat); |
|
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|
5132 %} |
|
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|
5133 |
|
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|
5134 // Load Effective Address which uses Narrow (32-bits) oop |
|
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|
5135 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
|
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|
5136 %{ |
|
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|
5137 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
660978a2a31a
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|
5138 match(Set dst mem); |
|
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|
5139 |
|
660978a2a31a
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diff
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|
5140 ins_cost(110); |
|
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diff
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|
5141 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
|
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|
5142 opcode(0x8D); |
|
660978a2a31a
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|
5143 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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|
5144 ins_pipe(ialu_reg_reg_fat); |
|
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|
5145 %} |
|
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|
5146 |
|
660978a2a31a
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|
5147 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
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|
5148 %{ |
|
660978a2a31a
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|
5149 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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|
5150 match(Set dst mem); |
|
660978a2a31a
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|
5151 |
|
660978a2a31a
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|
5152 ins_cost(110); // XXX |
|
660978a2a31a
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diff
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|
5153 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
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|
5154 opcode(0x8D); |
|
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|
5155 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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|
5156 ins_pipe(ialu_reg_reg_fat); |
|
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diff
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|
5157 %} |
|
660978a2a31a
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diff
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|
5158 |
|
660978a2a31a
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diff
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|
5159 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
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|
5160 %{ |
|
660978a2a31a
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diff
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|
5161 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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diff
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|
5162 match(Set dst mem); |
|
660978a2a31a
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diff
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|
5163 |
|
660978a2a31a
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diff
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|
5164 ins_cost(110); |
|
660978a2a31a
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624
diff
changeset
|
5165 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
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624
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|
5166 opcode(0x8D); |
|
660978a2a31a
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|
5167 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
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|
5168 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
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624
diff
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|
5169 %} |
|
660978a2a31a
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diff
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|
5170 |
|
660978a2a31a
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624
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changeset
|
5171 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
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|
5172 %{ |
|
660978a2a31a
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|
5173 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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diff
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|
5174 match(Set dst mem); |
|
660978a2a31a
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624
diff
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|
5175 |
|
660978a2a31a
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624
diff
changeset
|
5176 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
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|
5177 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
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624
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changeset
|
5178 opcode(0x8D); |
|
660978a2a31a
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|
5179 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
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|
5180 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
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624
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|
5181 %} |
|
660978a2a31a
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|
5182 |
|
660978a2a31a
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624
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changeset
|
5183 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
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|
5184 %{ |
|
660978a2a31a
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624
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|
5185 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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|
5186 match(Set dst mem); |
|
660978a2a31a
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|
5187 |
|
660978a2a31a
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diff
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|
5188 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
5189 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
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624
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|
5190 opcode(0x8D); |
|
660978a2a31a
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|
5191 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
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|
5192 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
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624
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|
5193 %} |
|
660978a2a31a
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|
5194 |
|
660978a2a31a
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changeset
|
5195 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
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|
5196 %{ |
|
660978a2a31a
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|
5197 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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|
5198 match(Set dst mem); |
|
660978a2a31a
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|
5199 |
|
660978a2a31a
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624
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|
5200 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
5201 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
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|
5202 opcode(0x8D); |
|
660978a2a31a
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|
5203 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
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|
5204 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
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|
5205 %} |
|
660978a2a31a
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|
5206 |
|
660978a2a31a
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changeset
|
5207 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
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|
5208 %{ |
|
660978a2a31a
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|
5209 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
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kvn
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diff
changeset
|
5210 match(Set dst mem); |
|
660978a2a31a
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|
5211 |
|
660978a2a31a
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changeset
|
5212 ins_cost(110); |
|
660978a2a31a
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diff
changeset
|
5213 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
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changeset
|
5214 opcode(0x8D); |
|
660978a2a31a
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|
5215 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
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|
5216 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
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changeset
|
5217 %} |
|
660978a2a31a
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|
5218 |
| 0 | 5219 instruct loadConI(rRegI dst, immI src) |
| 5220 %{ | |
| 5221 match(Set dst src); | |
| 5222 | |
| 5223 format %{ "movl $dst, $src\t# int" %} | |
| 5224 ins_encode(load_immI(dst, src)); | |
| 5225 ins_pipe(ialu_reg_fat); // XXX | |
| 5226 %} | |
| 5227 | |
| 5228 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 5229 %{ | |
| 5230 match(Set dst src); | |
| 5231 effect(KILL cr); | |
| 5232 | |
| 5233 ins_cost(50); | |
| 5234 format %{ "xorl $dst, $dst\t# int" %} | |
| 5235 opcode(0x33); /* + rd */ | |
| 5236 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5237 ins_pipe(ialu_reg); | |
| 5238 %} | |
| 5239 | |
| 5240 instruct loadConL(rRegL dst, immL src) | |
| 5241 %{ | |
| 5242 match(Set dst src); | |
| 5243 | |
| 5244 ins_cost(150); | |
| 5245 format %{ "movq $dst, $src\t# long" %} | |
| 5246 ins_encode(load_immL(dst, src)); | |
| 5247 ins_pipe(ialu_reg); | |
| 5248 %} | |
| 5249 | |
| 5250 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 5251 %{ | |
| 5252 match(Set dst src); | |
| 5253 effect(KILL cr); | |
| 5254 | |
| 5255 ins_cost(50); | |
| 5256 format %{ "xorl $dst, $dst\t# long" %} | |
| 5257 opcode(0x33); /* + rd */ | |
| 5258 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5259 ins_pipe(ialu_reg); // XXX | |
| 5260 %} | |
| 5261 | |
| 5262 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 5263 %{ | |
| 5264 match(Set dst src); | |
| 5265 | |
| 5266 ins_cost(60); | |
| 5267 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 5268 ins_encode(load_immUL32(dst, src)); | |
| 5269 ins_pipe(ialu_reg); | |
| 5270 %} | |
| 5271 | |
| 5272 instruct loadConL32(rRegL dst, immL32 src) | |
| 5273 %{ | |
| 5274 match(Set dst src); | |
| 5275 | |
| 5276 ins_cost(70); | |
| 5277 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 5278 ins_encode(load_immL32(dst, src)); | |
| 5279 ins_pipe(ialu_reg); | |
| 5280 %} | |
| 5281 | |
| 2008 | 5282 instruct loadConP(rRegP dst, immP con) %{ |
| 5283 match(Set dst con); | |
| 5284 | |
| 5285 format %{ "movq $dst, $con\t# ptr" %} | |
| 5286 ins_encode(load_immP(dst, con)); | |
| 0 | 5287 ins_pipe(ialu_reg_fat); // XXX |
| 5288 %} | |
| 5289 | |
| 5290 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 5291 %{ | |
| 5292 match(Set dst src); | |
| 5293 effect(KILL cr); | |
| 5294 | |
| 5295 ins_cost(50); | |
| 5296 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 5297 opcode(0x33); /* + rd */ | |
| 5298 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 5299 ins_pipe(ialu_reg); | |
| 5300 %} | |
| 5301 | |
| 5302 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 5303 %{ | |
| 5304 match(Set dst src); | |
| 5305 effect(KILL cr); | |
| 5306 | |
| 5307 ins_cost(60); | |
| 5308 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 5309 ins_encode(load_immP31(dst, src)); | |
| 5310 ins_pipe(ialu_reg); | |
| 5311 %} | |
| 5312 | |
| 2008 | 5313 instruct loadConF(regF dst, immF con) %{ |
| 5314 match(Set dst con); | |
| 0 | 5315 ins_cost(125); |
| 2008 | 5316 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
| 5317 ins_encode %{ | |
| 5318 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5319 %} | |
| 0 | 5320 ins_pipe(pipe_slow); |
| 5321 %} | |
| 5322 | |
|
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5323 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
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5324 match(Set dst src); |
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5325 effect(KILL cr); |
|
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5326 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
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5327 ins_encode %{ |
|
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5328 __ xorq($dst$$Register, $dst$$Register); |
|
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5329 %} |
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5330 ins_pipe(ialu_reg); |
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5331 %} |
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5332 |
|
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5333 instruct loadConN(rRegN dst, immN src) %{ |
|
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5334 match(Set dst src); |
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5335 |
|
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5336 ins_cost(125); |
|
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5337 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
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5338 ins_encode %{ |
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5339 address con = (address)$src$$constant; |
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5340 if (con == NULL) { |
|
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5341 ShouldNotReachHere(); |
|
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5342 } else { |
|
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5343 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
|
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5344 } |
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5345 %} |
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5346 ins_pipe(ialu_reg_fat); // XXX |
|
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5347 %} |
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5348 |
|
6848
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|
5349 instruct loadConNKlass(rRegN dst, immNKlass src) %{ |
|
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|
5350 match(Set dst src); |
|
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|
5351 |
|
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|
5352 ins_cost(125); |
|
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|
5353 format %{ "movl $dst, $src\t# compressed klass ptr" %} |
|
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|
5354 ins_encode %{ |
|
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|
5355 address con = (address)$src$$constant; |
|
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|
5356 if (con == NULL) { |
|
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|
5357 ShouldNotReachHere(); |
|
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|
5358 } else { |
|
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|
5359 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant); |
|
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|
5360 } |
|
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|
5361 %} |
|
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|
5362 ins_pipe(ialu_reg_fat); // XXX |
|
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|
5363 %} |
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|
5364 |
| 0 | 5365 instruct loadConF0(regF dst, immF0 src) |
| 5366 %{ | |
| 5367 match(Set dst src); | |
| 5368 ins_cost(100); | |
| 5369 | |
| 5370 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 4759 | 5371 ins_encode %{ |
| 5372 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5373 %} | |
| 0 | 5374 ins_pipe(pipe_slow); |
| 5375 %} | |
| 5376 | |
| 5377 // Use the same format since predicate() can not be used here. | |
| 2008 | 5378 instruct loadConD(regD dst, immD con) %{ |
| 5379 match(Set dst con); | |
| 0 | 5380 ins_cost(125); |
| 2008 | 5381 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
| 5382 ins_encode %{ | |
| 5383 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 5384 %} | |
| 0 | 5385 ins_pipe(pipe_slow); |
| 5386 %} | |
| 5387 | |
| 5388 instruct loadConD0(regD dst, immD0 src) | |
| 5389 %{ | |
| 5390 match(Set dst src); | |
| 5391 ins_cost(100); | |
| 5392 | |
| 5393 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 4759 | 5394 ins_encode %{ |
| 5395 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5396 %} | |
| 0 | 5397 ins_pipe(pipe_slow); |
| 5398 %} | |
| 5399 | |
| 5400 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 5401 %{ | |
| 5402 match(Set dst src); | |
| 5403 | |
| 5404 ins_cost(125); | |
| 5405 format %{ "movl $dst, $src\t# int stk" %} | |
| 5406 opcode(0x8B); | |
| 5407 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 5408 ins_pipe(ialu_reg_mem); | |
| 5409 %} | |
| 5410 | |
| 5411 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 5412 %{ | |
| 5413 match(Set dst src); | |
| 5414 | |
| 5415 ins_cost(125); | |
| 5416 format %{ "movq $dst, $src\t# long stk" %} | |
| 5417 opcode(0x8B); | |
| 5418 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5419 ins_pipe(ialu_reg_mem); | |
| 5420 %} | |
| 5421 | |
| 5422 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 5423 %{ | |
| 5424 match(Set dst src); | |
| 5425 | |
| 5426 ins_cost(125); | |
| 5427 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5428 opcode(0x8B); | |
| 5429 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 5430 ins_pipe(ialu_reg_mem); | |
| 5431 %} | |
| 5432 | |
| 5433 instruct loadSSF(regF dst, stackSlotF src) | |
| 5434 %{ | |
| 5435 match(Set dst src); | |
| 5436 | |
| 5437 ins_cost(125); | |
| 5438 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5439 ins_encode %{ |
| 5440 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5441 %} | |
| 0 | 5442 ins_pipe(pipe_slow); // XXX |
| 5443 %} | |
| 5444 | |
| 5445 // Use the same format since predicate() can not be used here. | |
| 5446 instruct loadSSD(regD dst, stackSlotD src) | |
| 5447 %{ | |
| 5448 match(Set dst src); | |
| 5449 | |
| 5450 ins_cost(125); | |
| 5451 format %{ "movsd $dst, $src\t# double stk" %} | |
| 5452 ins_encode %{ | |
| 5453 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 5454 %} | |
| 5455 ins_pipe(pipe_slow); // XXX | |
| 5456 %} | |
| 5457 | |
| 5458 // Prefetch instructions. | |
| 5459 // Must be safe to execute with invalid address (cannot fault). | |
| 5460 | |
| 5461 instruct prefetchr( memory mem ) %{ | |
| 5462 predicate(ReadPrefetchInstr==3); | |
| 5463 match(PrefetchRead mem); | |
| 5464 ins_cost(125); | |
| 5465 | |
| 5466 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 3854 | 5467 ins_encode %{ |
| 5468 __ prefetchr($mem$$Address); | |
| 5469 %} | |
| 0 | 5470 ins_pipe(ialu_mem); |
| 5471 %} | |
| 5472 | |
| 5473 instruct prefetchrNTA( memory mem ) %{ | |
| 5474 predicate(ReadPrefetchInstr==0); | |
| 5475 match(PrefetchRead mem); | |
| 5476 ins_cost(125); | |
| 5477 | |
| 5478 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 3854 | 5479 ins_encode %{ |
| 5480 __ prefetchnta($mem$$Address); | |
| 5481 %} | |
| 0 | 5482 ins_pipe(ialu_mem); |
| 5483 %} | |
| 5484 | |
| 5485 instruct prefetchrT0( memory mem ) %{ | |
| 5486 predicate(ReadPrefetchInstr==1); | |
| 5487 match(PrefetchRead mem); | |
| 5488 ins_cost(125); | |
| 5489 | |
| 5490 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 3854 | 5491 ins_encode %{ |
| 5492 __ prefetcht0($mem$$Address); | |
| 5493 %} | |
| 0 | 5494 ins_pipe(ialu_mem); |
| 5495 %} | |
| 5496 | |
| 5497 instruct prefetchrT2( memory mem ) %{ | |
| 5498 predicate(ReadPrefetchInstr==2); | |
| 5499 match(PrefetchRead mem); | |
| 5500 ins_cost(125); | |
| 5501 | |
| 5502 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 3854 | 5503 ins_encode %{ |
| 5504 __ prefetcht2($mem$$Address); | |
| 5505 %} | |
| 0 | 5506 ins_pipe(ialu_mem); |
| 5507 %} | |
| 5508 | |
| 5509 instruct prefetchwNTA( memory mem ) %{ | |
| 5510 match(PrefetchWrite mem); | |
| 5511 ins_cost(125); | |
| 5512 | |
| 5513 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 3854 | 5514 ins_encode %{ |
| 5515 __ prefetchnta($mem$$Address); | |
| 5516 %} | |
| 0 | 5517 ins_pipe(ialu_mem); |
| 5518 %} | |
| 5519 | |
| 3854 | 5520 // Prefetch instructions for allocation. |
| 5521 | |
| 5522 instruct prefetchAlloc( memory mem ) %{ | |
| 5523 predicate(AllocatePrefetchInstr==3); | |
| 5524 match(PrefetchAllocation mem); | |
| 5525 ins_cost(125); | |
| 5526 | |
| 5527 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %} | |
| 5528 ins_encode %{ | |
| 5529 __ prefetchw($mem$$Address); | |
| 5530 %} | |
| 5531 ins_pipe(ialu_mem); | |
| 5532 %} | |
| 5533 | |
| 5534 instruct prefetchAllocNTA( memory mem ) %{ | |
| 5535 predicate(AllocatePrefetchInstr==0); | |
| 5536 match(PrefetchAllocation mem); | |
| 0 | 5537 ins_cost(125); |
| 5538 | |
| 3854 | 5539 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %} |
| 5540 ins_encode %{ | |
| 5541 __ prefetchnta($mem$$Address); | |
| 5542 %} | |
| 0 | 5543 ins_pipe(ialu_mem); |
| 5544 %} | |
| 5545 | |
| 3854 | 5546 instruct prefetchAllocT0( memory mem ) %{ |
| 5547 predicate(AllocatePrefetchInstr==1); | |
| 5548 match(PrefetchAllocation mem); | |
| 0 | 5549 ins_cost(125); |
| 5550 | |
| 3854 | 5551 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %} |
| 5552 ins_encode %{ | |
| 5553 __ prefetcht0($mem$$Address); | |
| 5554 %} | |
| 5555 ins_pipe(ialu_mem); | |
| 5556 %} | |
| 5557 | |
| 5558 instruct prefetchAllocT2( memory mem ) %{ | |
| 5559 predicate(AllocatePrefetchInstr==2); | |
| 5560 match(PrefetchAllocation mem); | |
| 5561 ins_cost(125); | |
| 5562 | |
| 5563 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %} | |
| 5564 ins_encode %{ | |
| 5565 __ prefetcht2($mem$$Address); | |
| 5566 %} | |
| 0 | 5567 ins_pipe(ialu_mem); |
| 5568 %} | |
| 5569 | |
| 5570 //----------Store Instructions------------------------------------------------- | |
| 5571 | |
| 5572 // Store Byte | |
| 5573 instruct storeB(memory mem, rRegI src) | |
| 5574 %{ | |
| 5575 match(Set mem (StoreB mem src)); | |
| 5576 | |
| 5577 ins_cost(125); // XXX | |
| 5578 format %{ "movb $mem, $src\t# byte" %} | |
| 5579 opcode(0x88); | |
| 5580 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5581 ins_pipe(ialu_mem_reg); | |
| 5582 %} | |
| 5583 | |
| 5584 // Store Char/Short | |
| 5585 instruct storeC(memory mem, rRegI src) | |
| 5586 %{ | |
| 5587 match(Set mem (StoreC mem src)); | |
| 5588 | |
| 5589 ins_cost(125); // XXX | |
| 5590 format %{ "movw $mem, $src\t# char/short" %} | |
| 5591 opcode(0x89); | |
| 5592 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5593 ins_pipe(ialu_mem_reg); | |
| 5594 %} | |
| 5595 | |
| 5596 // Store Integer | |
| 5597 instruct storeI(memory mem, rRegI src) | |
| 5598 %{ | |
| 5599 match(Set mem (StoreI mem src)); | |
| 5600 | |
| 5601 ins_cost(125); // XXX | |
| 5602 format %{ "movl $mem, $src\t# int" %} | |
| 5603 opcode(0x89); | |
| 5604 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 5605 ins_pipe(ialu_mem_reg); | |
| 5606 %} | |
| 5607 | |
| 5608 // Store Long | |
| 5609 instruct storeL(memory mem, rRegL src) | |
| 5610 %{ | |
| 5611 match(Set mem (StoreL mem src)); | |
| 5612 | |
| 5613 ins_cost(125); // XXX | |
| 5614 format %{ "movq $mem, $src\t# long" %} | |
| 5615 opcode(0x89); | |
| 5616 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5617 ins_pipe(ialu_mem_reg); // XXX | |
| 5618 %} | |
| 5619 | |
| 5620 // Store Pointer | |
| 5621 instruct storeP(memory mem, any_RegP src) | |
| 5622 %{ | |
| 5623 match(Set mem (StoreP mem src)); | |
| 5624 | |
| 5625 ins_cost(125); // XXX | |
| 5626 format %{ "movq $mem, $src\t# ptr" %} | |
| 5627 opcode(0x89); | |
| 5628 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 5629 ins_pipe(ialu_mem_reg); | |
| 5630 %} | |
| 5631 | |
|
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5632 instruct storeImmP0(memory mem, immP0 zero) |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
5633 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5634 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5635 match(Set mem (StoreP mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5636 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5637 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5638 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5639 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5640 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5641 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5642 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5643 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5644 |
| 0 | 5645 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 5646 instruct storeImmP(memory mem, immP31 src) | |
| 5647 %{ | |
| 5648 match(Set mem (StoreP mem src)); | |
| 5649 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5650 ins_cost(150); // XXX |
| 0 | 5651 format %{ "movq $mem, $src\t# ptr" %} |
| 5652 opcode(0xC7); /* C7 /0 */ | |
| 5653 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5654 ins_pipe(ialu_mem_imm); | |
| 5655 %} | |
| 5656 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5657 // Store Compressed Pointer |
| 163 | 5658 instruct storeN(memory mem, rRegN src) |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5659 %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5660 match(Set mem (StoreN mem src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5661 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5662 ins_cost(125); // XXX |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
5663 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5664 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5665 __ movl($mem$$Address, $src$$Register); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5666 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5667 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5668 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5669 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5670 instruct storeNKlass(memory mem, rRegN src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5671 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5672 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5673 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5674 ins_cost(125); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5675 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5676 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5677 __ movl($mem$$Address, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5678 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5679 ins_pipe(ialu_mem_reg); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5680 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5681 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5682 instruct storeImmN0(memory mem, immN0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5683 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5684 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5685 match(Set mem (StoreN mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5686 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5687 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5688 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5689 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5690 __ movl($mem$$Address, r12); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5691 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5692 ins_pipe(ialu_mem_reg); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5693 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
5694 |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5695 instruct storeImmN(memory mem, immN src) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5696 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5697 match(Set mem (StoreN mem src)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5698 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5699 ins_cost(150); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5700 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5701 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5702 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5703 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5704 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5705 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5706 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5707 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5708 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5709 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5710 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5711 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5712 instruct storeImmNKlass(memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5713 %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5714 match(Set mem (StoreNKlass mem src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5715 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5716 ins_cost(150); // XXX |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5717 format %{ "movl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5718 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5719 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5720 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5721 ins_pipe(ialu_mem_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5722 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5723 |
| 0 | 5724 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5725 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5726 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5727 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5728 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5729 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5730 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5731 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5732 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5733 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5734 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5735 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5736 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5737 |
| 0 | 5738 instruct storeImmI(memory mem, immI src) |
| 5739 %{ | |
| 5740 match(Set mem (StoreI mem src)); | |
| 5741 | |
| 5742 ins_cost(150); | |
| 5743 format %{ "movl $mem, $src\t# int" %} | |
| 5744 opcode(0xC7); /* C7 /0 */ | |
| 5745 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5746 ins_pipe(ialu_mem_imm); | |
| 5747 %} | |
| 5748 | |
| 5749 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5750 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5751 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5752 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5753 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5754 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5755 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5756 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5757 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5758 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5759 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5760 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5761 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5762 |
| 0 | 5763 instruct storeImmL(memory mem, immL32 src) |
| 5764 %{ | |
| 5765 match(Set mem (StoreL mem src)); | |
| 5766 | |
| 5767 ins_cost(150); | |
| 5768 format %{ "movq $mem, $src\t# long" %} | |
| 5769 opcode(0xC7); /* C7 /0 */ | |
| 5770 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 5771 ins_pipe(ialu_mem_imm); | |
| 5772 %} | |
| 5773 | |
| 5774 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5775 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5776 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5777 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5778 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5779 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5780 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5781 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5782 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5783 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5784 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5785 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5786 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5787 |
| 0 | 5788 instruct storeImmI16(memory mem, immI16 src) |
| 5789 %{ | |
| 5790 predicate(UseStoreImmI16); | |
| 5791 match(Set mem (StoreC mem src)); | |
| 5792 | |
| 5793 ins_cost(150); | |
| 5794 format %{ "movw $mem, $src\t# short/char" %} | |
| 5795 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 5796 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 5797 ins_pipe(ialu_mem_imm); | |
| 5798 %} | |
| 5799 | |
| 5800 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5801 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5802 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5803 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5804 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5805 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5806 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5807 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5808 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5809 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5810 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5811 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5812 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5813 |
| 0 | 5814 instruct storeImmB(memory mem, immI8 src) |
| 5815 %{ | |
| 5816 match(Set mem (StoreB mem src)); | |
| 5817 | |
| 5818 ins_cost(150); // XXX | |
| 5819 format %{ "movb $mem, $src\t# byte" %} | |
| 5820 opcode(0xC6); /* C6 /0 */ | |
| 5821 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5822 ins_pipe(ialu_mem_imm); | |
| 5823 %} | |
| 5824 | |
| 5825 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5826 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5827 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5828 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5829 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5830 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5831 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5832 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5833 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5834 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5835 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5836 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5837 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5838 |
| 0 | 5839 instruct storeImmCM0(memory mem, immI0 src) |
| 5840 %{ | |
| 5841 match(Set mem (StoreCM mem src)); | |
| 5842 | |
| 5843 ins_cost(150); // XXX | |
| 5844 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 5845 opcode(0xC6); /* C6 /0 */ | |
| 5846 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 5847 ins_pipe(ialu_mem_imm); | |
| 5848 %} | |
| 5849 | |
| 5850 // Store Float | |
| 5851 instruct storeF(memory mem, regF src) | |
| 5852 %{ | |
| 5853 match(Set mem (StoreF mem src)); | |
| 5854 | |
| 5855 ins_cost(95); // XXX | |
| 5856 format %{ "movss $mem, $src\t# float" %} | |
| 4759 | 5857 ins_encode %{ |
| 5858 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 5859 %} | |
| 0 | 5860 ins_pipe(pipe_slow); // XXX |
| 5861 %} | |
| 5862 | |
| 5863 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5864 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5865 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5866 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5867 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5868 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5869 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5870 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5871 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5872 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5873 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5874 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5875 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5876 |
| 0 | 5877 instruct storeF_imm(memory mem, immF src) |
| 5878 %{ | |
| 5879 match(Set mem (StoreF mem src)); | |
| 5880 | |
| 5881 ins_cost(50); | |
| 5882 format %{ "movl $mem, $src\t# float" %} | |
| 5883 opcode(0xC7); /* C7 /0 */ | |
| 5884 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5885 ins_pipe(ialu_mem_imm); | |
| 5886 %} | |
| 5887 | |
| 5888 // Store Double | |
| 5889 instruct storeD(memory mem, regD src) | |
| 5890 %{ | |
| 5891 match(Set mem (StoreD mem src)); | |
| 5892 | |
| 5893 ins_cost(95); // XXX | |
| 5894 format %{ "movsd $mem, $src\t# double" %} | |
| 4759 | 5895 ins_encode %{ |
| 5896 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 5897 %} | |
| 0 | 5898 ins_pipe(pipe_slow); // XXX |
| 5899 %} | |
| 5900 | |
| 5901 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 5902 instruct storeD0_imm(memory mem, immD0 src) | |
| 5903 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5904 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 5905 match(Set mem (StoreD mem src)); |
| 5906 | |
| 5907 ins_cost(50); | |
| 5908 format %{ "movq $mem, $src\t# double 0." %} | |
| 5909 opcode(0xC7); /* C7 /0 */ | |
| 5910 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 5911 ins_pipe(ialu_mem_imm); | |
| 5912 %} | |
| 5913 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5914 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5915 %{ |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
5916 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5917 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5918 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5919 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5920 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5921 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5922 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5923 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5924 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5925 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5926 |
| 0 | 5927 instruct storeSSI(stackSlotI dst, rRegI src) |
| 5928 %{ | |
| 5929 match(Set dst src); | |
| 5930 | |
| 5931 ins_cost(100); | |
| 5932 format %{ "movl $dst, $src\t# int stk" %} | |
| 5933 opcode(0x89); | |
| 5934 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 5935 ins_pipe( ialu_mem_reg ); | |
| 5936 %} | |
| 5937 | |
| 5938 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 5939 %{ | |
| 5940 match(Set dst src); | |
| 5941 | |
| 5942 ins_cost(100); | |
| 5943 format %{ "movq $dst, $src\t# long stk" %} | |
| 5944 opcode(0x89); | |
| 5945 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5946 ins_pipe(ialu_mem_reg); | |
| 5947 %} | |
| 5948 | |
| 5949 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 5950 %{ | |
| 5951 match(Set dst src); | |
| 5952 | |
| 5953 ins_cost(100); | |
| 5954 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 5955 opcode(0x89); | |
| 5956 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 5957 ins_pipe(ialu_mem_reg); | |
| 5958 %} | |
| 5959 | |
| 5960 instruct storeSSF(stackSlotF dst, regF src) | |
| 5961 %{ | |
| 5962 match(Set dst src); | |
| 5963 | |
| 5964 ins_cost(95); // XXX | |
| 5965 format %{ "movss $dst, $src\t# float stk" %} | |
| 4759 | 5966 ins_encode %{ |
| 5967 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5968 %} | |
| 0 | 5969 ins_pipe(pipe_slow); // XXX |
| 5970 %} | |
| 5971 | |
| 5972 instruct storeSSD(stackSlotD dst, regD src) | |
| 5973 %{ | |
| 5974 match(Set dst src); | |
| 5975 | |
| 5976 ins_cost(95); // XXX | |
| 5977 format %{ "movsd $dst, $src\t# double stk" %} | |
| 4759 | 5978 ins_encode %{ |
| 5979 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 5980 %} | |
| 0 | 5981 ins_pipe(pipe_slow); // XXX |
| 5982 %} | |
| 5983 | |
| 5984 //----------BSWAP Instructions------------------------------------------------- | |
| 5985 instruct bytes_reverse_int(rRegI dst) %{ | |
| 5986 match(Set dst (ReverseBytesI dst)); | |
| 5987 | |
| 5988 format %{ "bswapl $dst" %} | |
| 5989 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 5990 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 5991 ins_pipe( ialu_reg ); | |
| 5992 %} | |
| 5993 | |
| 5994 instruct bytes_reverse_long(rRegL dst) %{ | |
| 5995 match(Set dst (ReverseBytesL dst)); | |
| 5996 | |
| 5997 format %{ "bswapq $dst" %} | |
| 5998 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 5999 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 6000 ins_pipe( ialu_reg); | |
| 6001 %} | |
| 6002 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6003 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6004 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6005 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6006 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6007 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6008 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6009 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6010 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6011 __ shrl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6012 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6013 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6014 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6015 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6016 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6017 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6018 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6019 |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6020 format %{ "bswapl $dst\n\t" |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6021 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6022 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6023 __ bswapl($dst$$Register); |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6024 __ sarl($dst$$Register, 16); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6025 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6026 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6027 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
6028 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6029 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6030 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6031 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6032 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6033 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6034 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6035 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6036 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6037 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6038 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6039 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6040 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6041 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6042 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6043 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6044 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6045 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6046 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6047 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6048 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6049 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6050 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6051 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6052 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6053 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6054 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6055 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6056 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6057 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6058 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6059 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6060 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6061 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6062 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6063 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6064 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6065 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6066 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6067 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6068 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6069 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6070 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6071 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6072 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6073 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6074 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6075 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6076 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6077 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6078 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6079 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6080 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6081 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6082 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6083 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6084 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6085 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6086 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6087 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6088 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6089 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6090 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6091 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6092 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6093 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6094 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6095 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6096 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6097 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6098 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6099 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6100 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6101 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6102 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6103 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6104 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6105 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6106 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6107 match(Set dst (CountTrailingZerosI src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6108 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6109 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6110 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6111 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6112 __ tzcntl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6113 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6114 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6115 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6116 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6117 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6118 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6119 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6120 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6121 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6122 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6123 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6124 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6125 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6126 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6127 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6128 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6129 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6130 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6131 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6132 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6133 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6134 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6135 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6136 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6137 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6138 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6139 match(Set dst (CountTrailingZerosL src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6140 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6141 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6142 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6143 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6144 __ tzcntq($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6145 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6146 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6147 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6148 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6149 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
6150 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6151 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6152 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6153 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6154 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6155 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6156 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6157 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6158 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6159 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6160 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6161 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6162 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6163 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6164 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6165 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6166 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6167 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6168 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
6169 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6170 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6171 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6172 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6173 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6174 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6175 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6176 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6177 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6178 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6179 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6180 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6181 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6182 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6183 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6184 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6185 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6186 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6187 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6188 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6189 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6190 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6191 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6192 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6193 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6194 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6195 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6196 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6197 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6198 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6199 match(Set dst (PopCountL src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6200 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6201 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6202 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6203 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6204 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6205 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6206 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6207 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6208 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6209 // Note: Long.bitCount(long) returns an int. |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6210 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6211 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6212 match(Set dst (PopCountL (LoadL mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
6213 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6214 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6215 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6216 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6217 __ popcntq($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6218 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6219 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6220 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6221 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
6222 |
| 0 | 6223 //----------MemBar Instructions----------------------------------------------- |
| 6224 // Memory barrier flavors | |
| 6225 | |
| 6226 instruct membar_acquire() | |
| 6227 %{ | |
| 6228 match(MemBarAcquire); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6229 match(LoadFence); |
| 0 | 6230 ins_cost(0); |
| 6231 | |
| 6232 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6233 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 6234 ins_encode(); |
| 6235 ins_pipe(empty); | |
| 6236 %} | |
| 6237 | |
| 6238 instruct membar_acquire_lock() | |
| 6239 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6240 match(MemBarAcquireLock); |
| 0 | 6241 ins_cost(0); |
| 6242 | |
| 6243 size(0); | |
| 6244 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6245 ins_encode(); | |
| 6246 ins_pipe(empty); | |
| 6247 %} | |
| 6248 | |
| 6249 instruct membar_release() | |
| 6250 %{ | |
| 6251 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6252 match(StoreFence); |
| 0 | 6253 ins_cost(0); |
| 6254 | |
| 6255 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6256 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 6257 ins_encode(); |
| 6258 ins_pipe(empty); | |
| 6259 %} | |
| 6260 | |
| 6261 instruct membar_release_lock() | |
| 6262 %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6263 match(MemBarReleaseLock); |
| 0 | 6264 ins_cost(0); |
| 6265 | |
| 6266 size(0); | |
| 6267 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6268 ins_encode(); | |
| 6269 ins_pipe(empty); | |
| 6270 %} | |
| 6271 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6272 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 6273 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6274 effect(KILL cr); |
| 0 | 6275 ins_cost(400); |
| 6276 | |
|
2404
b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
2401
diff
changeset
|
6277 format %{ |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6278 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6279 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6280 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6281 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6282 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6283 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6284 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6285 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6286 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6287 %} |
| 0 | 6288 ins_pipe(pipe_slow); |
| 6289 %} | |
| 6290 | |
| 6291 instruct unnecessary_membar_volatile() | |
| 6292 %{ | |
| 6293 match(MemBarVolatile); | |
| 6294 predicate(Matcher::post_store_load_barrier(n)); | |
| 6295 ins_cost(0); | |
| 6296 | |
| 6297 size(0); | |
| 6298 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6299 ins_encode(); | |
| 6300 ins_pipe(empty); | |
| 6301 %} | |
| 6302 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6303 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6304 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6305 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6306 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6307 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6308 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6309 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6310 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6311 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4762
diff
changeset
|
6312 |
| 0 | 6313 //----------Move Instructions-------------------------------------------------- |
| 6314 | |
| 6315 instruct castX2P(rRegP dst, rRegL src) | |
| 6316 %{ | |
| 6317 match(Set dst (CastX2P src)); | |
| 6318 | |
| 6319 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 4759 | 6320 ins_encode %{ |
| 6321 if ($dst$$reg != $src$$reg) { | |
| 6322 __ movptr($dst$$Register, $src$$Register); | |
| 6323 } | |
| 6324 %} | |
| 0 | 6325 ins_pipe(ialu_reg_reg); // XXX |
| 6326 %} | |
| 6327 | |
| 6328 instruct castP2X(rRegL dst, rRegP src) | |
| 6329 %{ | |
| 6330 match(Set dst (CastP2X src)); | |
| 6331 | |
| 6332 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 4759 | 6333 ins_encode %{ |
| 6334 if ($dst$$reg != $src$$reg) { | |
| 6335 __ movptr($dst$$Register, $src$$Register); | |
| 6336 } | |
| 6337 %} | |
| 0 | 6338 ins_pipe(ialu_reg_reg); // XXX |
| 6339 %} | |
| 6340 | |
|
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6341 // Convert oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6342 instruct convP2I(rRegI dst, rRegP src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6343 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6344 match(Set dst (ConvL2I (CastP2X src))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6345 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6346 format %{ "movl $dst, $src\t# ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6347 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6348 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6349 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6350 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6351 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6352 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6353 // Convert compressed oop into int for vectors alignment masking |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6354 // in case of 32bit oops (heap < 4Gb). |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6355 instruct convN2I(rRegI dst, rRegN src) |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6356 %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6357 predicate(Universe::narrow_oop_shift() == 0); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6358 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6359 |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6360 format %{ "movl $dst, $src\t# compressed ptr -> int" %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6361 ins_encode %{ |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6362 __ movl($dst$$Register, $src$$Register); |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6363 %} |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6364 ins_pipe(ialu_reg_reg); // XXX |
|
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6179
diff
changeset
|
6365 %} |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6366 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6367 // Convert oop pointer into compressed form |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6368 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6369 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6370 match(Set dst (EncodeP src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6371 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6372 format %{ "encode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6373 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6374 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6375 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6376 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6377 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6378 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6379 __ encode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6380 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6381 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6382 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6383 |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6384 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
182
diff
changeset
|
6385 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6386 match(Set dst (EncodeP src)); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6387 effect(KILL cr); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6388 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6389 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6390 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6391 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6392 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6393 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6394 |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6395 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6396 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull && |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6397 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6398 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6399 effect(KILL cr); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6400 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6401 ins_encode %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6402 Register s = $src$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6403 Register d = $dst$$Register; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6404 if (s != d) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6405 __ movq(d, s); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6406 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6407 __ decode_heap_oop(d); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6408 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6409 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6410 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6411 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6412 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6413 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull || |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
6414 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6415 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
6416 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6417 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6418 ins_encode %{ |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6419 Register s = $src$$Register; |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6420 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6421 if (s != d) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6422 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6423 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6424 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6425 } |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6426 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6427 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6428 %} |
|
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6429 |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6430 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6431 match(Set dst (EncodePKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6432 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6433 format %{ "encode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6434 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6435 __ encode_klass_not_null($dst$$Register, $src$$Register); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6436 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6437 ins_pipe(ialu_reg_long); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6438 %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6439 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6440 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6441 match(Set dst (DecodeNKlass src)); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6442 effect(KILL cr); |
|
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
parents:
10171
diff
changeset
|
6443 format %{ "decode_klass_not_null $dst,$src" %} |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6444 ins_encode %{ |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6445 Register s = $src$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6446 Register d = $dst$$Register; |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
6447 if (s != d) { |
|
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|
6448 __ decode_klass_not_null(d, s); |
|
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|
6449 } else { |
|
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|
6450 __ decode_klass_not_null(d); |
|
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|
6451 } |
|
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|
6452 %} |
|
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diff
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|
6453 ins_pipe(ialu_reg_long); |
|
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|
6454 %} |
|
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|
6455 |
|
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|
6456 |
| 0 | 6457 //----------Conditional Move--------------------------------------------------- |
| 6458 // Jump | |
| 6459 // dummy instruction for generating temp registers | |
| 6460 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 6461 match(Jump (LShiftL switch_val shift)); | |
| 6462 ins_cost(350); | |
| 6463 predicate(false); | |
| 6464 effect(TEMP dest); | |
| 6465 | |
| 2008 | 6466 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6467 "jmp [$dest + $switch_val << $shift]\n\t" %} |
| 2008 | 6468 ins_encode %{ |
| 6469 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6470 // to do that and the compiler is using that register as one it can allocate. | |
| 6471 // So we build it all by hand. | |
| 6472 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 6473 // ArrayAddress dispatch(table, index); | |
| 6474 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant); | |
| 6475 __ lea($dest$$Register, $constantaddress); | |
| 6476 __ jmp(dispatch); | |
| 6477 %} | |
| 0 | 6478 ins_pipe(pipe_jmp); |
| 6479 %} | |
| 6480 | |
| 6481 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 6482 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 6483 ins_cost(350); | |
| 6484 effect(TEMP dest); | |
| 6485 | |
| 2008 | 6486 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6487 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} |
| 2008 | 6488 ins_encode %{ |
| 6489 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6490 // to do that and the compiler is using that register as one it can allocate. | |
| 6491 // So we build it all by hand. | |
| 6492 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6493 // ArrayAddress dispatch(table, index); | |
| 6494 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant); | |
| 6495 __ lea($dest$$Register, $constantaddress); | |
| 6496 __ jmp(dispatch); | |
| 6497 %} | |
| 0 | 6498 ins_pipe(pipe_jmp); |
| 6499 %} | |
| 6500 | |
| 6501 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 6502 match(Jump switch_val); | |
| 6503 ins_cost(350); | |
| 6504 effect(TEMP dest); | |
| 6505 | |
| 2008 | 6506 format %{ "leaq $dest, [$constantaddress]\n\t" |
| 0 | 6507 "jmp [$dest + $switch_val]\n\t" %} |
| 2008 | 6508 ins_encode %{ |
| 6509 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 6510 // to do that and the compiler is using that register as one it can allocate. | |
| 6511 // So we build it all by hand. | |
| 6512 // Address index(noreg, switch_reg, Address::times_1); | |
| 6513 // ArrayAddress dispatch(table, index); | |
| 6514 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1); | |
| 6515 __ lea($dest$$Register, $constantaddress); | |
| 6516 __ jmp(dispatch); | |
| 6517 %} | |
| 0 | 6518 ins_pipe(pipe_jmp); |
| 6519 %} | |
| 6520 | |
| 6521 // Conditional move | |
| 6522 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 6523 %{ | |
| 6524 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6525 | |
| 6526 ins_cost(200); // XXX | |
| 6527 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6528 opcode(0x0F, 0x40); | |
| 6529 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6530 ins_pipe(pipe_cmov_reg); | |
| 6531 %} | |
| 6532 | |
|
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6533 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 6534 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 6535 | |
| 6536 ins_cost(200); // XXX | |
| 6537 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6538 opcode(0x0F, 0x40); | |
| 6539 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6540 ins_pipe(pipe_cmov_reg); | |
| 6541 %} | |
| 6542 | |
|
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6543 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
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|
6544 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
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|
6545 ins_cost(200); |
|
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|
6546 expand %{ |
|
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|
6547 cmovI_regU(cop, cr, dst, src); |
|
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|
6548 %} |
|
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|
6549 %} |
|
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|
6550 |
| 0 | 6551 // Conditional move |
|
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6552 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6553 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 6554 | |
| 6555 ins_cost(250); // XXX | |
| 6556 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 6557 opcode(0x0F, 0x40); | |
| 6558 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6559 ins_pipe(pipe_cmov_mem); | |
| 6560 %} | |
| 6561 | |
| 6562 // Conditional move | |
| 6563 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 6564 %{ | |
| 6565 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6566 | |
| 6567 ins_cost(250); // XXX | |
| 6568 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 6569 opcode(0x0F, 0x40); | |
| 6570 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6571 ins_pipe(pipe_cmov_mem); | |
| 6572 %} | |
| 6573 | |
|
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6574 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
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6575 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
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|
6576 ins_cost(250); |
|
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|
6577 expand %{ |
|
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|
6578 cmovI_memU(cop, cr, dst, src); |
|
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|
6579 %} |
|
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|
6580 %} |
|
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|
6581 |
| 0 | 6582 // Conditional move |
|
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6583 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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6584 %{ |
|
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6585 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
6586 |
|
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|
6587 ins_cost(200); // XXX |
|
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6588 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
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|
6589 opcode(0x0F, 0x40); |
|
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6590 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
6591 ins_pipe(pipe_cmov_reg); |
|
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|
6592 %} |
|
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|
6593 |
|
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|
6594 // Conditional move |
|
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6595 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
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|
6596 %{ |
|
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|
6597 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
6598 |
|
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|
6599 ins_cost(200); // XXX |
|
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|
6600 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
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|
6601 opcode(0x0F, 0x40); |
|
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|
6602 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
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|
6603 ins_pipe(pipe_cmov_reg); |
|
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|
6604 %} |
|
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|
6605 |
|
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|
6606 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
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|
6607 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
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|
6608 ins_cost(200); |
|
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|
6609 expand %{ |
|
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|
6610 cmovN_regU(cop, cr, dst, src); |
|
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|
6611 %} |
|
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|
6612 %} |
|
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|
6613 |
|
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|
6614 // Conditional move |
| 0 | 6615 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 6616 %{ | |
| 6617 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6618 | |
| 6619 ins_cost(200); // XXX | |
| 6620 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 6621 opcode(0x0F, 0x40); | |
| 6622 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6623 ins_pipe(pipe_cmov_reg); // XXX | |
| 6624 %} | |
| 6625 | |
| 6626 // Conditional move | |
|
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|
6627 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 6628 %{ |
| 6629 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6630 | |
| 6631 ins_cost(200); // XXX | |
| 6632 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 6633 opcode(0x0F, 0x40); | |
| 6634 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6635 ins_pipe(pipe_cmov_reg); // XXX | |
| 6636 %} | |
| 6637 | |
|
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|
6638 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
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|
6639 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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|
6640 ins_cost(200); |
|
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diff
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|
6641 expand %{ |
|
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|
6642 cmovP_regU(cop, cr, dst, src); |
|
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|
6643 %} |
|
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|
6644 %} |
|
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|
6645 |
| 0 | 6646 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6647 // correctly meets the two pointer arguments; one is an incoming | |
| 6648 // register but the other is a memory operand. ALSO appears to | |
| 6649 // be buggy with implicit null checks. | |
| 6650 // | |
| 6651 //// Conditional move | |
| 6652 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 6653 //%{ | |
| 6654 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6655 // ins_cost(250); | |
| 6656 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6657 // opcode(0x0F,0x40); | |
| 6658 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6659 // ins_pipe( pipe_cmov_mem ); | |
| 6660 //%} | |
| 6661 // | |
| 6662 //// Conditional move | |
| 6663 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 6664 //%{ | |
| 6665 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6666 // ins_cost(250); | |
| 6667 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6668 // opcode(0x0F,0x40); | |
| 6669 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 6670 // ins_pipe( pipe_cmov_mem ); | |
| 6671 //%} | |
| 6672 | |
| 6673 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 6674 %{ | |
| 6675 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6676 | |
| 6677 ins_cost(200); // XXX | |
| 6678 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6679 opcode(0x0F, 0x40); | |
| 6680 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6681 ins_pipe(pipe_cmov_reg); // XXX | |
| 6682 %} | |
| 6683 | |
| 6684 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 6685 %{ | |
| 6686 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6687 | |
| 6688 ins_cost(200); // XXX | |
| 6689 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 6690 opcode(0x0F, 0x40); | |
| 6691 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6692 ins_pipe(pipe_cmov_mem); // XXX | |
| 6693 %} | |
| 6694 | |
| 6695 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 6696 %{ | |
| 6697 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6698 | |
| 6699 ins_cost(200); // XXX | |
| 6700 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6701 opcode(0x0F, 0x40); | |
| 6702 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 6703 ins_pipe(pipe_cmov_reg); // XXX | |
| 6704 %} | |
| 6705 | |
|
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|
6706 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
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|
6707 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
6708 ins_cost(200); |
|
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diff
changeset
|
6709 expand %{ |
|
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diff
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|
6710 cmovL_regU(cop, cr, dst, src); |
|
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|
6711 %} |
|
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|
6712 %} |
|
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|
6713 |
| 0 | 6714 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 6715 %{ | |
| 6716 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6717 | |
| 6718 ins_cost(200); // XXX | |
| 6719 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 6720 opcode(0x0F, 0x40); | |
| 6721 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 6722 ins_pipe(pipe_cmov_mem); // XXX | |
| 6723 %} | |
| 6724 | |
|
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|
6725 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
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|
6726 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
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|
6727 ins_cost(200); |
|
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diff
changeset
|
6728 expand %{ |
|
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diff
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|
6729 cmovL_memU(cop, cr, dst, src); |
|
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|
6730 %} |
|
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|
6731 %} |
|
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|
6732 |
| 0 | 6733 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 6734 %{ | |
| 6735 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6736 | |
| 6737 ins_cost(200); // XXX | |
| 6738 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6739 "movss $dst, $src\n" | |
| 6740 "skip:" %} | |
| 4759 | 6741 ins_encode %{ |
| 6742 Label Lskip; | |
| 6743 // Invert sense of branch from sense of CMOV | |
| 6744 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6745 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6746 __ bind(Lskip); | |
| 6747 %} | |
| 0 | 6748 ins_pipe(pipe_slow); |
| 6749 %} | |
| 6750 | |
| 6751 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 6752 // %{ | |
| 6753 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 6754 | |
| 6755 // ins_cost(200); // XXX | |
| 6756 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 6757 // "movss $dst, $src\n" | |
| 6758 // "skip:" %} | |
| 6759 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 6760 // ins_pipe(pipe_slow); | |
| 6761 // %} | |
| 6762 | |
| 6763 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 6764 %{ | |
| 6765 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6766 | |
| 6767 ins_cost(200); // XXX | |
| 6768 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 6769 "movss $dst, $src\n" | |
| 6770 "skip:" %} | |
| 4759 | 6771 ins_encode %{ |
| 6772 Label Lskip; | |
| 6773 // Invert sense of branch from sense of CMOV | |
| 6774 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6775 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6776 __ bind(Lskip); | |
| 6777 %} | |
| 0 | 6778 ins_pipe(pipe_slow); |
| 6779 %} | |
| 6780 | |
|
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|
6781 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
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|
6782 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
6783 ins_cost(200); |
|
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diff
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|
6784 expand %{ |
|
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|
6785 cmovF_regU(cop, cr, dst, src); |
|
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|
6786 %} |
|
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|
6787 %} |
|
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diff
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|
6788 |
| 0 | 6789 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 6790 %{ | |
| 6791 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6792 | |
| 6793 ins_cost(200); // XXX | |
| 6794 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 6795 "movsd $dst, $src\n" | |
| 6796 "skip:" %} | |
| 4759 | 6797 ins_encode %{ |
| 6798 Label Lskip; | |
| 6799 // Invert sense of branch from sense of CMOV | |
| 6800 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6801 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6802 __ bind(Lskip); | |
| 6803 %} | |
| 0 | 6804 ins_pipe(pipe_slow); |
| 6805 %} | |
| 6806 | |
| 6807 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 6808 %{ | |
| 6809 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6810 | |
| 6811 ins_cost(200); // XXX | |
| 6812 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 6813 "movsd $dst, $src\n" | |
| 6814 "skip:" %} | |
| 4759 | 6815 ins_encode %{ |
| 6816 Label Lskip; | |
| 6817 // Invert sense of branch from sense of CMOV | |
| 6818 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6819 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6820 __ bind(Lskip); | |
| 6821 %} | |
| 0 | 6822 ins_pipe(pipe_slow); |
| 6823 %} | |
| 6824 | |
|
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|
6825 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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changeset
|
6826 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
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|
6827 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
6828 expand %{ |
|
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diff
changeset
|
6829 cmovD_regU(cop, cr, dst, src); |
|
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diff
changeset
|
6830 %} |
|
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parents:
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|
6831 %} |
|
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|
6832 |
| 0 | 6833 //----------Arithmetic Instructions-------------------------------------------- |
| 6834 //----------Addition Instructions---------------------------------------------- | |
| 6835 | |
| 6836 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 6837 %{ | |
| 6838 match(Set dst (AddI dst src)); | |
| 6839 effect(KILL cr); | |
| 6840 | |
| 6841 format %{ "addl $dst, $src\t# int" %} | |
| 6842 opcode(0x03); | |
| 6843 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 6844 ins_pipe(ialu_reg_reg); | |
| 6845 %} | |
| 6846 | |
| 6847 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 6848 %{ | |
| 6849 match(Set dst (AddI dst src)); | |
| 6850 effect(KILL cr); | |
| 6851 | |
| 6852 format %{ "addl $dst, $src\t# int" %} | |
| 6853 opcode(0x81, 0x00); /* /0 id */ | |
| 6854 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 6855 ins_pipe( ialu_reg ); | |
| 6856 %} | |
| 6857 | |
| 6858 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 6859 %{ | |
| 6860 match(Set dst (AddI dst (LoadI src))); | |
| 6861 effect(KILL cr); | |
| 6862 | |
| 6863 ins_cost(125); // XXX | |
| 6864 format %{ "addl $dst, $src\t# int" %} | |
| 6865 opcode(0x03); | |
| 6866 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6867 ins_pipe(ialu_reg_mem); | |
| 6868 %} | |
| 6869 | |
| 6870 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 6871 %{ | |
| 6872 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6873 effect(KILL cr); | |
| 6874 | |
| 6875 ins_cost(150); // XXX | |
| 6876 format %{ "addl $dst, $src\t# int" %} | |
| 6877 opcode(0x01); /* Opcode 01 /r */ | |
| 6878 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 6879 ins_pipe(ialu_mem_reg); | |
| 6880 %} | |
| 6881 | |
| 6882 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 6883 %{ | |
| 6884 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6885 effect(KILL cr); | |
| 6886 | |
| 6887 ins_cost(125); // XXX | |
| 6888 format %{ "addl $dst, $src\t# int" %} | |
| 6889 opcode(0x81); /* Opcode 81 /0 id */ | |
| 6890 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 6891 ins_pipe(ialu_mem_imm); | |
| 6892 %} | |
| 6893 | |
| 6894 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 6895 %{ | |
| 6896 predicate(UseIncDec); | |
| 6897 match(Set dst (AddI dst src)); | |
| 6898 effect(KILL cr); | |
| 6899 | |
| 6900 format %{ "incl $dst\t# int" %} | |
| 6901 opcode(0xFF, 0x00); // FF /0 | |
| 6902 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6903 ins_pipe(ialu_reg); | |
| 6904 %} | |
| 6905 | |
| 6906 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 6907 %{ | |
| 6908 predicate(UseIncDec); | |
| 6909 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6910 effect(KILL cr); | |
| 6911 | |
| 6912 ins_cost(125); // XXX | |
| 6913 format %{ "incl $dst\t# int" %} | |
| 6914 opcode(0xFF); /* Opcode FF /0 */ | |
| 6915 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 6916 ins_pipe(ialu_mem_imm); | |
| 6917 %} | |
| 6918 | |
| 6919 // XXX why does that use AddI | |
| 6920 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 6921 %{ | |
| 6922 predicate(UseIncDec); | |
| 6923 match(Set dst (AddI dst src)); | |
| 6924 effect(KILL cr); | |
| 6925 | |
| 6926 format %{ "decl $dst\t# int" %} | |
| 6927 opcode(0xFF, 0x01); // FF /1 | |
| 6928 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 6929 ins_pipe(ialu_reg); | |
| 6930 %} | |
| 6931 | |
| 6932 // XXX why does that use AddI | |
| 6933 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 6934 %{ | |
| 6935 predicate(UseIncDec); | |
| 6936 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 6937 effect(KILL cr); | |
| 6938 | |
| 6939 ins_cost(125); // XXX | |
| 6940 format %{ "decl $dst\t# int" %} | |
| 6941 opcode(0xFF); /* Opcode FF /1 */ | |
| 6942 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 6943 ins_pipe(ialu_mem_imm); | |
| 6944 %} | |
| 6945 | |
| 6946 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 6947 %{ | |
| 6948 match(Set dst (AddI src0 src1)); | |
| 6949 | |
| 6950 ins_cost(110); | |
| 6951 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 6952 opcode(0x8D); /* 0x8D /r */ | |
| 6953 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 6954 ins_pipe(ialu_reg_reg); | |
| 6955 %} | |
| 6956 | |
| 6957 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 6958 %{ | |
| 6959 match(Set dst (AddL dst src)); | |
| 6960 effect(KILL cr); | |
| 6961 | |
| 6962 format %{ "addq $dst, $src\t# long" %} | |
| 6963 opcode(0x03); | |
| 6964 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 6965 ins_pipe(ialu_reg_reg); | |
| 6966 %} | |
| 6967 | |
| 6968 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 6969 %{ | |
| 6970 match(Set dst (AddL dst src)); | |
| 6971 effect(KILL cr); | |
| 6972 | |
| 6973 format %{ "addq $dst, $src\t# long" %} | |
| 6974 opcode(0x81, 0x00); /* /0 id */ | |
| 6975 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 6976 ins_pipe( ialu_reg ); | |
| 6977 %} | |
| 6978 | |
| 6979 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 6980 %{ | |
| 6981 match(Set dst (AddL dst (LoadL src))); | |
| 6982 effect(KILL cr); | |
| 6983 | |
| 6984 ins_cost(125); // XXX | |
| 6985 format %{ "addq $dst, $src\t# long" %} | |
| 6986 opcode(0x03); | |
| 6987 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6988 ins_pipe(ialu_reg_mem); | |
| 6989 %} | |
| 6990 | |
| 6991 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 6992 %{ | |
| 6993 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 6994 effect(KILL cr); | |
| 6995 | |
| 6996 ins_cost(150); // XXX | |
| 6997 format %{ "addq $dst, $src\t# long" %} | |
| 6998 opcode(0x01); /* Opcode 01 /r */ | |
| 6999 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7000 ins_pipe(ialu_mem_reg); | |
| 7001 %} | |
| 7002 | |
| 7003 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7004 %{ | |
| 7005 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7006 effect(KILL cr); | |
| 7007 | |
| 7008 ins_cost(125); // XXX | |
| 7009 format %{ "addq $dst, $src\t# long" %} | |
| 7010 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7011 ins_encode(REX_mem_wide(dst), | |
| 7012 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 7013 ins_pipe(ialu_mem_imm); | |
| 7014 %} | |
| 7015 | |
| 7016 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 7017 %{ | |
| 7018 predicate(UseIncDec); | |
| 7019 match(Set dst (AddL dst src)); | |
| 7020 effect(KILL cr); | |
| 7021 | |
| 7022 format %{ "incq $dst\t# long" %} | |
| 7023 opcode(0xFF, 0x00); // FF /0 | |
| 7024 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7025 ins_pipe(ialu_reg); | |
| 7026 %} | |
| 7027 | |
| 7028 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 7029 %{ | |
| 7030 predicate(UseIncDec); | |
| 7031 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7032 effect(KILL cr); | |
| 7033 | |
| 7034 ins_cost(125); // XXX | |
| 7035 format %{ "incq $dst\t# long" %} | |
| 7036 opcode(0xFF); /* Opcode FF /0 */ | |
| 7037 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 7038 ins_pipe(ialu_mem_imm); | |
| 7039 %} | |
| 7040 | |
| 7041 // XXX why does that use AddL | |
| 7042 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 7043 %{ | |
| 7044 predicate(UseIncDec); | |
| 7045 match(Set dst (AddL dst src)); | |
| 7046 effect(KILL cr); | |
| 7047 | |
| 7048 format %{ "decq $dst\t# long" %} | |
| 7049 opcode(0xFF, 0x01); // FF /1 | |
| 7050 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7051 ins_pipe(ialu_reg); | |
| 7052 %} | |
| 7053 | |
| 7054 // XXX why does that use AddL | |
| 7055 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 7056 %{ | |
| 7057 predicate(UseIncDec); | |
| 7058 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 7059 effect(KILL cr); | |
| 7060 | |
| 7061 ins_cost(125); // XXX | |
| 7062 format %{ "decq $dst\t# long" %} | |
| 7063 opcode(0xFF); /* Opcode FF /1 */ | |
| 7064 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 7065 ins_pipe(ialu_mem_imm); | |
| 7066 %} | |
| 7067 | |
| 7068 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 7069 %{ | |
| 7070 match(Set dst (AddL src0 src1)); | |
| 7071 | |
| 7072 ins_cost(110); | |
| 7073 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 7074 opcode(0x8D); /* 0x8D /r */ | |
| 7075 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 7076 ins_pipe(ialu_reg_reg); | |
| 7077 %} | |
| 7078 | |
| 7079 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 7080 %{ | |
| 7081 match(Set dst (AddP dst src)); | |
| 7082 effect(KILL cr); | |
| 7083 | |
| 7084 format %{ "addq $dst, $src\t# ptr" %} | |
| 7085 opcode(0x03); | |
| 7086 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7087 ins_pipe(ialu_reg_reg); | |
| 7088 %} | |
| 7089 | |
| 7090 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 7091 %{ | |
| 7092 match(Set dst (AddP dst src)); | |
| 7093 effect(KILL cr); | |
| 7094 | |
| 7095 format %{ "addq $dst, $src\t# ptr" %} | |
| 7096 opcode(0x81, 0x00); /* /0 id */ | |
| 7097 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7098 ins_pipe( ialu_reg ); | |
| 7099 %} | |
| 7100 | |
| 7101 // XXX addP mem ops ???? | |
| 7102 | |
| 7103 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 7104 %{ | |
| 7105 match(Set dst (AddP src0 src1)); | |
| 7106 | |
| 7107 ins_cost(110); | |
| 7108 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 7109 opcode(0x8D); /* 0x8D /r */ | |
| 7110 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 7111 ins_pipe(ialu_reg_reg); | |
| 7112 %} | |
| 7113 | |
| 7114 instruct checkCastPP(rRegP dst) | |
| 7115 %{ | |
| 7116 match(Set dst (CheckCastPP dst)); | |
| 7117 | |
| 7118 size(0); | |
| 7119 format %{ "# checkcastPP of $dst" %} | |
| 7120 ins_encode(/* empty encoding */); | |
| 7121 ins_pipe(empty); | |
| 7122 %} | |
| 7123 | |
| 7124 instruct castPP(rRegP dst) | |
| 7125 %{ | |
| 7126 match(Set dst (CastPP dst)); | |
| 7127 | |
| 7128 size(0); | |
| 7129 format %{ "# castPP of $dst" %} | |
| 7130 ins_encode(/* empty encoding */); | |
| 7131 ins_pipe(empty); | |
| 7132 %} | |
| 7133 | |
| 7134 instruct castII(rRegI dst) | |
| 7135 %{ | |
| 7136 match(Set dst (CastII dst)); | |
| 7137 | |
| 7138 size(0); | |
| 7139 format %{ "# castII of $dst" %} | |
| 7140 ins_encode(/* empty encoding */); | |
| 7141 ins_cost(0); | |
| 7142 ins_pipe(empty); | |
| 7143 %} | |
| 7144 | |
| 7145 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 7146 instruct loadPLocked(rRegP dst, memory mem) | |
| 7147 %{ | |
| 7148 match(Set dst (LoadPLocked mem)); | |
| 7149 | |
| 7150 ins_cost(125); // XXX | |
| 7151 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 7152 opcode(0x8B); | |
| 7153 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 7154 ins_pipe(ialu_reg_mem); // XXX | |
| 7155 %} | |
| 7156 | |
| 7157 // Conditional-store of the updated heap-top. | |
| 7158 // Used during allocation of the shared heap. | |
| 7159 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7160 | |
| 7161 instruct storePConditional(memory heap_top_ptr, | |
| 7162 rax_RegP oldval, rRegP newval, | |
| 7163 rFlagsReg cr) | |
| 7164 %{ | |
| 7165 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
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7166 |
| 0 | 7167 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 7168 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 7169 opcode(0x0F, 0xB1); | |
| 7170 ins_encode(lock_prefix, | |
| 7171 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 7172 OpcP, OpcS, | |
| 7173 reg_mem(newval, heap_top_ptr)); | |
| 7174 ins_pipe(pipe_cmpxchg); | |
| 7175 %} | |
| 7176 | |
|
420
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|
7177 // Conditional-store of an int value. |
|
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|
7178 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
a1980da045cc
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|
7179 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7180 %{ |
|
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|
7181 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
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|
7182 effect(KILL oldval); |
|
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6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7183 |
|
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6462850: generate biased locking code in C2 ideal graph
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changeset
|
7184 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7185 opcode(0x0F, 0xB1); |
| 7186 ins_encode(lock_prefix, | |
|
420
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|
7187 REX_reg_mem(newval, mem), |
| 0 | 7188 OpcP, OpcS, |
|
420
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changeset
|
7189 reg_mem(newval, mem)); |
| 0 | 7190 ins_pipe(pipe_cmpxchg); |
| 7191 %} | |
| 7192 | |
|
420
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|
7193 // Conditional-store of a long value. |
|
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|
7194 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
a1980da045cc
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|
7195 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7196 %{ |
|
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6462850: generate biased locking code in C2 ideal graph
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|
7197 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7198 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7199 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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changeset
|
7200 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 7201 opcode(0x0F, 0xB1); |
| 7202 ins_encode(lock_prefix, | |
|
420
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|
7203 REX_reg_mem_wide(newval, mem), |
| 0 | 7204 OpcP, OpcS, |
|
420
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|
7205 reg_mem(newval, mem)); |
| 0 | 7206 ins_pipe(pipe_cmpxchg); |
| 7207 %} | |
| 7208 | |
|
420
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|
7209 |
|
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changeset
|
7210 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 7211 instruct compareAndSwapP(rRegI res, |
| 7212 memory mem_ptr, | |
| 7213 rax_RegP oldval, rRegP newval, | |
| 7214 rFlagsReg cr) | |
| 7215 %{ | |
|
6795
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|
7216 predicate(VM_Version::supports_cx8()); |
| 0 | 7217 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7218 effect(KILL cr, KILL oldval); | |
| 7219 | |
| 7220 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7221 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7222 "sete $res\n\t" | |
| 7223 "movzbl $res, $res" %} | |
| 7224 opcode(0x0F, 0xB1); | |
| 7225 ins_encode(lock_prefix, | |
| 7226 REX_reg_mem_wide(newval, mem_ptr), | |
| 7227 OpcP, OpcS, | |
| 7228 reg_mem(newval, mem_ptr), | |
| 7229 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7230 REX_reg_breg(res, res), // movzbl | |
| 7231 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7232 ins_pipe( pipe_cmpxchg ); | |
| 7233 %} | |
| 7234 | |
| 7235 instruct compareAndSwapL(rRegI res, | |
| 7236 memory mem_ptr, | |
| 7237 rax_RegL oldval, rRegL newval, | |
| 7238 rFlagsReg cr) | |
| 7239 %{ | |
|
6795
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|
7240 predicate(VM_Version::supports_cx8()); |
| 0 | 7241 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7242 effect(KILL cr, KILL oldval); | |
| 7243 | |
| 7244 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 7245 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7246 "sete $res\n\t" | |
| 7247 "movzbl $res, $res" %} | |
| 7248 opcode(0x0F, 0xB1); | |
| 7249 ins_encode(lock_prefix, | |
| 7250 REX_reg_mem_wide(newval, mem_ptr), | |
| 7251 OpcP, OpcS, | |
| 7252 reg_mem(newval, mem_ptr), | |
| 7253 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7254 REX_reg_breg(res, res), // movzbl | |
| 7255 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7256 ins_pipe( pipe_cmpxchg ); | |
| 7257 %} | |
| 7258 | |
| 7259 instruct compareAndSwapI(rRegI res, | |
| 7260 memory mem_ptr, | |
| 7261 rax_RegI oldval, rRegI newval, | |
| 7262 rFlagsReg cr) | |
| 7263 %{ | |
| 7264 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7265 effect(KILL cr, KILL oldval); | |
| 7266 | |
| 7267 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 7268 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 7269 "sete $res\n\t" | |
| 7270 "movzbl $res, $res" %} | |
| 7271 opcode(0x0F, 0xB1); | |
| 7272 ins_encode(lock_prefix, | |
| 7273 REX_reg_mem(newval, mem_ptr), | |
| 7274 OpcP, OpcS, | |
| 7275 reg_mem(newval, mem_ptr), | |
| 7276 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 7277 REX_reg_breg(res, res), // movzbl | |
| 7278 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 7279 ins_pipe( pipe_cmpxchg ); | |
| 7280 %} | |
| 7281 | |
| 7282 | |
|
113
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|
7283 instruct compareAndSwapN(rRegI res, |
|
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diff
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|
7284 memory mem_ptr, |
|
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|
7285 rax_RegN oldval, rRegN newval, |
|
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|
7286 rFlagsReg cr) %{ |
|
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|
7287 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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|
7288 effect(KILL cr, KILL oldval); |
|
ba764ed4b6f2
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|
7289 |
|
ba764ed4b6f2
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diff
changeset
|
7290 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
|
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|
7291 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
|
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|
7292 "sete $res\n\t" |
|
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|
7293 "movzbl $res, $res" %} |
|
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|
7294 opcode(0x0F, 0xB1); |
|
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|
7295 ins_encode(lock_prefix, |
|
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|
7296 REX_reg_mem(newval, mem_ptr), |
|
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|
7297 OpcP, OpcS, |
|
ba764ed4b6f2
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|
7298 reg_mem(newval, mem_ptr), |
|
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|
7299 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
|
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|
7300 REX_reg_breg(res, res), // movzbl |
|
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|
7301 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
|
ba764ed4b6f2
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|
7302 ins_pipe( pipe_cmpxchg ); |
|
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|
7303 %} |
|
ba764ed4b6f2
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|
7304 |
|
6795
7eca5de9e0b6
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diff
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|
7305 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{ |
|
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|
7306 predicate(n->as_LoadStore()->result_not_used()); |
|
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|
7307 match(Set dummy (GetAndAddI mem add)); |
|
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diff
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|
7308 effect(KILL cr); |
|
7eca5de9e0b6
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diff
changeset
|
7309 format %{ "ADDL [$mem],$add" %} |
|
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|
7310 ins_encode %{ |
|
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|
7311 if (os::is_MP()) { __ lock(); } |
|
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|
7312 __ addl($mem$$Address, $add$$constant); |
|
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|
7313 %} |
|
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changeset
|
7314 ins_pipe( pipe_cmpxchg ); |
|
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|
7315 %} |
|
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changeset
|
7316 |
|
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changeset
|
7317 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{ |
|
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|
7318 match(Set newval (GetAndAddI mem newval)); |
|
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|
7319 effect(KILL cr); |
|
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diff
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|
7320 format %{ "XADDL [$mem],$newval" %} |
|
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|
7321 ins_encode %{ |
|
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diff
changeset
|
7322 if (os::is_MP()) { __ lock(); } |
|
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changeset
|
7323 __ xaddl($mem$$Address, $newval$$Register); |
|
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|
7324 %} |
|
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changeset
|
7325 ins_pipe( pipe_cmpxchg ); |
|
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6725
diff
changeset
|
7326 %} |
|
7eca5de9e0b6
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changeset
|
7327 |
|
10139
35c15dad89ea
8011901: Unsafe.getAndAddLong(obj, off, delta) does not work properly with long deltas
roland
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9154
diff
changeset
|
7328 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7329 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7330 match(Set dummy (GetAndAddL mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7331 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7332 format %{ "ADDQ [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7333 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7334 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7335 __ addq($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7336 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7337 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7338 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7339 |
|
7eca5de9e0b6
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6725
diff
changeset
|
7340 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7341 match(Set newval (GetAndAddL mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7342 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7343 format %{ "XADDQ [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7344 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7345 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7346 __ xaddq($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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diff
changeset
|
7347 %} |
|
7eca5de9e0b6
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diff
changeset
|
7348 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7349 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7350 |
|
7eca5de9e0b6
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diff
changeset
|
7351 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
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diff
changeset
|
7352 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7353 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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diff
changeset
|
7354 ins_encode %{ |
|
7eca5de9e0b6
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diff
changeset
|
7355 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7356 %} |
|
7eca5de9e0b6
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diff
changeset
|
7357 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7358 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7359 |
|
7eca5de9e0b6
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6725
diff
changeset
|
7360 instruct xchgL( memory mem, rRegL newval) %{ |
|
7eca5de9e0b6
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6725
diff
changeset
|
7361 match(Set newval (GetAndSetL mem newval)); |
|
7eca5de9e0b6
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6725
diff
changeset
|
7362 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
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diff
changeset
|
7363 ins_encode %{ |
|
7eca5de9e0b6
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diff
changeset
|
7364 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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diff
changeset
|
7365 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7366 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7367 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7368 |
|
7eca5de9e0b6
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6725
diff
changeset
|
7369 instruct xchgP( memory mem, rRegP newval) %{ |
|
7eca5de9e0b6
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6725
diff
changeset
|
7370 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
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6725
diff
changeset
|
7371 format %{ "XCHGQ $newval,[$mem]" %} |
|
7eca5de9e0b6
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diff
changeset
|
7372 ins_encode %{ |
|
7eca5de9e0b6
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6725
diff
changeset
|
7373 __ xchgq($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7374 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7375 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7376 %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7377 |
|
7eca5de9e0b6
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6725
diff
changeset
|
7378 instruct xchgN( memory mem, rRegN newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7379 match(Set newval (GetAndSetN mem newval)); |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7380 format %{ "XCHGL $newval,$mem]" %} |
|
7eca5de9e0b6
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6725
diff
changeset
|
7381 ins_encode %{ |
|
7eca5de9e0b6
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roland
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6725
diff
changeset
|
7382 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7383 %} |
|
7eca5de9e0b6
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diff
changeset
|
7384 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7385 %} |
|
7eca5de9e0b6
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|
7386 |
| 0 | 7387 //----------Subtraction Instructions------------------------------------------- |
| 7388 | |
| 7389 // Integer Subtraction Instructions | |
| 7390 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7391 %{ | |
| 7392 match(Set dst (SubI dst src)); | |
| 7393 effect(KILL cr); | |
| 7394 | |
| 7395 format %{ "subl $dst, $src\t# int" %} | |
| 7396 opcode(0x2B); | |
| 7397 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 7398 ins_pipe(ialu_reg_reg); | |
| 7399 %} | |
| 7400 | |
| 7401 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 7402 %{ | |
| 7403 match(Set dst (SubI dst src)); | |
| 7404 effect(KILL cr); | |
| 7405 | |
| 7406 format %{ "subl $dst, $src\t# int" %} | |
| 7407 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7408 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 7409 ins_pipe(ialu_reg); | |
| 7410 %} | |
| 7411 | |
| 7412 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7413 %{ | |
| 7414 match(Set dst (SubI dst (LoadI src))); | |
| 7415 effect(KILL cr); | |
| 7416 | |
| 7417 ins_cost(125); | |
| 7418 format %{ "subl $dst, $src\t# int" %} | |
| 7419 opcode(0x2B); | |
| 7420 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 7421 ins_pipe(ialu_reg_mem); | |
| 7422 %} | |
| 7423 | |
| 7424 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 7425 %{ | |
| 7426 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7427 effect(KILL cr); | |
| 7428 | |
| 7429 ins_cost(150); | |
| 7430 format %{ "subl $dst, $src\t# int" %} | |
| 7431 opcode(0x29); /* Opcode 29 /r */ | |
| 7432 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7433 ins_pipe(ialu_mem_reg); | |
| 7434 %} | |
| 7435 | |
| 7436 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 7437 %{ | |
| 7438 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7439 effect(KILL cr); | |
| 7440 | |
| 7441 ins_cost(125); // XXX | |
| 7442 format %{ "subl $dst, $src\t# int" %} | |
| 7443 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7444 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7445 ins_pipe(ialu_mem_imm); | |
| 7446 %} | |
| 7447 | |
| 7448 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7449 %{ | |
| 7450 match(Set dst (SubL dst src)); | |
| 7451 effect(KILL cr); | |
| 7452 | |
| 7453 format %{ "subq $dst, $src\t# long" %} | |
| 7454 opcode(0x2B); | |
| 7455 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7456 ins_pipe(ialu_reg_reg); | |
| 7457 %} | |
| 7458 | |
| 7459 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 7460 %{ | |
| 7461 match(Set dst (SubL dst src)); | |
| 7462 effect(KILL cr); | |
| 7463 | |
| 7464 format %{ "subq $dst, $src\t# long" %} | |
| 7465 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 7466 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 7467 ins_pipe(ialu_reg); | |
| 7468 %} | |
| 7469 | |
| 7470 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7471 %{ | |
| 7472 match(Set dst (SubL dst (LoadL src))); | |
| 7473 effect(KILL cr); | |
| 7474 | |
| 7475 ins_cost(125); | |
| 7476 format %{ "subq $dst, $src\t# long" %} | |
| 7477 opcode(0x2B); | |
| 7478 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 7479 ins_pipe(ialu_reg_mem); | |
| 7480 %} | |
| 7481 | |
| 7482 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 7483 %{ | |
| 7484 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7485 effect(KILL cr); | |
| 7486 | |
| 7487 ins_cost(150); | |
| 7488 format %{ "subq $dst, $src\t# long" %} | |
| 7489 opcode(0x29); /* Opcode 29 /r */ | |
| 7490 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7491 ins_pipe(ialu_mem_reg); | |
| 7492 %} | |
| 7493 | |
| 7494 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 7495 %{ | |
| 7496 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 7497 effect(KILL cr); | |
| 7498 | |
| 7499 ins_cost(125); // XXX | |
| 7500 format %{ "subq $dst, $src\t# long" %} | |
| 7501 opcode(0x81); /* Opcode 81 /5 id */ | |
| 7502 ins_encode(REX_mem_wide(dst), | |
| 7503 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 7504 ins_pipe(ialu_mem_imm); | |
| 7505 %} | |
| 7506 | |
| 7507 // Subtract from a pointer | |
| 7508 // XXX hmpf??? | |
| 7509 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 7510 %{ | |
| 7511 match(Set dst (AddP dst (SubI zero src))); | |
| 7512 effect(KILL cr); | |
| 7513 | |
| 7514 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 7515 opcode(0x2B); | |
| 7516 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 7517 ins_pipe(ialu_reg_reg); | |
| 7518 %} | |
| 7519 | |
| 7520 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 7521 %{ | |
| 7522 match(Set dst (SubI zero dst)); | |
| 7523 effect(KILL cr); | |
| 7524 | |
| 7525 format %{ "negl $dst\t# int" %} | |
| 7526 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7527 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7528 ins_pipe(ialu_reg); | |
| 7529 %} | |
| 7530 | |
| 7531 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 7532 %{ | |
| 7533 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 7534 effect(KILL cr); | |
| 7535 | |
| 7536 format %{ "negl $dst\t# int" %} | |
| 7537 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7538 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7539 ins_pipe(ialu_reg); | |
| 7540 %} | |
| 7541 | |
| 7542 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 7543 %{ | |
| 7544 match(Set dst (SubL zero dst)); | |
| 7545 effect(KILL cr); | |
| 7546 | |
| 7547 format %{ "negq $dst\t# long" %} | |
| 7548 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7549 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 7550 ins_pipe(ialu_reg); | |
| 7551 %} | |
| 7552 | |
| 7553 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 7554 %{ | |
| 7555 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 7556 effect(KILL cr); | |
| 7557 | |
| 7558 format %{ "negq $dst\t# long" %} | |
| 7559 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 7560 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7561 ins_pipe(ialu_reg); | |
| 7562 %} | |
| 7563 | |
| 7564 //----------Multiplication/Division Instructions------------------------------- | |
| 7565 // Integer Multiplication Instructions | |
| 7566 // Multiply Register | |
| 7567 | |
| 7568 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 7569 %{ | |
| 7570 match(Set dst (MulI dst src)); | |
| 7571 effect(KILL cr); | |
| 7572 | |
| 7573 ins_cost(300); | |
| 7574 format %{ "imull $dst, $src\t# int" %} | |
| 7575 opcode(0x0F, 0xAF); | |
| 7576 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7577 ins_pipe(ialu_reg_reg_alu0); | |
| 7578 %} | |
| 7579 | |
| 7580 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 7581 %{ | |
| 7582 match(Set dst (MulI src imm)); | |
| 7583 effect(KILL cr); | |
| 7584 | |
| 7585 ins_cost(300); | |
| 7586 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7587 opcode(0x69); /* 69 /r id */ | |
| 7588 ins_encode(REX_reg_reg(dst, src), | |
| 7589 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7590 ins_pipe(ialu_reg_reg_alu0); | |
| 7591 %} | |
| 7592 | |
| 7593 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 7594 %{ | |
| 7595 match(Set dst (MulI dst (LoadI src))); | |
| 7596 effect(KILL cr); | |
| 7597 | |
| 7598 ins_cost(350); | |
| 7599 format %{ "imull $dst, $src\t# int" %} | |
| 7600 opcode(0x0F, 0xAF); | |
| 7601 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7602 ins_pipe(ialu_reg_mem_alu0); | |
| 7603 %} | |
| 7604 | |
| 7605 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 7606 %{ | |
| 7607 match(Set dst (MulI (LoadI src) imm)); | |
| 7608 effect(KILL cr); | |
| 7609 | |
| 7610 ins_cost(300); | |
| 7611 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 7612 opcode(0x69); /* 69 /r id */ | |
| 7613 ins_encode(REX_reg_mem(dst, src), | |
| 7614 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7615 ins_pipe(ialu_reg_mem_alu0); | |
| 7616 %} | |
| 7617 | |
| 7618 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 7619 %{ | |
| 7620 match(Set dst (MulL dst src)); | |
| 7621 effect(KILL cr); | |
| 7622 | |
| 7623 ins_cost(300); | |
| 7624 format %{ "imulq $dst, $src\t# long" %} | |
| 7625 opcode(0x0F, 0xAF); | |
| 7626 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 7627 ins_pipe(ialu_reg_reg_alu0); | |
| 7628 %} | |
| 7629 | |
| 7630 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 7631 %{ | |
| 7632 match(Set dst (MulL src imm)); | |
| 7633 effect(KILL cr); | |
| 7634 | |
| 7635 ins_cost(300); | |
| 7636 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7637 opcode(0x69); /* 69 /r id */ | |
| 7638 ins_encode(REX_reg_reg_wide(dst, src), | |
| 7639 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 7640 ins_pipe(ialu_reg_reg_alu0); | |
| 7641 %} | |
| 7642 | |
| 7643 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 7644 %{ | |
| 7645 match(Set dst (MulL dst (LoadL src))); | |
| 7646 effect(KILL cr); | |
| 7647 | |
| 7648 ins_cost(350); | |
| 7649 format %{ "imulq $dst, $src\t# long" %} | |
| 7650 opcode(0x0F, 0xAF); | |
| 7651 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 7652 ins_pipe(ialu_reg_mem_alu0); | |
| 7653 %} | |
| 7654 | |
| 7655 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 7656 %{ | |
| 7657 match(Set dst (MulL (LoadL src) imm)); | |
| 7658 effect(KILL cr); | |
| 7659 | |
| 7660 ins_cost(300); | |
| 7661 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 7662 opcode(0x69); /* 69 /r id */ | |
| 7663 ins_encode(REX_reg_mem_wide(dst, src), | |
| 7664 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 7665 ins_pipe(ialu_reg_mem_alu0); | |
| 7666 %} | |
| 7667 | |
| 145 | 7668 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 7669 %{ | |
| 7670 match(Set dst (MulHiL src rax)); | |
| 7671 effect(USE_KILL rax, KILL cr); | |
| 7672 | |
| 7673 ins_cost(300); | |
| 7674 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 7675 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7676 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7677 ins_pipe(ialu_reg_reg_alu0); | |
| 7678 %} | |
| 7679 | |
| 0 | 7680 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 7681 rFlagsReg cr) | |
| 7682 %{ | |
| 7683 match(Set rax (DivI rax div)); | |
| 7684 effect(KILL rdx, KILL cr); | |
| 7685 | |
| 7686 ins_cost(30*100+10*100); // XXX | |
| 7687 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7688 "jne,s normal\n\t" | |
| 7689 "xorl rdx, rdx\n\t" | |
| 7690 "cmpl $div, -1\n\t" | |
| 7691 "je,s done\n" | |
| 7692 "normal: cdql\n\t" | |
| 7693 "idivl $div\n" | |
| 7694 "done:" %} | |
| 7695 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7696 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7697 ins_pipe(ialu_reg_reg_alu0); | |
| 7698 %} | |
| 7699 | |
| 7700 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7701 rFlagsReg cr) | |
| 7702 %{ | |
| 7703 match(Set rax (DivL rax div)); | |
| 7704 effect(KILL rdx, KILL cr); | |
| 7705 | |
| 7706 ins_cost(30*100+10*100); // XXX | |
| 7707 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7708 "cmpq rax, rdx\n\t" | |
| 7709 "jne,s normal\n\t" | |
| 7710 "xorl rdx, rdx\n\t" | |
| 7711 "cmpq $div, -1\n\t" | |
| 7712 "je,s done\n" | |
| 7713 "normal: cdqq\n\t" | |
| 7714 "idivq $div\n" | |
| 7715 "done:" %} | |
| 7716 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7717 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7718 ins_pipe(ialu_reg_reg_alu0); | |
| 7719 %} | |
| 7720 | |
| 7721 // Integer DIVMOD with Register, both quotient and mod results | |
| 7722 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 7723 rFlagsReg cr) | |
| 7724 %{ | |
| 7725 match(DivModI rax div); | |
| 7726 effect(KILL cr); | |
| 7727 | |
| 7728 ins_cost(30*100+10*100); // XXX | |
| 7729 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 7730 "jne,s normal\n\t" | |
| 7731 "xorl rdx, rdx\n\t" | |
| 7732 "cmpl $div, -1\n\t" | |
| 7733 "je,s done\n" | |
| 7734 "normal: cdql\n\t" | |
| 7735 "idivl $div\n" | |
| 7736 "done:" %} | |
| 7737 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7738 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7739 ins_pipe(pipe_slow); | |
| 7740 %} | |
| 7741 | |
| 7742 // Long DIVMOD with Register, both quotient and mod results | |
| 7743 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 7744 rFlagsReg cr) | |
| 7745 %{ | |
| 7746 match(DivModL rax div); | |
| 7747 effect(KILL cr); | |
| 7748 | |
| 7749 ins_cost(30*100+10*100); // XXX | |
| 7750 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 7751 "cmpq rax, rdx\n\t" | |
| 7752 "jne,s normal\n\t" | |
| 7753 "xorl rdx, rdx\n\t" | |
| 7754 "cmpq $div, -1\n\t" | |
| 7755 "je,s done\n" | |
| 7756 "normal: cdqq\n\t" | |
| 7757 "idivq $div\n" | |
| 7758 "done:" %} | |
| 7759 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7760 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7761 ins_pipe(pipe_slow); | |
| 7762 %} | |
| 7763 | |
| 7764 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 7765 // DivI cases are handled by the compiler | |
| 7766 | |
| 605 | 7767 // Magic constant, reciprocal of 10 |
| 0 | 7768 instruct loadConL_0x6666666666666667(rRegL dst) |
| 7769 %{ | |
| 7770 effect(DEF dst); | |
| 7771 | |
| 7772 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 7773 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 7774 ins_pipe(ialu_reg); | |
| 7775 %} | |
| 7776 | |
| 7777 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 7778 %{ | |
| 7779 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 7780 | |
| 7781 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 7782 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 7783 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 7784 ins_pipe(ialu_reg_reg_alu0); | |
| 7785 %} | |
| 7786 | |
| 7787 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 7788 %{ | |
| 7789 effect(USE_DEF dst, KILL cr); | |
| 7790 | |
| 7791 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 7792 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7793 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 7794 ins_pipe(ialu_reg); | |
| 7795 %} | |
| 7796 | |
| 7797 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 7798 %{ | |
| 7799 effect(USE_DEF dst, KILL cr); | |
| 7800 | |
| 7801 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 7802 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7803 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 7804 ins_pipe(ialu_reg); | |
| 7805 %} | |
| 7806 | |
| 7807 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 7808 %{ | |
| 7809 match(Set dst (DivL src div)); | |
| 7810 | |
| 7811 ins_cost((5+8)*100); | |
| 7812 expand %{ | |
| 7813 rax_RegL rax; // Killed temp | |
| 7814 rFlagsReg cr; // Killed | |
| 7815 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 7816 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 7817 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 7818 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 7819 subL_rReg(dst, src, cr); // subl rdx, src | |
| 7820 %} | |
| 7821 %} | |
| 7822 | |
| 7823 //----------------------------------------------------------------------------- | |
| 7824 | |
| 7825 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 7826 rFlagsReg cr) | |
| 7827 %{ | |
| 7828 match(Set rdx (ModI rax div)); | |
| 7829 effect(KILL rax, KILL cr); | |
| 7830 | |
| 7831 ins_cost(300); // XXX | |
| 7832 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 7833 "jne,s normal\n\t" | |
| 7834 "xorl rdx, rdx\n\t" | |
| 7835 "cmpl $div, -1\n\t" | |
| 7836 "je,s done\n" | |
| 7837 "normal: cdql\n\t" | |
| 7838 "idivl $div\n" | |
| 7839 "done:" %} | |
| 7840 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7841 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 7842 ins_pipe(ialu_reg_reg_alu0); | |
| 7843 %} | |
| 7844 | |
| 7845 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 7846 rFlagsReg cr) | |
| 7847 %{ | |
| 7848 match(Set rdx (ModL rax div)); | |
| 7849 effect(KILL rax, KILL cr); | |
| 7850 | |
| 7851 ins_cost(300); // XXX | |
| 7852 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 7853 "cmpq rax, rdx\n\t" | |
| 7854 "jne,s normal\n\t" | |
| 7855 "xorl rdx, rdx\n\t" | |
| 7856 "cmpq $div, -1\n\t" | |
| 7857 "je,s done\n" | |
| 7858 "normal: cdqq\n\t" | |
| 7859 "idivq $div\n" | |
| 7860 "done:" %} | |
| 7861 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7862 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 7863 ins_pipe(ialu_reg_reg_alu0); | |
| 7864 %} | |
| 7865 | |
| 7866 // Integer Shift Instructions | |
| 7867 // Shift Left by one | |
| 7868 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 7869 %{ | |
| 7870 match(Set dst (LShiftI dst shift)); | |
| 7871 effect(KILL cr); | |
| 7872 | |
| 7873 format %{ "sall $dst, $shift" %} | |
| 7874 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7875 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7876 ins_pipe(ialu_reg); | |
| 7877 %} | |
| 7878 | |
| 7879 // Shift Left by one | |
| 7880 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7881 %{ | |
| 7882 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7883 effect(KILL cr); | |
| 7884 | |
| 7885 format %{ "sall $dst, $shift\t" %} | |
| 7886 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7887 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7888 ins_pipe(ialu_mem_imm); | |
| 7889 %} | |
| 7890 | |
| 7891 // Shift Left by 8-bit immediate | |
| 7892 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 7893 %{ | |
| 7894 match(Set dst (LShiftI dst shift)); | |
| 7895 effect(KILL cr); | |
| 7896 | |
| 7897 format %{ "sall $dst, $shift" %} | |
| 7898 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7899 ins_encode(reg_opc_imm(dst, shift)); | |
| 7900 ins_pipe(ialu_reg); | |
| 7901 %} | |
| 7902 | |
| 7903 // Shift Left by 8-bit immediate | |
| 7904 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 7905 %{ | |
| 7906 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7907 effect(KILL cr); | |
| 7908 | |
| 7909 format %{ "sall $dst, $shift" %} | |
| 7910 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7911 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 7912 ins_pipe(ialu_mem_imm); | |
| 7913 %} | |
| 7914 | |
| 7915 // Shift Left by variable | |
| 7916 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 7917 %{ | |
| 7918 match(Set dst (LShiftI dst shift)); | |
| 7919 effect(KILL cr); | |
| 7920 | |
| 7921 format %{ "sall $dst, $shift" %} | |
| 7922 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7923 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7924 ins_pipe(ialu_reg_reg); | |
| 7925 %} | |
| 7926 | |
| 7927 // Shift Left by variable | |
| 7928 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 7929 %{ | |
| 7930 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 7931 effect(KILL cr); | |
| 7932 | |
| 7933 format %{ "sall $dst, $shift" %} | |
| 7934 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7935 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7936 ins_pipe(ialu_mem_reg); | |
| 7937 %} | |
| 7938 | |
| 7939 // Arithmetic shift right by one | |
| 7940 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 7941 %{ | |
| 7942 match(Set dst (RShiftI dst shift)); | |
| 7943 effect(KILL cr); | |
| 7944 | |
| 7945 format %{ "sarl $dst, $shift" %} | |
| 7946 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7947 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7948 ins_pipe(ialu_reg); | |
| 7949 %} | |
| 7950 | |
| 7951 // Arithmetic shift right by one | |
| 7952 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 7953 %{ | |
| 7954 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7955 effect(KILL cr); | |
| 7956 | |
| 7957 format %{ "sarl $dst, $shift" %} | |
| 7958 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7959 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 7960 ins_pipe(ialu_mem_imm); | |
| 7961 %} | |
| 7962 | |
| 7963 // Arithmetic Shift Right by 8-bit immediate | |
| 7964 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 7965 %{ | |
| 7966 match(Set dst (RShiftI dst shift)); | |
| 7967 effect(KILL cr); | |
| 7968 | |
| 7969 format %{ "sarl $dst, $shift" %} | |
| 7970 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7971 ins_encode(reg_opc_imm(dst, shift)); | |
| 7972 ins_pipe(ialu_mem_imm); | |
| 7973 %} | |
| 7974 | |
| 7975 // Arithmetic Shift Right by 8-bit immediate | |
| 7976 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 7977 %{ | |
| 7978 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7979 effect(KILL cr); | |
| 7980 | |
| 7981 format %{ "sarl $dst, $shift" %} | |
| 7982 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7983 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 7984 ins_pipe(ialu_mem_imm); | |
| 7985 %} | |
| 7986 | |
| 7987 // Arithmetic Shift Right by variable | |
| 7988 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 7989 %{ | |
| 7990 match(Set dst (RShiftI dst shift)); | |
| 7991 effect(KILL cr); | |
| 7992 | |
| 7993 format %{ "sarl $dst, $shift" %} | |
| 7994 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7995 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 7996 ins_pipe(ialu_reg_reg); | |
| 7997 %} | |
| 7998 | |
| 7999 // Arithmetic Shift Right by variable | |
| 8000 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8001 %{ | |
| 8002 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8003 effect(KILL cr); | |
| 8004 | |
| 8005 format %{ "sarl $dst, $shift" %} | |
| 8006 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8007 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8008 ins_pipe(ialu_mem_reg); | |
| 8009 %} | |
| 8010 | |
| 8011 // Logical shift right by one | |
| 8012 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 8013 %{ | |
| 8014 match(Set dst (URShiftI dst shift)); | |
| 8015 effect(KILL cr); | |
| 8016 | |
| 8017 format %{ "shrl $dst, $shift" %} | |
| 8018 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8019 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8020 ins_pipe(ialu_reg); | |
| 8021 %} | |
| 8022 | |
| 8023 // Logical shift right by one | |
| 8024 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8025 %{ | |
| 8026 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8027 effect(KILL cr); | |
| 8028 | |
| 8029 format %{ "shrl $dst, $shift" %} | |
| 8030 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8031 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8032 ins_pipe(ialu_mem_imm); | |
| 8033 %} | |
| 8034 | |
| 8035 // Logical Shift Right by 8-bit immediate | |
| 8036 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8037 %{ | |
| 8038 match(Set dst (URShiftI dst shift)); | |
| 8039 effect(KILL cr); | |
| 8040 | |
| 8041 format %{ "shrl $dst, $shift" %} | |
| 8042 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8043 ins_encode(reg_opc_imm(dst, shift)); | |
| 8044 ins_pipe(ialu_reg); | |
| 8045 %} | |
| 8046 | |
| 8047 // Logical Shift Right by 8-bit immediate | |
| 8048 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8049 %{ | |
| 8050 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8051 effect(KILL cr); | |
| 8052 | |
| 8053 format %{ "shrl $dst, $shift" %} | |
| 8054 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8055 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8056 ins_pipe(ialu_mem_imm); | |
| 8057 %} | |
| 8058 | |
| 8059 // Logical Shift Right by variable | |
| 8060 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8061 %{ | |
| 8062 match(Set dst (URShiftI dst shift)); | |
| 8063 effect(KILL cr); | |
| 8064 | |
| 8065 format %{ "shrl $dst, $shift" %} | |
| 8066 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8067 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8068 ins_pipe(ialu_reg_reg); | |
| 8069 %} | |
| 8070 | |
| 8071 // Logical Shift Right by variable | |
| 8072 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8073 %{ | |
| 8074 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 8075 effect(KILL cr); | |
| 8076 | |
| 8077 format %{ "shrl $dst, $shift" %} | |
| 8078 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8079 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8080 ins_pipe(ialu_mem_reg); | |
| 8081 %} | |
| 8082 | |
| 8083 // Long Shift Instructions | |
| 8084 // Shift Left by one | |
| 8085 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8086 %{ | |
| 8087 match(Set dst (LShiftL dst shift)); | |
| 8088 effect(KILL cr); | |
| 8089 | |
| 8090 format %{ "salq $dst, $shift" %} | |
| 8091 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8092 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8093 ins_pipe(ialu_reg); | |
| 8094 %} | |
| 8095 | |
| 8096 // Shift Left by one | |
| 8097 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8098 %{ | |
| 8099 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8100 effect(KILL cr); | |
| 8101 | |
| 8102 format %{ "salq $dst, $shift" %} | |
| 8103 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8104 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8105 ins_pipe(ialu_mem_imm); | |
| 8106 %} | |
| 8107 | |
| 8108 // Shift Left by 8-bit immediate | |
| 8109 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8110 %{ | |
| 8111 match(Set dst (LShiftL dst shift)); | |
| 8112 effect(KILL cr); | |
| 8113 | |
| 8114 format %{ "salq $dst, $shift" %} | |
| 8115 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8116 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8117 ins_pipe(ialu_reg); | |
| 8118 %} | |
| 8119 | |
| 8120 // Shift Left by 8-bit immediate | |
| 8121 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8122 %{ | |
| 8123 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8124 effect(KILL cr); | |
| 8125 | |
| 8126 format %{ "salq $dst, $shift" %} | |
| 8127 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8128 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8129 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8130 ins_pipe(ialu_mem_imm); | |
| 8131 %} | |
| 8132 | |
| 8133 // Shift Left by variable | |
| 8134 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8135 %{ | |
| 8136 match(Set dst (LShiftL dst shift)); | |
| 8137 effect(KILL cr); | |
| 8138 | |
| 8139 format %{ "salq $dst, $shift" %} | |
| 8140 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8141 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8142 ins_pipe(ialu_reg_reg); | |
| 8143 %} | |
| 8144 | |
| 8145 // Shift Left by variable | |
| 8146 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8147 %{ | |
| 8148 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 8149 effect(KILL cr); | |
| 8150 | |
| 8151 format %{ "salq $dst, $shift" %} | |
| 8152 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8153 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8154 ins_pipe(ialu_mem_reg); | |
| 8155 %} | |
| 8156 | |
| 8157 // Arithmetic shift right by one | |
| 8158 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8159 %{ | |
| 8160 match(Set dst (RShiftL dst shift)); | |
| 8161 effect(KILL cr); | |
| 8162 | |
| 8163 format %{ "sarq $dst, $shift" %} | |
| 8164 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8165 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8166 ins_pipe(ialu_reg); | |
| 8167 %} | |
| 8168 | |
| 8169 // Arithmetic shift right by one | |
| 8170 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8171 %{ | |
| 8172 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8173 effect(KILL cr); | |
| 8174 | |
| 8175 format %{ "sarq $dst, $shift" %} | |
| 8176 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8177 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8178 ins_pipe(ialu_mem_imm); | |
| 8179 %} | |
| 8180 | |
| 8181 // Arithmetic Shift Right by 8-bit immediate | |
| 8182 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8183 %{ | |
| 8184 match(Set dst (RShiftL dst shift)); | |
| 8185 effect(KILL cr); | |
| 8186 | |
| 8187 format %{ "sarq $dst, $shift" %} | |
| 8188 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8189 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8190 ins_pipe(ialu_mem_imm); | |
| 8191 %} | |
| 8192 | |
| 8193 // Arithmetic Shift Right by 8-bit immediate | |
| 8194 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8195 %{ | |
| 8196 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8197 effect(KILL cr); | |
| 8198 | |
| 8199 format %{ "sarq $dst, $shift" %} | |
| 8200 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8201 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8202 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8203 ins_pipe(ialu_mem_imm); | |
| 8204 %} | |
| 8205 | |
| 8206 // Arithmetic Shift Right by variable | |
| 8207 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8208 %{ | |
| 8209 match(Set dst (RShiftL dst shift)); | |
| 8210 effect(KILL cr); | |
| 8211 | |
| 8212 format %{ "sarq $dst, $shift" %} | |
| 8213 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8214 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8215 ins_pipe(ialu_reg_reg); | |
| 8216 %} | |
| 8217 | |
| 8218 // Arithmetic Shift Right by variable | |
| 8219 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8220 %{ | |
| 8221 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 8222 effect(KILL cr); | |
| 8223 | |
| 8224 format %{ "sarq $dst, $shift" %} | |
| 8225 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8226 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8227 ins_pipe(ialu_mem_reg); | |
| 8228 %} | |
| 8229 | |
| 8230 // Logical shift right by one | |
| 8231 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 8232 %{ | |
| 8233 match(Set dst (URShiftL dst shift)); | |
| 8234 effect(KILL cr); | |
| 8235 | |
| 8236 format %{ "shrq $dst, $shift" %} | |
| 8237 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8238 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 8239 ins_pipe(ialu_reg); | |
| 8240 %} | |
| 8241 | |
| 8242 // Logical shift right by one | |
| 8243 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 8244 %{ | |
| 8245 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8246 effect(KILL cr); | |
| 8247 | |
| 8248 format %{ "shrq $dst, $shift" %} | |
| 8249 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8250 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8251 ins_pipe(ialu_mem_imm); | |
| 8252 %} | |
| 8253 | |
| 8254 // Logical Shift Right by 8-bit immediate | |
| 8255 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8256 %{ | |
| 8257 match(Set dst (URShiftL dst shift)); | |
| 8258 effect(KILL cr); | |
| 8259 | |
| 8260 format %{ "shrq $dst, $shift" %} | |
| 8261 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8262 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8263 ins_pipe(ialu_reg); | |
| 8264 %} | |
| 8265 | |
|
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|
8266 |
| 0 | 8267 // Logical Shift Right by 8-bit immediate |
| 8268 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 8269 %{ | |
| 8270 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8271 effect(KILL cr); | |
| 8272 | |
| 8273 format %{ "shrq $dst, $shift" %} | |
| 8274 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8275 ins_encode(REX_mem_wide(dst), OpcP, | |
| 8276 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 8277 ins_pipe(ialu_mem_imm); | |
| 8278 %} | |
| 8279 | |
| 8280 // Logical Shift Right by variable | |
| 8281 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8282 %{ | |
| 8283 match(Set dst (URShiftL dst shift)); | |
| 8284 effect(KILL cr); | |
| 8285 | |
| 8286 format %{ "shrq $dst, $shift" %} | |
| 8287 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8288 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8289 ins_pipe(ialu_reg_reg); | |
| 8290 %} | |
| 8291 | |
| 8292 // Logical Shift Right by variable | |
| 8293 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 8294 %{ | |
| 8295 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 8296 effect(KILL cr); | |
| 8297 | |
| 8298 format %{ "shrq $dst, $shift" %} | |
| 8299 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8300 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8301 ins_pipe(ialu_mem_reg); | |
| 8302 %} | |
| 8303 | |
| 8304 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 8305 // This idiom is used by the compiler for the i2b bytecode. | |
| 8306 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 8307 %{ | |
| 8308 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 8309 | |
| 8310 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 8311 opcode(0x0F, 0xBE); | |
| 8312 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8313 ins_pipe(ialu_reg_reg); | |
| 8314 %} | |
| 8315 | |
| 8316 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8317 // This idiom is used by the compiler the i2s bytecode. | |
| 8318 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 8319 %{ | |
| 8320 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 8321 | |
| 8322 format %{ "movswl $dst, $src\t# i2s" %} | |
| 8323 opcode(0x0F, 0xBF); | |
| 8324 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8325 ins_pipe(ialu_reg_reg); | |
| 8326 %} | |
| 8327 | |
| 8328 // ROL/ROR instructions | |
| 8329 | |
| 8330 // ROL expand | |
| 8331 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 8332 effect(KILL cr, USE_DEF dst); | |
| 8333 | |
| 8334 format %{ "roll $dst" %} | |
| 8335 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8336 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8337 ins_pipe(ialu_reg); | |
| 8338 %} | |
| 8339 | |
| 8340 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 8341 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8342 | |
| 8343 format %{ "roll $dst, $shift" %} | |
| 8344 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8345 ins_encode( reg_opc_imm(dst, shift) ); | |
| 8346 ins_pipe(ialu_reg); | |
| 8347 %} | |
| 8348 | |
| 8349 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8350 %{ | |
| 8351 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8352 | |
| 8353 format %{ "roll $dst, $shift" %} | |
| 8354 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8355 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8356 ins_pipe(ialu_reg_reg); | |
| 8357 %} | |
| 8358 // end of ROL expand | |
| 8359 | |
| 8360 // Rotate Left by one | |
| 8361 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8362 %{ | |
| 8363 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8364 | |
| 8365 expand %{ | |
| 8366 rolI_rReg_imm1(dst, cr); | |
| 8367 %} | |
| 8368 %} | |
| 8369 | |
| 8370 // Rotate Left by 8-bit immediate | |
| 8371 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8372 %{ | |
| 8373 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8374 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8375 | |
| 8376 expand %{ | |
| 8377 rolI_rReg_imm8(dst, lshift, cr); | |
| 8378 %} | |
| 8379 %} | |
| 8380 | |
| 8381 // Rotate Left by variable | |
| 8382 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8383 %{ | |
| 8384 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8385 | |
| 8386 expand %{ | |
| 8387 rolI_rReg_CL(dst, shift, cr); | |
| 8388 %} | |
| 8389 %} | |
| 8390 | |
| 8391 // Rotate Left by variable | |
| 8392 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8393 %{ | |
| 8394 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8395 | |
| 8396 expand %{ | |
| 8397 rolI_rReg_CL(dst, shift, cr); | |
| 8398 %} | |
| 8399 %} | |
| 8400 | |
| 8401 // ROR expand | |
| 8402 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 8403 %{ | |
| 8404 effect(USE_DEF dst, KILL cr); | |
| 8405 | |
| 8406 format %{ "rorl $dst" %} | |
| 8407 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8408 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8409 ins_pipe(ialu_reg); | |
| 8410 %} | |
| 8411 | |
| 8412 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 8413 %{ | |
| 8414 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8415 | |
| 8416 format %{ "rorl $dst, $shift" %} | |
| 8417 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8418 ins_encode(reg_opc_imm(dst, shift)); | |
| 8419 ins_pipe(ialu_reg); | |
| 8420 %} | |
| 8421 | |
| 8422 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 8423 %{ | |
| 8424 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8425 | |
| 8426 format %{ "rorl $dst, $shift" %} | |
| 8427 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8428 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8429 ins_pipe(ialu_reg_reg); | |
| 8430 %} | |
| 8431 // end of ROR expand | |
| 8432 | |
| 8433 // Rotate Right by one | |
| 8434 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8435 %{ | |
| 8436 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8437 | |
| 8438 expand %{ | |
| 8439 rorI_rReg_imm1(dst, cr); | |
| 8440 %} | |
| 8441 %} | |
| 8442 | |
| 8443 // Rotate Right by 8-bit immediate | |
| 8444 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8445 %{ | |
| 8446 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8447 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8448 | |
| 8449 expand %{ | |
| 8450 rorI_rReg_imm8(dst, rshift, cr); | |
| 8451 %} | |
| 8452 %} | |
| 8453 | |
| 8454 // Rotate Right by variable | |
| 8455 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8456 %{ | |
| 8457 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8458 | |
| 8459 expand %{ | |
| 8460 rorI_rReg_CL(dst, shift, cr); | |
| 8461 %} | |
| 8462 %} | |
| 8463 | |
| 8464 // Rotate Right by variable | |
| 8465 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 8466 %{ | |
| 8467 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8468 | |
| 8469 expand %{ | |
| 8470 rorI_rReg_CL(dst, shift, cr); | |
| 8471 %} | |
| 8472 %} | |
| 8473 | |
| 8474 // for long rotate | |
| 8475 // ROL expand | |
| 8476 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 8477 effect(USE_DEF dst, KILL cr); | |
| 8478 | |
| 8479 format %{ "rolq $dst" %} | |
| 8480 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8481 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8482 ins_pipe(ialu_reg); | |
| 8483 %} | |
| 8484 | |
| 8485 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 8486 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8487 | |
| 8488 format %{ "rolq $dst, $shift" %} | |
| 8489 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 8490 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 8491 ins_pipe(ialu_reg); | |
| 8492 %} | |
| 8493 | |
| 8494 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8495 %{ | |
| 8496 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8497 | |
| 8498 format %{ "rolq $dst, $shift" %} | |
| 8499 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8500 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8501 ins_pipe(ialu_reg_reg); | |
| 8502 %} | |
| 8503 // end of ROL expand | |
| 8504 | |
| 8505 // Rotate Left by one | |
| 8506 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 8507 %{ | |
| 8508 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8509 | |
| 8510 expand %{ | |
| 8511 rolL_rReg_imm1(dst, cr); | |
| 8512 %} | |
| 8513 %} | |
| 8514 | |
| 8515 // Rotate Left by 8-bit immediate | |
| 8516 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 8517 %{ | |
| 8518 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8519 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 8520 | |
| 8521 expand %{ | |
| 8522 rolL_rReg_imm8(dst, lshift, cr); | |
| 8523 %} | |
| 8524 %} | |
| 8525 | |
| 8526 // Rotate Left by variable | |
| 8527 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8528 %{ | |
| 8529 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 8530 | |
| 8531 expand %{ | |
| 8532 rolL_rReg_CL(dst, shift, cr); | |
| 8533 %} | |
| 8534 %} | |
| 8535 | |
| 8536 // Rotate Left by variable | |
| 8537 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8538 %{ | |
| 8539 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 8540 | |
| 8541 expand %{ | |
| 8542 rolL_rReg_CL(dst, shift, cr); | |
| 8543 %} | |
| 8544 %} | |
| 8545 | |
| 8546 // ROR expand | |
| 8547 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 8548 %{ | |
| 8549 effect(USE_DEF dst, KILL cr); | |
| 8550 | |
| 8551 format %{ "rorq $dst" %} | |
| 8552 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 8553 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8554 ins_pipe(ialu_reg); | |
| 8555 %} | |
| 8556 | |
| 8557 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 8558 %{ | |
| 8559 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8560 | |
| 8561 format %{ "rorq $dst, $shift" %} | |
| 8562 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 8563 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 8564 ins_pipe(ialu_reg); | |
| 8565 %} | |
| 8566 | |
| 8567 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 8568 %{ | |
| 8569 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8570 | |
| 8571 format %{ "rorq $dst, $shift" %} | |
| 8572 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 8573 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8574 ins_pipe(ialu_reg_reg); | |
| 8575 %} | |
| 8576 // end of ROR expand | |
| 8577 | |
| 8578 // Rotate Right by one | |
| 8579 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 8580 %{ | |
| 8581 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8582 | |
| 8583 expand %{ | |
| 8584 rorL_rReg_imm1(dst, cr); | |
| 8585 %} | |
| 8586 %} | |
| 8587 | |
| 8588 // Rotate Right by 8-bit immediate | |
| 8589 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 8590 %{ | |
| 8591 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 8592 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 8593 | |
| 8594 expand %{ | |
| 8595 rorL_rReg_imm8(dst, rshift, cr); | |
| 8596 %} | |
| 8597 %} | |
| 8598 | |
| 8599 // Rotate Right by variable | |
| 8600 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 8601 %{ | |
| 8602 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 8603 | |
| 8604 expand %{ | |
| 8605 rorL_rReg_CL(dst, shift, cr); | |
| 8606 %} | |
| 8607 %} | |
| 8608 | |
| 8609 // Rotate Right by variable | |
| 8610 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 8611 %{ | |
| 8612 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 8613 | |
| 8614 expand %{ | |
| 8615 rorL_rReg_CL(dst, shift, cr); | |
| 8616 %} | |
| 8617 %} | |
| 8618 | |
| 8619 // Logical Instructions | |
| 8620 | |
| 8621 // Integer Logical Instructions | |
| 8622 | |
| 8623 // And Instructions | |
| 8624 // And Register with Register | |
| 8625 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8626 %{ | |
| 8627 match(Set dst (AndI dst src)); | |
| 8628 effect(KILL cr); | |
| 8629 | |
| 8630 format %{ "andl $dst, $src\t# int" %} | |
| 8631 opcode(0x23); | |
| 8632 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8633 ins_pipe(ialu_reg_reg); | |
| 8634 %} | |
| 8635 | |
| 8636 // And Register with Immediate 255 | |
| 8637 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 8638 %{ | |
| 8639 match(Set dst (AndI dst src)); | |
| 8640 | |
| 8641 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 8642 opcode(0x0F, 0xB6); | |
| 8643 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8644 ins_pipe(ialu_reg); | |
| 8645 %} | |
| 8646 | |
| 8647 // And Register with Immediate 255 and promote to long | |
| 8648 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 8649 %{ | |
| 8650 match(Set dst (ConvI2L (AndI src mask))); | |
| 8651 | |
| 8652 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 8653 opcode(0x0F, 0xB6); | |
| 8654 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8655 ins_pipe(ialu_reg); | |
| 8656 %} | |
| 8657 | |
| 8658 // And Register with Immediate 65535 | |
| 8659 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 8660 %{ | |
| 8661 match(Set dst (AndI dst src)); | |
| 8662 | |
| 8663 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 8664 opcode(0x0F, 0xB7); | |
| 8665 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 8666 ins_pipe(ialu_reg); | |
| 8667 %} | |
| 8668 | |
| 8669 // And Register with Immediate 65535 and promote to long | |
| 8670 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 8671 %{ | |
| 8672 match(Set dst (ConvI2L (AndI src mask))); | |
| 8673 | |
| 8674 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 8675 opcode(0x0F, 0xB7); | |
| 8676 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8677 ins_pipe(ialu_reg); | |
| 8678 %} | |
| 8679 | |
| 8680 // And Register with Immediate | |
| 8681 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8682 %{ | |
| 8683 match(Set dst (AndI dst src)); | |
| 8684 effect(KILL cr); | |
| 8685 | |
| 8686 format %{ "andl $dst, $src\t# int" %} | |
| 8687 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 8688 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8689 ins_pipe(ialu_reg); | |
| 8690 %} | |
| 8691 | |
| 8692 // And Register with Memory | |
| 8693 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8694 %{ | |
| 8695 match(Set dst (AndI dst (LoadI src))); | |
| 8696 effect(KILL cr); | |
| 8697 | |
| 8698 ins_cost(125); | |
| 8699 format %{ "andl $dst, $src\t# int" %} | |
| 8700 opcode(0x23); | |
| 8701 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8702 ins_pipe(ialu_reg_mem); | |
| 8703 %} | |
| 8704 | |
| 8705 // And Memory with Register | |
| 8706 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8707 %{ | |
| 8708 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8709 effect(KILL cr); | |
| 8710 | |
| 8711 ins_cost(150); | |
| 8712 format %{ "andl $dst, $src\t# int" %} | |
| 8713 opcode(0x21); /* Opcode 21 /r */ | |
| 8714 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8715 ins_pipe(ialu_mem_reg); | |
| 8716 %} | |
| 8717 | |
| 8718 // And Memory with Immediate | |
| 8719 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8720 %{ | |
| 8721 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8722 effect(KILL cr); | |
| 8723 | |
| 8724 ins_cost(125); | |
| 8725 format %{ "andl $dst, $src\t# int" %} | |
| 8726 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8727 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8728 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8729 ins_pipe(ialu_mem_imm); | |
| 8730 %} | |
| 8731 | |
|
17729
8a8ff6b577ed
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|
8732 // BMI1 instructions |
|
8a8ff6b577ed
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|
8733 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
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|
8734 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2))); |
|
8a8ff6b577ed
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|
8735 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8736 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8737 |
|
8a8ff6b577ed
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changeset
|
8738 ins_cost(125); |
|
8a8ff6b577ed
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|
8739 format %{ "andnl $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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changeset
|
8740 |
|
8a8ff6b577ed
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changeset
|
8741 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8742 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
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|
8743 %} |
|
8a8ff6b577ed
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changeset
|
8744 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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|
8745 %} |
|
8a8ff6b577ed
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changeset
|
8746 |
|
8a8ff6b577ed
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|
8747 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{ |
|
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|
8748 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8a8ff6b577ed
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diff
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|
8749 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
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|
8750 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8751 |
|
8a8ff6b577ed
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|
8752 format %{ "andnl $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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|
8753 |
|
8a8ff6b577ed
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changeset
|
8754 ins_encode %{ |
|
8a8ff6b577ed
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|
8755 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8a8ff6b577ed
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|
8756 %} |
|
8a8ff6b577ed
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changeset
|
8757 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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|
8758 %} |
|
8a8ff6b577ed
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changeset
|
8759 |
|
8a8ff6b577ed
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|
8760 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{ |
|
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|
8761 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8a8ff6b577ed
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changeset
|
8762 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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|
8763 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8764 |
|
8a8ff6b577ed
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|
8765 format %{ "blsil $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8766 |
|
8a8ff6b577ed
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|
8767 ins_encode %{ |
|
8a8ff6b577ed
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|
8768 __ blsil($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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|
8769 %} |
|
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|
8770 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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|
8771 %} |
|
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|
8772 |
|
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|
8773 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{ |
|
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|
8774 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8a8ff6b577ed
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diff
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|
8775 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
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|
8776 effect(KILL cr); |
|
8a8ff6b577ed
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diff
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|
8777 |
|
8a8ff6b577ed
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|
8778 ins_cost(125); |
|
8a8ff6b577ed
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diff
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|
8779 format %{ "blsil $dst, $src" %} |
|
8a8ff6b577ed
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diff
changeset
|
8780 |
|
8a8ff6b577ed
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|
8781 ins_encode %{ |
|
8a8ff6b577ed
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diff
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|
8782 __ blsil($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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changeset
|
8783 %} |
|
8a8ff6b577ed
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diff
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|
8784 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
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|
8785 %} |
|
8a8ff6b577ed
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diff
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|
8786 |
|
8a8ff6b577ed
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|
8787 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
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|
8788 %{ |
|
8a8ff6b577ed
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diff
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|
8789 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8a8ff6b577ed
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diff
changeset
|
8790 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
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|
8791 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8792 |
|
8a8ff6b577ed
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diff
changeset
|
8793 ins_cost(125); |
|
8a8ff6b577ed
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|
8794 format %{ "blsmskl $dst, $src" %} |
|
8a8ff6b577ed
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diff
changeset
|
8795 |
|
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diff
changeset
|
8796 ins_encode %{ |
|
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|
8797 __ blsmskl($dst$$Register, $src$$Address); |
|
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diff
changeset
|
8798 %} |
|
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diff
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|
8799 ins_pipe(ialu_reg_mem); |
|
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diff
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|
8800 %} |
|
8a8ff6b577ed
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diff
changeset
|
8801 |
|
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|
8802 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
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diff
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|
8803 %{ |
|
8a8ff6b577ed
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diff
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|
8804 match(Set dst (XorI (AddI src minus_1) src)); |
|
8a8ff6b577ed
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diff
changeset
|
8805 predicate(UseBMI1Instructions); |
|
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diff
changeset
|
8806 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8807 |
|
8a8ff6b577ed
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diff
changeset
|
8808 format %{ "blsmskl $dst, $src" %} |
|
8a8ff6b577ed
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diff
changeset
|
8809 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8810 ins_encode %{ |
|
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diff
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|
8811 __ blsmskl($dst$$Register, $src$$Register); |
|
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diff
changeset
|
8812 %} |
|
8a8ff6b577ed
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diff
changeset
|
8813 |
|
8a8ff6b577ed
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diff
changeset
|
8814 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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diff
changeset
|
8815 %} |
|
8a8ff6b577ed
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diff
changeset
|
8816 |
|
8a8ff6b577ed
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|
8817 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
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diff
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|
8818 %{ |
|
8a8ff6b577ed
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diff
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|
8819 match(Set dst (AndI (AddI src minus_1) src) ); |
|
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diff
changeset
|
8820 predicate(UseBMI1Instructions); |
|
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changeset
|
8821 effect(KILL cr); |
|
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|
8822 |
|
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|
8823 format %{ "blsrl $dst, $src" %} |
|
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|
8824 |
|
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|
8825 ins_encode %{ |
|
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|
8826 __ blsrl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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|
8827 %} |
|
8a8ff6b577ed
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|
8828 |
|
8a8ff6b577ed
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|
8829 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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|
8830 %} |
|
8a8ff6b577ed
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|
8831 |
|
8a8ff6b577ed
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|
8832 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
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|
8833 %{ |
|
8a8ff6b577ed
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|
8834 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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changeset
|
8835 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8836 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8837 |
|
8a8ff6b577ed
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changeset
|
8838 ins_cost(125); |
|
8a8ff6b577ed
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|
8839 format %{ "blsrl $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8840 |
|
8a8ff6b577ed
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changeset
|
8841 ins_encode %{ |
|
8a8ff6b577ed
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|
8842 __ blsrl($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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|
8843 %} |
|
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changeset
|
8844 |
|
8a8ff6b577ed
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changeset
|
8845 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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|
8846 %} |
|
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|
8847 |
| 0 | 8848 // Or Instructions |
| 8849 // Or Register with Register | |
| 8850 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8851 %{ | |
| 8852 match(Set dst (OrI dst src)); | |
| 8853 effect(KILL cr); | |
| 8854 | |
| 8855 format %{ "orl $dst, $src\t# int" %} | |
| 8856 opcode(0x0B); | |
| 8857 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8858 ins_pipe(ialu_reg_reg); | |
| 8859 %} | |
| 8860 | |
| 8861 // Or Register with Immediate | |
| 8862 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8863 %{ | |
| 8864 match(Set dst (OrI dst src)); | |
| 8865 effect(KILL cr); | |
| 8866 | |
| 8867 format %{ "orl $dst, $src\t# int" %} | |
| 8868 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 8869 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8870 ins_pipe(ialu_reg); | |
| 8871 %} | |
| 8872 | |
| 8873 // Or Register with Memory | |
| 8874 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8875 %{ | |
| 8876 match(Set dst (OrI dst (LoadI src))); | |
| 8877 effect(KILL cr); | |
| 8878 | |
| 8879 ins_cost(125); | |
| 8880 format %{ "orl $dst, $src\t# int" %} | |
| 8881 opcode(0x0B); | |
| 8882 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8883 ins_pipe(ialu_reg_mem); | |
| 8884 %} | |
| 8885 | |
| 8886 // Or Memory with Register | |
| 8887 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8888 %{ | |
| 8889 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8890 effect(KILL cr); | |
| 8891 | |
| 8892 ins_cost(150); | |
| 8893 format %{ "orl $dst, $src\t# int" %} | |
| 8894 opcode(0x09); /* Opcode 09 /r */ | |
| 8895 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8896 ins_pipe(ialu_mem_reg); | |
| 8897 %} | |
| 8898 | |
| 8899 // Or Memory with Immediate | |
| 8900 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8901 %{ | |
| 8902 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8903 effect(KILL cr); | |
| 8904 | |
| 8905 ins_cost(125); | |
| 8906 format %{ "orl $dst, $src\t# int" %} | |
| 8907 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 8908 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8909 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8910 ins_pipe(ialu_mem_imm); | |
| 8911 %} | |
| 8912 | |
| 8913 // Xor Instructions | |
| 8914 // Xor Register with Register | |
| 8915 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8916 %{ | |
| 8917 match(Set dst (XorI dst src)); | |
| 8918 effect(KILL cr); | |
| 8919 | |
| 8920 format %{ "xorl $dst, $src\t# int" %} | |
| 8921 opcode(0x33); | |
| 8922 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8923 ins_pipe(ialu_reg_reg); | |
| 8924 %} | |
| 8925 | |
| 403 | 8926 // Xor Register with Immediate -1 |
| 8927 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
|
2404
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|
8928 match(Set dst (XorI dst imm)); |
|
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|
8929 |
|
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diff
changeset
|
8930 format %{ "not $dst" %} |
| 403 | 8931 ins_encode %{ |
| 8932 __ notl($dst$$Register); | |
| 8933 %} | |
| 8934 ins_pipe(ialu_reg); | |
| 8935 %} | |
| 8936 | |
| 0 | 8937 // Xor Register with Immediate |
| 8938 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8939 %{ | |
| 8940 match(Set dst (XorI dst src)); | |
| 8941 effect(KILL cr); | |
| 8942 | |
| 8943 format %{ "xorl $dst, $src\t# int" %} | |
| 8944 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 8945 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8946 ins_pipe(ialu_reg); | |
| 8947 %} | |
| 8948 | |
| 8949 // Xor Register with Memory | |
| 8950 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8951 %{ | |
| 8952 match(Set dst (XorI dst (LoadI src))); | |
| 8953 effect(KILL cr); | |
| 8954 | |
| 8955 ins_cost(125); | |
| 8956 format %{ "xorl $dst, $src\t# int" %} | |
| 8957 opcode(0x33); | |
| 8958 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8959 ins_pipe(ialu_reg_mem); | |
| 8960 %} | |
| 8961 | |
| 8962 // Xor Memory with Register | |
| 8963 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8964 %{ | |
| 8965 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8966 effect(KILL cr); | |
| 8967 | |
| 8968 ins_cost(150); | |
| 8969 format %{ "xorl $dst, $src\t# int" %} | |
| 8970 opcode(0x31); /* Opcode 31 /r */ | |
| 8971 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8972 ins_pipe(ialu_mem_reg); | |
| 8973 %} | |
| 8974 | |
| 8975 // Xor Memory with Immediate | |
| 8976 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8977 %{ | |
| 8978 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8979 effect(KILL cr); | |
| 8980 | |
| 8981 ins_cost(125); | |
| 8982 format %{ "xorl $dst, $src\t# int" %} | |
| 8983 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 8984 ins_encode(REX_mem(dst), OpcSE(src), | |
| 8985 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 8986 ins_pipe(ialu_mem_imm); | |
| 8987 %} | |
| 8988 | |
| 8989 | |
| 8990 // Long Logical Instructions | |
| 8991 | |
| 8992 // And Instructions | |
| 8993 // And Register with Register | |
| 8994 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8995 %{ | |
| 8996 match(Set dst (AndL dst src)); | |
| 8997 effect(KILL cr); | |
| 8998 | |
| 8999 format %{ "andq $dst, $src\t# long" %} | |
| 9000 opcode(0x23); | |
| 9001 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9002 ins_pipe(ialu_reg_reg); | |
| 9003 %} | |
| 9004 | |
| 9005 // And Register with Immediate 255 | |
| 9006 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 9007 %{ | |
| 9008 match(Set dst (AndL dst src)); | |
| 9009 | |
|
569
2cacccded90f
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diff
changeset
|
9010 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 9011 opcode(0x0F, 0xB6); |
| 9012 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9013 ins_pipe(ialu_reg); | |
| 9014 %} | |
| 9015 | |
| 9016 // And Register with Immediate 65535 | |
|
569
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558
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|
9017 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 9018 %{ |
| 9019 match(Set dst (AndL dst src)); | |
| 9020 | |
| 9021 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 9022 opcode(0x0F, 0xB7); | |
| 9023 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9024 ins_pipe(ialu_reg); | |
| 9025 %} | |
| 9026 | |
| 9027 // And Register with Immediate | |
| 9028 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9029 %{ | |
| 9030 match(Set dst (AndL dst src)); | |
| 9031 effect(KILL cr); | |
| 9032 | |
| 9033 format %{ "andq $dst, $src\t# long" %} | |
| 9034 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9035 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9036 ins_pipe(ialu_reg); | |
| 9037 %} | |
| 9038 | |
| 9039 // And Register with Memory | |
| 9040 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9041 %{ | |
| 9042 match(Set dst (AndL dst (LoadL src))); | |
| 9043 effect(KILL cr); | |
| 9044 | |
| 9045 ins_cost(125); | |
| 9046 format %{ "andq $dst, $src\t# long" %} | |
| 9047 opcode(0x23); | |
| 9048 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9049 ins_pipe(ialu_reg_mem); | |
| 9050 %} | |
| 9051 | |
| 9052 // And Memory with Register | |
| 9053 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9054 %{ | |
| 9055 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9056 effect(KILL cr); | |
| 9057 | |
| 9058 ins_cost(150); | |
| 9059 format %{ "andq $dst, $src\t# long" %} | |
| 9060 opcode(0x21); /* Opcode 21 /r */ | |
| 9061 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9062 ins_pipe(ialu_mem_reg); | |
| 9063 %} | |
| 9064 | |
| 9065 // And Memory with Immediate | |
| 9066 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9067 %{ | |
| 9068 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 9069 effect(KILL cr); | |
| 9070 | |
| 9071 ins_cost(125); | |
| 9072 format %{ "andq $dst, $src\t# long" %} | |
| 9073 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9074 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9075 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9076 ins_pipe(ialu_mem_imm); | |
| 9077 %} | |
| 9078 | |
|
17729
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|
9079 // BMI1 instructions |
|
8a8ff6b577ed
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|
9080 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
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|
9081 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2))); |
|
8a8ff6b577ed
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diff
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|
9082 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
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|
9083 effect(KILL cr); |
|
8a8ff6b577ed
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diff
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|
9084 |
|
8a8ff6b577ed
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|
9085 ins_cost(125); |
|
8a8ff6b577ed
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diff
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|
9086 format %{ "andnq $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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|
9087 |
|
8a8ff6b577ed
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diff
changeset
|
9088 ins_encode %{ |
|
8a8ff6b577ed
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diff
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|
9089 __ andnq($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
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diff
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|
9090 %} |
|
8a8ff6b577ed
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diff
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|
9091 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
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|
9092 %} |
|
8a8ff6b577ed
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changeset
|
9093 |
|
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|
9094 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{ |
|
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|
9095 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
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diff
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|
9096 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
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|
9097 effect(KILL cr); |
|
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diff
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|
9098 |
|
8a8ff6b577ed
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diff
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|
9099 format %{ "andnq $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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diff
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|
9100 |
|
8a8ff6b577ed
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diff
changeset
|
9101 ins_encode %{ |
|
8a8ff6b577ed
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diff
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|
9102 __ andnq($dst$$Register, $src1$$Register, $src2$$Register); |
|
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|
9103 %} |
|
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diff
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|
9104 ins_pipe(ialu_reg_mem); |
|
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diff
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|
9105 %} |
|
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changeset
|
9106 |
|
8a8ff6b577ed
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diff
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|
9107 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{ |
|
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|
9108 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8a8ff6b577ed
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diff
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|
9109 predicate(UseBMI1Instructions); |
|
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diff
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|
9110 effect(KILL cr); |
|
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diff
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|
9111 |
|
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diff
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|
9112 format %{ "blsiq $dst, $src" %} |
|
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diff
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|
9113 |
|
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diff
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|
9114 ins_encode %{ |
|
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diff
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|
9115 __ blsiq($dst$$Register, $src$$Register); |
|
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diff
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|
9116 %} |
|
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|
9117 ins_pipe(ialu_reg); |
|
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diff
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|
9118 %} |
|
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|
9119 |
|
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changeset
|
9120 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{ |
|
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8031321: Support Intel bit manipulation instructions
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|
9121 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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diff
changeset
|
9122 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
9123 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
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diff
changeset
|
9124 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
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diff
changeset
|
9125 ins_cost(125); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9126 format %{ "blsiq $dst, $src" %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9127 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9128 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
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diff
changeset
|
9129 __ blsiq($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9130 %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9131 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
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diff
changeset
|
9132 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
9133 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9134 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9135 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
9136 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9137 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
9138 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9139 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9140 ins_cost(125); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9141 format %{ "blsmskq $dst, $src" %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9142 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
9143 ins_encode %{ |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9144 __ blsmskq($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9145 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9146 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9147 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9148 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
9149 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9150 %{ |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
9151 match(Set dst (XorL (AddL src minus_1) src)); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9152 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9153 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9154 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
9155 format %{ "blsmskq $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9156 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9157 ins_encode %{ |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9158 __ blsmskq($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9159 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9160 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9161 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9162 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9163 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9164 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
9165 %{ |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
9166 match(Set dst (AndL (AddL src minus_1) src) ); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9167 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9168 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9169 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
9170 format %{ "blsrq $dst, $src" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9171 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9172 ins_encode %{ |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
9173 __ blsrq($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
9174 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9175 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9176 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9177 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9178 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9179 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9180 %{ |
|
8a8ff6b577ed
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17726
diff
changeset
|
9181 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9182 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9183 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9184 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9185 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9186 format %{ "blsrq $dst, $src" %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9187 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9188 ins_encode %{ |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9189 __ blsrq($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9190 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
9191 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9192 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
9193 %} |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
9194 |
| 0 | 9195 // Or Instructions |
| 9196 // Or Register with Register | |
| 9197 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9198 %{ | |
| 9199 match(Set dst (OrL dst src)); | |
| 9200 effect(KILL cr); | |
| 9201 | |
| 9202 format %{ "orq $dst, $src\t# long" %} | |
| 9203 opcode(0x0B); | |
| 9204 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9205 ins_pipe(ialu_reg_reg); | |
| 9206 %} | |
| 9207 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9208 // Use any_RegP to match R15 (TLS register) without spilling. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9209 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9210 match(Set dst (OrL dst (CastP2X src))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9211 effect(KILL cr); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9212 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9213 format %{ "orq $dst, $src\t# long" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9214 opcode(0x0B); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9215 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9216 ins_pipe(ialu_reg_reg); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9217 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9218 |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
9219 |
| 0 | 9220 // Or Register with Immediate |
| 9221 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9222 %{ | |
| 9223 match(Set dst (OrL dst src)); | |
| 9224 effect(KILL cr); | |
| 9225 | |
| 9226 format %{ "orq $dst, $src\t# long" %} | |
| 9227 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9228 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9229 ins_pipe(ialu_reg); | |
| 9230 %} | |
| 9231 | |
| 9232 // Or Register with Memory | |
| 9233 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9234 %{ | |
| 9235 match(Set dst (OrL dst (LoadL src))); | |
| 9236 effect(KILL cr); | |
| 9237 | |
| 9238 ins_cost(125); | |
| 9239 format %{ "orq $dst, $src\t# long" %} | |
| 9240 opcode(0x0B); | |
| 9241 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9242 ins_pipe(ialu_reg_mem); | |
| 9243 %} | |
| 9244 | |
| 9245 // Or Memory with Register | |
| 9246 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9247 %{ | |
| 9248 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9249 effect(KILL cr); | |
| 9250 | |
| 9251 ins_cost(150); | |
| 9252 format %{ "orq $dst, $src\t# long" %} | |
| 9253 opcode(0x09); /* Opcode 09 /r */ | |
| 9254 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9255 ins_pipe(ialu_mem_reg); | |
| 9256 %} | |
| 9257 | |
| 9258 // Or Memory with Immediate | |
| 9259 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9260 %{ | |
| 9261 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 9262 effect(KILL cr); | |
| 9263 | |
| 9264 ins_cost(125); | |
| 9265 format %{ "orq $dst, $src\t# long" %} | |
| 9266 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9267 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9268 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9269 ins_pipe(ialu_mem_imm); | |
| 9270 %} | |
| 9271 | |
| 9272 // Xor Instructions | |
| 9273 // Xor Register with Register | |
| 9274 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 9275 %{ | |
| 9276 match(Set dst (XorL dst src)); | |
| 9277 effect(KILL cr); | |
| 9278 | |
| 9279 format %{ "xorq $dst, $src\t# long" %} | |
| 9280 opcode(0x33); | |
| 9281 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 9282 ins_pipe(ialu_reg_reg); | |
| 9283 %} | |
| 9284 | |
| 403 | 9285 // Xor Register with Immediate -1 |
| 9286 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
|
2404
b40d4fa697bf
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iveresov
parents:
2401
diff
changeset
|
9287 match(Set dst (XorL dst imm)); |
|
b40d4fa697bf
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iveresov
parents:
2401
diff
changeset
|
9288 |
|
b40d4fa697bf
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iveresov
parents:
2401
diff
changeset
|
9289 format %{ "notq $dst" %} |
| 403 | 9290 ins_encode %{ |
| 9291 __ notq($dst$$Register); | |
| 9292 %} | |
| 9293 ins_pipe(ialu_reg); | |
| 9294 %} | |
| 9295 | |
| 0 | 9296 // Xor Register with Immediate |
| 9297 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 9298 %{ | |
| 9299 match(Set dst (XorL dst src)); | |
| 9300 effect(KILL cr); | |
| 9301 | |
| 9302 format %{ "xorq $dst, $src\t# long" %} | |
| 9303 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9304 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 9305 ins_pipe(ialu_reg); | |
| 9306 %} | |
| 9307 | |
| 9308 // Xor Register with Memory | |
| 9309 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 9310 %{ | |
| 9311 match(Set dst (XorL dst (LoadL src))); | |
| 9312 effect(KILL cr); | |
| 9313 | |
| 9314 ins_cost(125); | |
| 9315 format %{ "xorq $dst, $src\t# long" %} | |
| 9316 opcode(0x33); | |
| 9317 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 9318 ins_pipe(ialu_reg_mem); | |
| 9319 %} | |
| 9320 | |
| 9321 // Xor Memory with Register | |
| 9322 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 9323 %{ | |
| 9324 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9325 effect(KILL cr); | |
| 9326 | |
| 9327 ins_cost(150); | |
| 9328 format %{ "xorq $dst, $src\t# long" %} | |
| 9329 opcode(0x31); /* Opcode 31 /r */ | |
| 9330 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 9331 ins_pipe(ialu_mem_reg); | |
| 9332 %} | |
| 9333 | |
| 9334 // Xor Memory with Immediate | |
| 9335 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 9336 %{ | |
| 9337 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 9338 effect(KILL cr); | |
| 9339 | |
| 9340 ins_cost(125); | |
| 9341 format %{ "xorq $dst, $src\t# long" %} | |
| 9342 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 9343 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 9344 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9345 ins_pipe(ialu_mem_imm); | |
| 9346 %} | |
| 9347 | |
| 9348 // Convert Int to Boolean | |
| 9349 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9350 %{ | |
| 9351 match(Set dst (Conv2B src)); | |
| 9352 effect(KILL cr); | |
| 9353 | |
| 9354 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 9355 "setnz $dst\n\t" | |
| 9356 "movzbl $dst, $dst" %} | |
| 9357 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 9358 setNZ_reg(dst), | |
| 9359 REX_reg_breg(dst, dst), // movzbl | |
| 9360 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9361 ins_pipe(pipe_slow); // XXX | |
| 9362 %} | |
| 9363 | |
| 9364 // Convert Pointer to Boolean | |
| 9365 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 9366 %{ | |
| 9367 match(Set dst (Conv2B src)); | |
| 9368 effect(KILL cr); | |
| 9369 | |
| 9370 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 9371 "setnz $dst\n\t" | |
| 9372 "movzbl $dst, $dst" %} | |
| 9373 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 9374 setNZ_reg(dst), | |
| 9375 REX_reg_breg(dst, dst), // movzbl | |
| 9376 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 9377 ins_pipe(pipe_slow); // XXX | |
| 9378 %} | |
| 9379 | |
| 9380 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 9381 %{ | |
| 9382 match(Set dst (CmpLTMask p q)); | |
| 9383 effect(KILL cr); | |
| 9384 | |
| 9154 | 9385 ins_cost(400); |
| 0 | 9386 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" |
| 9387 "setlt $dst\n\t" | |
| 9388 "movzbl $dst, $dst\n\t" | |
| 9389 "negl $dst" %} | |
| 9390 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 9391 setLT_reg(dst), | |
| 9392 REX_reg_breg(dst, dst), // movzbl | |
| 9393 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 9394 neg_reg(dst)); | |
| 9395 ins_pipe(pipe_slow); | |
| 9396 %} | |
| 9397 | |
| 9398 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 9399 %{ | |
| 9400 match(Set dst (CmpLTMask dst zero)); | |
| 9401 effect(KILL cr); | |
| 9402 | |
| 9154 | 9403 ins_cost(100); |
| 0 | 9404 format %{ "sarl $dst, #31\t# cmpLTMask0" %} |
| 9154 | 9405 ins_encode %{ |
| 9406 __ sarl($dst$$Register, 31); | |
| 9407 %} | |
| 0 | 9408 ins_pipe(ialu_reg); |
| 9409 %} | |
| 9410 | |
| 9154 | 9411 /* Better to save a register than avoid a branch */ |
| 9412 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 0 | 9413 %{ |
| 9414 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9154 | 9415 effect(KILL cr); |
| 9416 ins_cost(300); | |
| 9417 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t" | |
| 9418 "jge done\n\t" | |
| 9419 "addl $p,$y\n" | |
| 9420 "done: " %} | |
|
3410
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|
9421 ins_encode %{ |
|
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|
9422 Register Rp = $p$$Register; |
|
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|
9423 Register Rq = $q$$Register; |
|
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|
9424 Register Ry = $y$$Register; |
| 9154 | 9425 Label done; |
|
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|
9426 __ subl(Rp, Rq); |
| 9154 | 9427 __ jccb(Assembler::greaterEqual, done); |
| 9428 __ addl(Rp, Ry); | |
| 9429 __ bind(done); | |
|
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|
9430 %} |
| 0 | 9431 ins_pipe(pipe_cmplt); |
| 9432 %} | |
| 9433 | |
| 9154 | 9434 /* Better to save a register than avoid a branch */ |
| 9435 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr) | |
| 9436 %{ | |
| 9437 match(Set y (AndI (CmpLTMask p q) y)); | |
| 9438 effect(KILL cr); | |
| 9439 | |
| 9440 ins_cost(300); | |
| 9441 | |
| 9442 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t" | |
| 9443 "jlt done\n\t" | |
| 9444 "xorl $y, $y\n" | |
| 9445 "done: " %} | |
| 9446 ins_encode %{ | |
| 9447 Register Rp = $p$$Register; | |
| 9448 Register Rq = $q$$Register; | |
| 9449 Register Ry = $y$$Register; | |
| 9450 Label done; | |
| 9451 __ cmpl(Rp, Rq); | |
| 9452 __ jccb(Assembler::less, done); | |
| 9453 __ xorl(Ry, Ry); | |
| 9454 __ bind(done); | |
| 9455 %} | |
| 9456 ins_pipe(pipe_cmplt); | |
| 9457 %} | |
| 9458 | |
| 9459 | |
| 0 | 9460 //---------- FP Instructions------------------------------------------------ |
| 9461 | |
| 9462 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 9463 %{ | |
| 9464 match(Set cr (CmpF src1 src2)); | |
| 9465 | |
| 9466 ins_cost(145); | |
| 9467 format %{ "ucomiss $src1, $src2\n\t" | |
| 9468 "jnp,s exit\n\t" | |
| 9469 "pushfq\t# saw NaN, set CF\n\t" | |
| 9470 "andq [rsp], #0xffffff2b\n\t" | |
| 9471 "popfq\n" | |
| 4759 | 9472 "exit:" %} |
| 9473 ins_encode %{ | |
| 9474 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9475 emit_cmpfp_fixup(_masm); | |
| 9476 %} | |
| 0 | 9477 ins_pipe(pipe_slow); |
| 9478 %} | |
| 9479 | |
|
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|
9480 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
9481 match(Set cr (CmpF src1 src2)); |
|
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|
9482 |
| 4759 | 9483 ins_cost(100); |
|
415
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|
9484 format %{ "ucomiss $src1, $src2" %} |
|
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|
9485 ins_encode %{ |
|
4d9884b01ba6
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diff
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|
9486 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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|
9487 %} |
|
4d9884b01ba6
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diff
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|
9488 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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diff
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|
9489 %} |
|
4d9884b01ba6
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403
diff
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|
9490 |
| 0 | 9491 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 9492 %{ | |
| 9493 match(Set cr (CmpF src1 (LoadF src2))); | |
| 9494 | |
| 9495 ins_cost(145); | |
| 9496 format %{ "ucomiss $src1, $src2\n\t" | |
| 9497 "jnp,s exit\n\t" | |
| 9498 "pushfq\t# saw NaN, set CF\n\t" | |
| 9499 "andq [rsp], #0xffffff2b\n\t" | |
| 9500 "popfq\n" | |
| 4759 | 9501 "exit:" %} |
| 9502 ins_encode %{ | |
| 9503 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9504 emit_cmpfp_fixup(_masm); | |
| 9505 %} | |
| 0 | 9506 ins_pipe(pipe_slow); |
| 9507 %} | |
| 9508 | |
|
415
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changeset
|
9509 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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diff
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|
9510 match(Set cr (CmpF src1 (LoadF src2))); |
|
4d9884b01ba6
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diff
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|
9511 |
|
4d9884b01ba6
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diff
changeset
|
9512 ins_cost(100); |
|
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diff
changeset
|
9513 format %{ "ucomiss $src1, $src2" %} |
| 4759 | 9514 ins_encode %{ |
| 9515 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9516 %} | |
|
415
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|
9517 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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diff
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|
9518 %} |
|
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parents:
403
diff
changeset
|
9519 |
| 2008 | 9520 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{ |
| 9521 match(Set cr (CmpF src con)); | |
| 0 | 9522 |
| 9523 ins_cost(145); | |
| 2008 | 9524 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9525 "jnp,s exit\n\t" |
| 9526 "pushfq\t# saw NaN, set CF\n\t" | |
| 9527 "andq [rsp], #0xffffff2b\n\t" | |
| 9528 "popfq\n" | |
| 4759 | 9529 "exit:" %} |
| 2008 | 9530 ins_encode %{ |
| 9531 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 3457 | 9532 emit_cmpfp_fixup(_masm); |
| 2008 | 9533 %} |
| 9534 ins_pipe(pipe_slow); | |
| 9535 %} | |
| 9536 | |
| 9537 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{ | |
| 9538 match(Set cr (CmpF src con)); | |
|
415
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parents:
403
diff
changeset
|
9539 ins_cost(100); |
| 2008 | 9540 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %} |
| 9541 ins_encode %{ | |
| 9542 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 9543 %} | |
|
415
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changeset
|
9544 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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diff
changeset
|
9545 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9546 |
| 0 | 9547 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 9548 %{ | |
| 9549 match(Set cr (CmpD src1 src2)); | |
| 9550 | |
| 9551 ins_cost(145); | |
| 9552 format %{ "ucomisd $src1, $src2\n\t" | |
| 9553 "jnp,s exit\n\t" | |
| 9554 "pushfq\t# saw NaN, set CF\n\t" | |
| 9555 "andq [rsp], #0xffffff2b\n\t" | |
| 9556 "popfq\n" | |
| 4759 | 9557 "exit:" %} |
| 9558 ins_encode %{ | |
| 9559 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9560 emit_cmpfp_fixup(_masm); | |
| 9561 %} | |
| 0 | 9562 ins_pipe(pipe_slow); |
| 9563 %} | |
| 9564 | |
|
415
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diff
changeset
|
9565 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9566 match(Set cr (CmpD src1 src2)); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
9567 |
|
4d9884b01ba6
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403
diff
changeset
|
9568 ins_cost(100); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
9569 format %{ "ucomisd $src1, $src2 test" %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9570 ins_encode %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9571 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9572 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9573 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9574 %} |
|
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parents:
403
diff
changeset
|
9575 |
| 0 | 9576 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 9577 %{ | |
| 9578 match(Set cr (CmpD src1 (LoadD src2))); | |
| 9579 | |
| 9580 ins_cost(145); | |
| 9581 format %{ "ucomisd $src1, $src2\n\t" | |
| 9582 "jnp,s exit\n\t" | |
| 9583 "pushfq\t# saw NaN, set CF\n\t" | |
| 9584 "andq [rsp], #0xffffff2b\n\t" | |
| 9585 "popfq\n" | |
| 4759 | 9586 "exit:" %} |
| 9587 ins_encode %{ | |
| 9588 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9589 emit_cmpfp_fixup(_masm); | |
| 9590 %} | |
| 0 | 9591 ins_pipe(pipe_slow); |
| 9592 %} | |
| 9593 | |
|
415
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diff
changeset
|
9594 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
9595 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9596 |
|
4d9884b01ba6
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403
diff
changeset
|
9597 ins_cost(100); |
|
4d9884b01ba6
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diff
changeset
|
9598 format %{ "ucomisd $src1, $src2" %} |
| 4759 | 9599 ins_encode %{ |
| 9600 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9601 %} | |
|
415
4d9884b01ba6
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changeset
|
9602 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9603 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
9604 |
| 2008 | 9605 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{ |
| 9606 match(Set cr (CmpD src con)); | |
| 0 | 9607 |
| 9608 ins_cost(145); | |
| 2008 | 9609 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9610 "jnp,s exit\n\t" |
| 9611 "pushfq\t# saw NaN, set CF\n\t" | |
| 9612 "andq [rsp], #0xffffff2b\n\t" | |
| 9613 "popfq\n" | |
| 4759 | 9614 "exit:" %} |
| 2008 | 9615 ins_encode %{ |
| 9616 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 3457 | 9617 emit_cmpfp_fixup(_masm); |
| 2008 | 9618 %} |
| 9619 ins_pipe(pipe_slow); | |
| 9620 %} | |
| 9621 | |
| 9622 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{ | |
| 9623 match(Set cr (CmpD src con)); | |
|
415
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diff
changeset
|
9624 ins_cost(100); |
| 2008 | 9625 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %} |
| 9626 ins_encode %{ | |
| 9627 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 9628 %} | |
|
415
4d9884b01ba6
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403
diff
changeset
|
9629 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9630 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
9631 |
| 0 | 9632 // Compare into -1,0,1 |
| 9633 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 9634 %{ | |
| 9635 match(Set dst (CmpF3 src1 src2)); | |
| 9636 effect(KILL cr); | |
| 9637 | |
| 9638 ins_cost(275); | |
| 9639 format %{ "ucomiss $src1, $src2\n\t" | |
| 9640 "movl $dst, #-1\n\t" | |
| 9641 "jp,s done\n\t" | |
| 9642 "jb,s done\n\t" | |
| 9643 "setne $dst\n\t" | |
| 9644 "movzbl $dst, $dst\n" | |
| 9645 "done:" %} | |
| 4759 | 9646 ins_encode %{ |
| 9647 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9648 emit_cmpfp3(_masm, $dst$$Register); | |
| 9649 %} | |
| 0 | 9650 ins_pipe(pipe_slow); |
| 9651 %} | |
| 9652 | |
| 9653 // Compare into -1,0,1 | |
| 9654 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 9655 %{ | |
| 9656 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 9657 effect(KILL cr); | |
| 9658 | |
| 9659 ins_cost(275); | |
| 9660 format %{ "ucomiss $src1, $src2\n\t" | |
| 9661 "movl $dst, #-1\n\t" | |
| 9662 "jp,s done\n\t" | |
| 9663 "jb,s done\n\t" | |
| 9664 "setne $dst\n\t" | |
| 9665 "movzbl $dst, $dst\n" | |
| 9666 "done:" %} | |
| 4759 | 9667 ins_encode %{ |
| 9668 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 9669 emit_cmpfp3(_masm, $dst$$Register); | |
| 9670 %} | |
| 0 | 9671 ins_pipe(pipe_slow); |
| 9672 %} | |
| 9673 | |
| 9674 // Compare into -1,0,1 | |
| 2008 | 9675 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{ |
| 9676 match(Set dst (CmpF3 src con)); | |
| 0 | 9677 effect(KILL cr); |
| 9678 | |
| 9679 ins_cost(275); | |
| 2008 | 9680 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t" |
| 0 | 9681 "movl $dst, #-1\n\t" |
| 9682 "jp,s done\n\t" | |
| 9683 "jb,s done\n\t" | |
| 9684 "setne $dst\n\t" | |
| 9685 "movzbl $dst, $dst\n" | |
| 9686 "done:" %} | |
| 2008 | 9687 ins_encode %{ |
| 9688 __ ucomiss($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9689 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9690 %} |
| 0 | 9691 ins_pipe(pipe_slow); |
| 9692 %} | |
| 9693 | |
| 9694 // Compare into -1,0,1 | |
| 9695 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 9696 %{ | |
| 9697 match(Set dst (CmpD3 src1 src2)); | |
| 9698 effect(KILL cr); | |
| 9699 | |
| 9700 ins_cost(275); | |
| 9701 format %{ "ucomisd $src1, $src2\n\t" | |
| 9702 "movl $dst, #-1\n\t" | |
| 9703 "jp,s done\n\t" | |
| 9704 "jb,s done\n\t" | |
| 9705 "setne $dst\n\t" | |
| 9706 "movzbl $dst, $dst\n" | |
| 9707 "done:" %} | |
| 4759 | 9708 ins_encode %{ |
| 9709 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9710 emit_cmpfp3(_masm, $dst$$Register); | |
| 9711 %} | |
| 0 | 9712 ins_pipe(pipe_slow); |
| 9713 %} | |
| 9714 | |
| 9715 // Compare into -1,0,1 | |
| 9716 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 9717 %{ | |
| 9718 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 9719 effect(KILL cr); | |
| 9720 | |
| 9721 ins_cost(275); | |
| 9722 format %{ "ucomisd $src1, $src2\n\t" | |
| 9723 "movl $dst, #-1\n\t" | |
| 9724 "jp,s done\n\t" | |
| 9725 "jb,s done\n\t" | |
| 9726 "setne $dst\n\t" | |
| 9727 "movzbl $dst, $dst\n" | |
| 9728 "done:" %} | |
| 4759 | 9729 ins_encode %{ |
| 9730 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9731 emit_cmpfp3(_masm, $dst$$Register); | |
| 9732 %} | |
| 0 | 9733 ins_pipe(pipe_slow); |
| 9734 %} | |
| 9735 | |
| 9736 // Compare into -1,0,1 | |
| 2008 | 9737 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{ |
| 9738 match(Set dst (CmpD3 src con)); | |
| 0 | 9739 effect(KILL cr); |
| 9740 | |
| 9741 ins_cost(275); | |
| 2008 | 9742 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9743 "movl $dst, #-1\n\t" |
| 9744 "jp,s done\n\t" | |
| 9745 "jb,s done\n\t" | |
| 9746 "setne $dst\n\t" | |
| 9747 "movzbl $dst, $dst\n" | |
| 9748 "done:" %} | |
| 2008 | 9749 ins_encode %{ |
| 9750 __ ucomisd($src$$XMMRegister, $constantaddress($con)); | |
| 4759 | 9751 emit_cmpfp3(_masm, $dst$$Register); |
| 2008 | 9752 %} |
| 0 | 9753 ins_pipe(pipe_slow); |
| 9754 %} | |
| 9755 | |
| 9756 // -----------Trig and Trancendental Instructions------------------------------ | |
| 9757 instruct cosD_reg(regD dst) %{ | |
| 9758 match(Set dst (CosD dst)); | |
| 9759 | |
| 9760 format %{ "dcos $dst\n\t" %} | |
| 9761 opcode(0xD9, 0xFF); | |
| 9762 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9763 ins_pipe( pipe_slow ); | |
| 9764 %} | |
| 9765 | |
| 9766 instruct sinD_reg(regD dst) %{ | |
| 9767 match(Set dst (SinD dst)); | |
| 9768 | |
| 9769 format %{ "dsin $dst\n\t" %} | |
| 9770 opcode(0xD9, 0xFE); | |
| 9771 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 9772 ins_pipe( pipe_slow ); | |
| 9773 %} | |
| 9774 | |
| 9775 instruct tanD_reg(regD dst) %{ | |
| 9776 match(Set dst (TanD dst)); | |
| 9777 | |
| 9778 format %{ "dtan $dst\n\t" %} | |
| 9779 ins_encode( Push_SrcXD(dst), | |
| 9780 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 9781 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 9782 Push_ResultXD(dst) ); | |
| 9783 ins_pipe( pipe_slow ); | |
| 9784 %} | |
| 9785 | |
| 9786 instruct log10D_reg(regD dst) %{ | |
| 9787 // The source and result Double operands in XMM registers | |
| 9788 match(Set dst (Log10D dst)); | |
| 9789 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9790 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9791 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 9792 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 9793 %} | |
| 9794 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9795 Push_SrcXD(dst), | |
| 9796 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9797 Push_ResultXD(dst)); | |
| 9798 | |
| 9799 ins_pipe( pipe_slow ); | |
| 9800 %} | |
| 9801 | |
| 9802 instruct logD_reg(regD dst) %{ | |
| 9803 // The source and result Double operands in XMM registers | |
| 9804 match(Set dst (LogD dst)); | |
| 9805 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9806 // fyl2x ; compute log_e(2) * log_2(x) | |
| 9807 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 9808 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 9809 %} | |
| 9810 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 9811 Push_SrcXD(dst), | |
| 9812 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 9813 Push_ResultXD(dst)); | |
| 9814 ins_pipe( pipe_slow ); | |
| 9815 %} | |
| 9816 | |
|
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9817 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
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9818 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power |
|
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9819 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
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9820 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
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9821 ins_encode %{ |
|
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9822 __ subptr(rsp, 8); |
|
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9823 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
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9824 __ fld_d(Address(rsp, 0)); |
|
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9825 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
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9826 __ fld_d(Address(rsp, 0)); |
|
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9827 __ fast_pow(); |
|
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|
9828 __ fstp_d(Address(rsp, 0)); |
|
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9829 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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9830 __ addptr(rsp, 8); |
|
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|
9831 %} |
|
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|
9832 ins_pipe( pipe_slow ); |
|
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9833 %} |
|
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|
9834 |
|
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9835 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{ |
|
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9836 match(Set dst (ExpD src)); |
|
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|
9837 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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|
9838 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
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|
9839 ins_encode %{ |
|
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|
9840 __ subptr(rsp, 8); |
|
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9841 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
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|
9842 __ fld_d(Address(rsp, 0)); |
|
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|
9843 __ fast_exp(); |
|
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|
9844 __ fstp_d(Address(rsp, 0)); |
|
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9845 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
9846 __ addptr(rsp, 8); |
|
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|
9847 %} |
|
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|
9848 ins_pipe( pipe_slow ); |
|
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|
9849 %} |
| 0 | 9850 |
| 9851 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9852 | |
| 9853 instruct roundFloat_nop(regF dst) | |
| 9854 %{ | |
| 9855 match(Set dst (RoundFloat dst)); | |
| 9856 | |
| 9857 ins_cost(0); | |
| 9858 ins_encode(); | |
| 9859 ins_pipe(empty); | |
| 9860 %} | |
| 9861 | |
| 9862 instruct roundDouble_nop(regD dst) | |
| 9863 %{ | |
| 9864 match(Set dst (RoundDouble dst)); | |
| 9865 | |
| 9866 ins_cost(0); | |
| 9867 ins_encode(); | |
| 9868 ins_pipe(empty); | |
| 9869 %} | |
| 9870 | |
| 9871 instruct convF2D_reg_reg(regD dst, regF src) | |
| 9872 %{ | |
| 9873 match(Set dst (ConvF2D src)); | |
| 9874 | |
| 9875 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9876 ins_encode %{ |
| 9877 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9878 %} | |
| 0 | 9879 ins_pipe(pipe_slow); // XXX |
| 9880 %} | |
| 9881 | |
| 9882 instruct convF2D_reg_mem(regD dst, memory src) | |
| 9883 %{ | |
| 9884 match(Set dst (ConvF2D (LoadF src))); | |
| 9885 | |
| 9886 format %{ "cvtss2sd $dst, $src" %} | |
| 4759 | 9887 ins_encode %{ |
| 9888 __ cvtss2sd ($dst$$XMMRegister, $src$$Address); | |
| 9889 %} | |
| 0 | 9890 ins_pipe(pipe_slow); // XXX |
| 9891 %} | |
| 9892 | |
| 9893 instruct convD2F_reg_reg(regF dst, regD src) | |
| 9894 %{ | |
| 9895 match(Set dst (ConvD2F src)); | |
| 9896 | |
| 9897 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9898 ins_encode %{ |
| 9899 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 9900 %} | |
| 0 | 9901 ins_pipe(pipe_slow); // XXX |
| 9902 %} | |
| 9903 | |
| 9904 instruct convD2F_reg_mem(regF dst, memory src) | |
| 9905 %{ | |
| 9906 match(Set dst (ConvD2F (LoadD src))); | |
| 9907 | |
| 9908 format %{ "cvtsd2ss $dst, $src" %} | |
| 4759 | 9909 ins_encode %{ |
| 9910 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address); | |
| 9911 %} | |
| 0 | 9912 ins_pipe(pipe_slow); // XXX |
| 9913 %} | |
| 9914 | |
| 9915 // XXX do mem variants | |
| 9916 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 9917 %{ | |
| 9918 match(Set dst (ConvF2I src)); | |
| 9919 effect(KILL cr); | |
| 9920 | |
| 9921 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 9922 "cmpl $dst, #0x80000000\n\t" | |
| 9923 "jne,s done\n\t" | |
| 9924 "subq rsp, #8\n\t" | |
| 9925 "movss [rsp], $src\n\t" | |
| 9926 "call f2i_fixup\n\t" | |
| 9927 "popq $dst\n" | |
| 9928 "done: "%} | |
| 4759 | 9929 ins_encode %{ |
| 9930 Label done; | |
| 9931 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 9932 __ cmpl($dst$$Register, 0x80000000); | |
| 9933 __ jccb(Assembler::notEqual, done); | |
| 9934 __ subptr(rsp, 8); | |
| 9935 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9936 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); | |
| 9937 __ pop($dst$$Register); | |
| 9938 __ bind(done); | |
| 9939 %} | |
| 0 | 9940 ins_pipe(pipe_slow); |
| 9941 %} | |
| 9942 | |
| 9943 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 9944 %{ | |
| 9945 match(Set dst (ConvF2L src)); | |
| 9946 effect(KILL cr); | |
| 9947 | |
| 9948 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 9949 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 9950 "jne,s done\n\t" | |
| 9951 "subq rsp, #8\n\t" | |
| 9952 "movss [rsp], $src\n\t" | |
| 9953 "call f2l_fixup\n\t" | |
| 9954 "popq $dst\n" | |
| 9955 "done: "%} | |
| 4759 | 9956 ins_encode %{ |
| 9957 Label done; | |
| 9958 __ cvttss2siq($dst$$Register, $src$$XMMRegister); | |
| 9959 __ cmp64($dst$$Register, | |
| 9960 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 9961 __ jccb(Assembler::notEqual, done); | |
| 9962 __ subptr(rsp, 8); | |
| 9963 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 9964 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); | |
| 9965 __ pop($dst$$Register); | |
| 9966 __ bind(done); | |
| 9967 %} | |
| 0 | 9968 ins_pipe(pipe_slow); |
| 9969 %} | |
| 9970 | |
| 9971 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 9972 %{ | |
| 9973 match(Set dst (ConvD2I src)); | |
| 9974 effect(KILL cr); | |
| 9975 | |
| 9976 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 9977 "cmpl $dst, #0x80000000\n\t" | |
| 9978 "jne,s done\n\t" | |
| 9979 "subq rsp, #8\n\t" | |
| 9980 "movsd [rsp], $src\n\t" | |
| 9981 "call d2i_fixup\n\t" | |
| 9982 "popq $dst\n" | |
| 9983 "done: "%} | |
| 4759 | 9984 ins_encode %{ |
| 9985 Label done; | |
| 9986 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 9987 __ cmpl($dst$$Register, 0x80000000); | |
| 9988 __ jccb(Assembler::notEqual, done); | |
| 9989 __ subptr(rsp, 8); | |
| 9990 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 9991 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); | |
| 9992 __ pop($dst$$Register); | |
| 9993 __ bind(done); | |
| 9994 %} | |
| 0 | 9995 ins_pipe(pipe_slow); |
| 9996 %} | |
| 9997 | |
| 9998 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 9999 %{ | |
| 10000 match(Set dst (ConvD2L src)); | |
| 10001 effect(KILL cr); | |
| 10002 | |
| 10003 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 10004 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 10005 "jne,s done\n\t" | |
| 10006 "subq rsp, #8\n\t" | |
| 10007 "movsd [rsp], $src\n\t" | |
| 10008 "call d2l_fixup\n\t" | |
| 10009 "popq $dst\n" | |
| 10010 "done: "%} | |
| 4759 | 10011 ins_encode %{ |
| 10012 Label done; | |
| 10013 __ cvttsd2siq($dst$$Register, $src$$XMMRegister); | |
| 10014 __ cmp64($dst$$Register, | |
| 10015 ExternalAddress((address) StubRoutines::x86::double_sign_flip())); | |
| 10016 __ jccb(Assembler::notEqual, done); | |
| 10017 __ subptr(rsp, 8); | |
| 10018 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10019 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); | |
| 10020 __ pop($dst$$Register); | |
| 10021 __ bind(done); | |
| 10022 %} | |
| 0 | 10023 ins_pipe(pipe_slow); |
| 10024 %} | |
| 10025 | |
| 10026 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 10027 %{ | |
| 71 | 10028 predicate(!UseXmmI2F); |
| 0 | 10029 match(Set dst (ConvI2F src)); |
| 10030 | |
| 10031 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10032 ins_encode %{ |
| 10033 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 10034 %} | |
| 0 | 10035 ins_pipe(pipe_slow); // XXX |
| 10036 %} | |
| 10037 | |
| 10038 instruct convI2F_reg_mem(regF dst, memory src) | |
| 10039 %{ | |
| 10040 match(Set dst (ConvI2F (LoadI src))); | |
| 10041 | |
| 10042 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 4759 | 10043 ins_encode %{ |
| 10044 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address); | |
| 10045 %} | |
| 0 | 10046 ins_pipe(pipe_slow); // XXX |
| 10047 %} | |
| 10048 | |
| 10049 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 10050 %{ | |
| 71 | 10051 predicate(!UseXmmI2D); |
| 0 | 10052 match(Set dst (ConvI2D src)); |
| 10053 | |
| 10054 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10055 ins_encode %{ |
| 10056 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 10057 %} | |
| 0 | 10058 ins_pipe(pipe_slow); // XXX |
| 10059 %} | |
| 10060 | |
| 10061 instruct convI2D_reg_mem(regD dst, memory src) | |
| 10062 %{ | |
| 10063 match(Set dst (ConvI2D (LoadI src))); | |
| 10064 | |
| 10065 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 4759 | 10066 ins_encode %{ |
| 10067 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address); | |
| 10068 %} | |
| 0 | 10069 ins_pipe(pipe_slow); // XXX |
| 10070 %} | |
| 10071 | |
| 71 | 10072 instruct convXI2F_reg(regF dst, rRegI src) |
| 10073 %{ | |
| 10074 predicate(UseXmmI2F); | |
| 10075 match(Set dst (ConvI2F src)); | |
| 10076 | |
| 10077 format %{ "movdl $dst, $src\n\t" | |
| 10078 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 10079 ins_encode %{ | |
| 10080 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10081 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10082 %} | |
| 10083 ins_pipe(pipe_slow); // XXX | |
| 10084 %} | |
| 10085 | |
| 10086 instruct convXI2D_reg(regD dst, rRegI src) | |
| 10087 %{ | |
| 10088 predicate(UseXmmI2D); | |
| 10089 match(Set dst (ConvI2D src)); | |
| 10090 | |
| 10091 format %{ "movdl $dst, $src\n\t" | |
| 10092 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 10093 ins_encode %{ | |
| 10094 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10095 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 10096 %} | |
| 10097 ins_pipe(pipe_slow); // XXX | |
| 10098 %} | |
| 10099 | |
| 0 | 10100 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 10101 %{ | |
| 10102 match(Set dst (ConvL2F src)); | |
| 10103 | |
| 10104 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10105 ins_encode %{ |
| 10106 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register); | |
| 10107 %} | |
| 0 | 10108 ins_pipe(pipe_slow); // XXX |
| 10109 %} | |
| 10110 | |
| 10111 instruct convL2F_reg_mem(regF dst, memory src) | |
| 10112 %{ | |
| 10113 match(Set dst (ConvL2F (LoadL src))); | |
| 10114 | |
| 10115 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 4759 | 10116 ins_encode %{ |
| 10117 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address); | |
| 10118 %} | |
| 0 | 10119 ins_pipe(pipe_slow); // XXX |
| 10120 %} | |
| 10121 | |
| 10122 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 10123 %{ | |
| 10124 match(Set dst (ConvL2D src)); | |
| 10125 | |
| 10126 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10127 ins_encode %{ |
| 10128 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register); | |
| 10129 %} | |
| 0 | 10130 ins_pipe(pipe_slow); // XXX |
| 10131 %} | |
| 10132 | |
| 10133 instruct convL2D_reg_mem(regD dst, memory src) | |
| 10134 %{ | |
| 10135 match(Set dst (ConvL2D (LoadL src))); | |
| 10136 | |
| 10137 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 4759 | 10138 ins_encode %{ |
| 10139 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address); | |
| 10140 %} | |
| 0 | 10141 ins_pipe(pipe_slow); // XXX |
| 10142 %} | |
| 10143 | |
| 10144 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 10145 %{ | |
| 10146 match(Set dst (ConvI2L src)); | |
| 10147 | |
| 10148 ins_cost(125); | |
| 10149 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 10150 ins_encode %{ |
| 10151 __ movslq($dst$$Register, $src$$Register); | |
| 10152 %} | |
| 0 | 10153 ins_pipe(ialu_reg_reg); |
| 10154 %} | |
| 10155 | |
| 10156 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 10157 // %{ | |
| 10158 // match(Set dst (ConvI2L src)); | |
| 10159 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 10160 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 10161 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 10162 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 10163 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 10164 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 10165 | |
| 10166 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 10167 // ins_encode(enc_copy(dst, src)); | |
| 10168 // // opcode(0x63); // needs REX.W | |
| 10169 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 10170 // ins_pipe(ialu_reg_reg); | |
| 10171 // %} | |
| 10172 | |
| 10173 // Zero-extend convert int to long | |
| 10174 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 10175 %{ | |
| 10176 match(Set dst (AndL (ConvI2L src) mask)); | |
| 10177 | |
| 10178 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10179 ins_encode %{ |
| 10180 if ($dst$$reg != $src$$reg) { | |
| 10181 __ movl($dst$$Register, $src$$Register); | |
| 10182 } | |
| 10183 %} | |
| 0 | 10184 ins_pipe(ialu_reg_reg); |
| 10185 %} | |
| 10186 | |
| 10187 // Zero-extend convert int to long | |
| 10188 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 10189 %{ | |
| 10190 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 10191 | |
| 10192 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 4759 | 10193 ins_encode %{ |
| 10194 __ movl($dst$$Register, $src$$Address); | |
| 10195 %} | |
| 0 | 10196 ins_pipe(ialu_reg_mem); |
| 10197 %} | |
| 10198 | |
| 10199 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 10200 %{ | |
| 10201 match(Set dst (AndL src mask)); | |
| 10202 | |
| 10203 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 4759 | 10204 ins_encode %{ |
| 10205 __ movl($dst$$Register, $src$$Register); | |
| 10206 %} | |
| 0 | 10207 ins_pipe(ialu_reg_reg); |
| 10208 %} | |
| 10209 | |
| 10210 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 10211 %{ | |
| 10212 match(Set dst (ConvL2I src)); | |
| 10213 | |
| 10214 format %{ "movl $dst, $src\t# l2i" %} | |
| 4759 | 10215 ins_encode %{ |
| 10216 __ movl($dst$$Register, $src$$Register); | |
| 10217 %} | |
| 0 | 10218 ins_pipe(ialu_reg_reg); |
| 10219 %} | |
| 10220 | |
| 10221 | |
| 10222 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 10223 match(Set dst (MoveF2I src)); | |
| 10224 effect(DEF dst, USE src); | |
| 10225 | |
| 10226 ins_cost(125); | |
| 10227 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 4759 | 10228 ins_encode %{ |
| 10229 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 10230 %} | |
| 0 | 10231 ins_pipe(ialu_reg_mem); |
| 10232 %} | |
| 10233 | |
| 10234 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 10235 match(Set dst (MoveI2F src)); | |
| 10236 effect(DEF dst, USE src); | |
| 10237 | |
| 10238 ins_cost(125); | |
| 10239 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 4759 | 10240 ins_encode %{ |
| 10241 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10242 %} | |
| 0 | 10243 ins_pipe(pipe_slow); |
| 10244 %} | |
| 10245 | |
| 10246 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 10247 match(Set dst (MoveD2L src)); | |
| 10248 effect(DEF dst, USE src); | |
| 10249 | |
| 10250 ins_cost(125); | |
| 10251 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 4759 | 10252 ins_encode %{ |
| 10253 __ movq($dst$$Register, Address(rsp, $src$$disp)); | |
| 10254 %} | |
| 0 | 10255 ins_pipe(ialu_reg_mem); |
| 10256 %} | |
| 10257 | |
| 10258 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 10259 predicate(!UseXmmLoadAndClearUpper); | |
| 10260 match(Set dst (MoveL2D src)); | |
| 10261 effect(DEF dst, USE src); | |
| 10262 | |
| 10263 ins_cost(125); | |
| 10264 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10265 ins_encode %{ |
| 10266 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10267 %} | |
| 0 | 10268 ins_pipe(pipe_slow); |
| 10269 %} | |
| 10270 | |
| 10271 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 10272 predicate(UseXmmLoadAndClearUpper); | |
| 10273 match(Set dst (MoveL2D src)); | |
| 10274 effect(DEF dst, USE src); | |
| 10275 | |
| 10276 ins_cost(125); | |
| 10277 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 4759 | 10278 ins_encode %{ |
| 10279 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 10280 %} | |
| 0 | 10281 ins_pipe(pipe_slow); |
| 10282 %} | |
| 10283 | |
| 10284 | |
| 10285 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 10286 match(Set dst (MoveF2I src)); | |
| 10287 effect(DEF dst, USE src); | |
| 10288 | |
| 10289 ins_cost(95); // XXX | |
| 10290 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 4759 | 10291 ins_encode %{ |
| 10292 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10293 %} | |
| 0 | 10294 ins_pipe(pipe_slow); |
| 10295 %} | |
| 10296 | |
| 10297 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 10298 match(Set dst (MoveI2F src)); | |
| 10299 effect(DEF dst, USE src); | |
| 10300 | |
| 10301 ins_cost(100); | |
| 10302 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 4759 | 10303 ins_encode %{ |
| 10304 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 10305 %} | |
| 0 | 10306 ins_pipe( ialu_mem_reg ); |
| 10307 %} | |
| 10308 | |
| 10309 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 10310 match(Set dst (MoveD2L src)); | |
| 10311 effect(DEF dst, USE src); | |
| 10312 | |
| 10313 ins_cost(95); // XXX | |
| 10314 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10315 ins_encode %{ |
| 10316 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 10317 %} | |
| 0 | 10318 ins_pipe(pipe_slow); |
| 10319 %} | |
| 10320 | |
| 10321 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 10322 match(Set dst (MoveL2D src)); | |
| 10323 effect(DEF dst, USE src); | |
| 10324 | |
| 10325 ins_cost(100); | |
| 10326 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 4759 | 10327 ins_encode %{ |
| 10328 __ movq(Address(rsp, $dst$$disp), $src$$Register); | |
| 10329 %} | |
| 0 | 10330 ins_pipe(ialu_mem_reg); |
| 10331 %} | |
| 10332 | |
| 10333 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 10334 match(Set dst (MoveF2I src)); | |
| 10335 effect(DEF dst, USE src); | |
| 10336 ins_cost(85); | |
| 10337 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 4759 | 10338 ins_encode %{ |
| 10339 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 10340 %} | |
| 0 | 10341 ins_pipe( pipe_slow ); |
| 10342 %} | |
| 10343 | |
| 10344 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 10345 match(Set dst (MoveD2L src)); | |
| 10346 effect(DEF dst, USE src); | |
| 10347 ins_cost(85); | |
| 10348 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 4759 | 10349 ins_encode %{ |
| 10350 __ movdq($dst$$Register, $src$$XMMRegister); | |
| 10351 %} | |
| 0 | 10352 ins_pipe( pipe_slow ); |
| 10353 %} | |
| 10354 | |
| 10355 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 10356 match(Set dst (MoveI2F src)); | |
| 10357 effect(DEF dst, USE src); | |
|
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10358 ins_cost(100); |
| 0 | 10359 format %{ "movd $dst,$src\t# MoveI2F" %} |
| 4759 | 10360 ins_encode %{ |
| 10361 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 10362 %} | |
| 0 | 10363 ins_pipe( pipe_slow ); |
| 10364 %} | |
| 10365 | |
| 10366 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 10367 match(Set dst (MoveL2D src)); | |
| 10368 effect(DEF dst, USE src); | |
|
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10369 ins_cost(100); |
| 0 | 10370 format %{ "movd $dst,$src\t# MoveL2D" %} |
| 4759 | 10371 ins_encode %{ |
| 10372 __ movdq($dst$$XMMRegister, $src$$Register); | |
| 10373 %} | |
| 0 | 10374 ins_pipe( pipe_slow ); |
| 10375 %} | |
| 10376 | |
| 10377 | |
| 10378 // ======================================================================= | |
| 10379 // fast clearing of an array | |
| 10380 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 10381 rFlagsReg cr) | |
| 10382 %{ | |
|
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10383 predicate(!UseFastStosb); |
| 0 | 10384 match(Set dummy (ClearArray cnt base)); |
| 10385 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 10386 | |
|
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10387 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
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10388 "rep stosq\t# Store rax to *rdi++ while rcx--" %} |
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10389 ins_encode %{ |
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10390 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
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10391 %} |
| 0 | 10392 ins_pipe(pipe_slow); |
| 10393 %} | |
| 10394 | |
|
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10395 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, |
|
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10396 rFlagsReg cr) |
|
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10397 %{ |
|
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10398 predicate(UseFastStosb); |
|
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10399 match(Set dummy (ClearArray cnt base)); |
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10400 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
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10401 format %{ "xorq rax, rax\t# ClearArray:\n\t" |
|
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10402 "shlq rcx,3\t# Convert doublewords to bytes\n\t" |
|
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10403 "rep stosb\t# Store rax to *rdi++ while rcx--" %} |
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10404 ins_encode %{ |
|
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10405 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
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10406 %} |
|
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10407 ins_pipe( pipe_slow ); |
|
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10408 %} |
|
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10409 |
| 2262 | 10410 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2, |
| 10411 rax_RegI result, regD tmp1, rFlagsReg cr) | |
|
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10412 %{ |
|
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10413 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 10414 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 10415 | |
| 10416 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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10417 ins_encode %{ |
|
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10418 __ string_compare($str1$$Register, $str2$$Register, |
|
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10419 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 10420 $tmp1$$XMMRegister); |
|
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10421 %} |
| 681 | 10422 ins_pipe( pipe_slow ); |
| 10423 %} | |
| 10424 | |
|
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10425 // fast search of substring with known size. |
|
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10426 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2, |
|
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10427 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr) |
|
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10428 %{ |
|
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10429 predicate(UseSSE42Intrinsics); |
|
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10430 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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10431 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
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10432 |
|
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10433 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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10434 ins_encode %{ |
|
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10435 int icnt2 = (int)$int_cnt2$$constant; |
|
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10436 if (icnt2 >= 8) { |
|
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10437 // IndexOf for constant substrings with size >= 8 elements |
|
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10438 // which don't need to be loaded through stack. |
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changeset
|
10439 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10440 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10441 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10442 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10443 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10444 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10445 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10446 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10447 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10448 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10449 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10450 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10451 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10452 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10453 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10454 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10455 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr) |
| 681 | 10456 %{ |
| 10457 predicate(UseSSE42Intrinsics); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10458 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10459 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10460 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10461 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10462 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10463 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10464 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10465 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
10466 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10467 %} |
| 681 | 10468 ins_pipe( pipe_slow ); |
| 10469 %} | |
| 10470 | |
| 10471 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10472 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10473 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10474 %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10475 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10476 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10477 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10478 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10479 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10480 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10481 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10482 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10483 %} |
| 0 | 10484 ins_pipe( pipe_slow ); |
| 10485 %} | |
| 10486 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10487 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10488 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10489 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 10490 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10491 match(Set result (AryEq ary1 ary2)); |
| 681 | 10492 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10493 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10494 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10495 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10496 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10497 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10498 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10499 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
10500 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10501 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10502 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
10503 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10504 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10505 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10506 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10507 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10508 match(Set result (EncodeISOArray src (Binary dst len))); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10509 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10510 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10511 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10512 ins_encode %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10513 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10514 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10515 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10516 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10517 ins_pipe( pipe_slow ); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10518 %} |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
10519 |
|
17726
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10520 //----------Overflow Math Instructions----------------------------------------- |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10521 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10522 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10523 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10524 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10525 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10526 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10527 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10528 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10529 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10530 __ addl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10531 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10532 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10533 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10534 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10535 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10536 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10537 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10538 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10539 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10540 format %{ "addl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10541 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10542 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10543 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10544 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10545 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10546 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10547 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10548 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10549 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10550 match(Set cr (OverflowAddL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10551 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10552 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10553 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10554 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10555 __ addq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10556 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10557 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10558 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10559 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10560 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10561 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10562 match(Set cr (OverflowAddL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10563 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10564 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10565 format %{ "addq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10566 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10567 __ addq($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10568 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10569 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10570 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10571 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10572 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10573 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10574 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10575 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10576 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10577 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10578 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10579 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10580 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10581 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10582 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10583 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10584 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10585 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10586 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10587 format %{ "cmpl $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10588 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10589 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10590 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10591 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10592 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10593 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10594 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10595 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10596 match(Set cr (OverflowSubL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10597 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10598 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10599 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10600 __ cmpq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10601 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10602 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10603 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10604 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10605 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10606 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10607 match(Set cr (OverflowSubL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10608 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10609 format %{ "cmpq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10610 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10611 __ cmpq($op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10612 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10613 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10614 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10615 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10616 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10617 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10618 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10619 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10620 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10621 format %{ "negl $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10622 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10623 __ negl($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10624 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10625 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10626 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10627 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10628 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10629 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10630 match(Set cr (OverflowSubL zero op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10631 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10632 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10633 format %{ "negq $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10634 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10635 __ negq($op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10636 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10637 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10638 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10639 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10640 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10641 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10642 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10643 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10644 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10645 format %{ "imull $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10646 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10647 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10648 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10649 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10650 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10651 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10652 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10653 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10654 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10655 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10656 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10657 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10658 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10659 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10660 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10661 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10662 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10663 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10664 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10665 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10666 match(Set cr (OverflowMulL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10667 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10668 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10669 format %{ "imulq $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10670 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10671 __ imulq($op1$$Register, $op2$$Register); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10672 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10673 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10674 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10675 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10676 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp) |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10677 %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10678 match(Set cr (OverflowMulL op1 op2)); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10679 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10680 |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10681 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10682 ins_encode %{ |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10683 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10684 %} |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
changeset
|
10685 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
8027754: Enable loop optimizations for loops with MathExact inside
rbackman
parents:
17714
diff
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|
10686 %} |
|
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|
10687 |
|
7637
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|
10688 |
| 0 | 10689 //----------Control Flow Instructions------------------------------------------ |
| 10690 // Signed compare Instructions | |
| 10691 | |
| 10692 // XXX more variants!! | |
| 10693 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 10694 %{ | |
| 10695 match(Set cr (CmpI op1 op2)); | |
| 10696 effect(DEF cr, USE op1, USE op2); | |
| 10697 | |
| 10698 format %{ "cmpl $op1, $op2" %} | |
| 10699 opcode(0x3B); /* Opcode 3B /r */ | |
| 10700 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10701 ins_pipe(ialu_cr_reg_reg); | |
| 10702 %} | |
| 10703 | |
| 10704 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 10705 %{ | |
| 10706 match(Set cr (CmpI op1 op2)); | |
| 10707 | |
| 10708 format %{ "cmpl $op1, $op2" %} | |
| 10709 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 10710 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10711 ins_pipe(ialu_cr_reg_imm); | |
| 10712 %} | |
| 10713 | |
| 10714 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 10715 %{ | |
| 10716 match(Set cr (CmpI op1 (LoadI op2))); | |
| 10717 | |
| 10718 ins_cost(500); // XXX | |
| 10719 format %{ "cmpl $op1, $op2" %} | |
| 10720 opcode(0x3B); /* Opcode 3B /r */ | |
| 10721 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10722 ins_pipe(ialu_cr_reg_mem); | |
| 10723 %} | |
| 10724 | |
| 10725 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 10726 %{ | |
| 10727 match(Set cr (CmpI src zero)); | |
| 10728 | |
| 10729 format %{ "testl $src, $src" %} | |
| 10730 opcode(0x85); | |
| 10731 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10732 ins_pipe(ialu_cr_reg_imm); | |
| 10733 %} | |
| 10734 | |
| 10735 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 10736 %{ | |
| 10737 match(Set cr (CmpI (AndI src con) zero)); | |
| 10738 | |
| 10739 format %{ "testl $src, $con" %} | |
| 10740 opcode(0xF7, 0x00); | |
| 10741 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 10742 ins_pipe(ialu_cr_reg_imm); | |
| 10743 %} | |
| 10744 | |
| 10745 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 10746 %{ | |
| 10747 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 10748 | |
| 10749 format %{ "testl $src, $mem" %} | |
| 10750 opcode(0x85); | |
| 10751 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 10752 ins_pipe(ialu_cr_reg_mem); | |
| 10753 %} | |
| 10754 | |
| 10755 // Unsigned compare Instructions; really, same as signed except they | |
| 10756 // produce an rFlagsRegU instead of rFlagsReg. | |
| 10757 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 10758 %{ | |
| 10759 match(Set cr (CmpU op1 op2)); | |
| 10760 | |
| 10761 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10762 opcode(0x3B); /* Opcode 3B /r */ | |
| 10763 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10764 ins_pipe(ialu_cr_reg_reg); | |
| 10765 %} | |
| 10766 | |
| 10767 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 10768 %{ | |
| 10769 match(Set cr (CmpU op1 op2)); | |
| 10770 | |
| 10771 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10772 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 10773 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 10774 ins_pipe(ialu_cr_reg_imm); | |
| 10775 %} | |
| 10776 | |
| 10777 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 10778 %{ | |
| 10779 match(Set cr (CmpU op1 (LoadI op2))); | |
| 10780 | |
| 10781 ins_cost(500); // XXX | |
| 10782 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 10783 opcode(0x3B); /* Opcode 3B /r */ | |
| 10784 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10785 ins_pipe(ialu_cr_reg_mem); | |
| 10786 %} | |
| 10787 | |
| 10788 // // // Cisc-spilled version of cmpU_rReg | |
| 10789 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 10790 // //%{ | |
| 10791 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 10792 // // | |
| 10793 // // format %{ "CMPu $op1,$op2" %} | |
| 10794 // // ins_cost(500); | |
| 10795 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10796 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10797 // //%} | |
| 10798 | |
| 10799 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 10800 %{ | |
| 10801 match(Set cr (CmpU src zero)); | |
| 10802 | |
| 10803 format %{ "testl $src, $src\t# unsigned" %} | |
| 10804 opcode(0x85); | |
| 10805 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 10806 ins_pipe(ialu_cr_reg_imm); | |
| 10807 %} | |
| 10808 | |
| 10809 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 10810 %{ | |
| 10811 match(Set cr (CmpP op1 op2)); | |
| 10812 | |
| 10813 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10814 opcode(0x3B); /* Opcode 3B /r */ | |
| 10815 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 10816 ins_pipe(ialu_cr_reg_reg); | |
| 10817 %} | |
| 10818 | |
| 10819 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10820 %{ | |
| 10821 match(Set cr (CmpP op1 (LoadP op2))); | |
| 10822 | |
| 10823 ins_cost(500); // XXX | |
| 10824 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 10825 opcode(0x3B); /* Opcode 3B /r */ | |
| 10826 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10827 ins_pipe(ialu_cr_reg_mem); | |
| 10828 %} | |
| 10829 | |
| 10830 // // // Cisc-spilled version of cmpP_rReg | |
| 10831 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 10832 // //%{ | |
| 10833 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 10834 // // | |
| 10835 // // format %{ "CMPu $op1,$op2" %} | |
| 10836 // // ins_cost(500); | |
| 10837 // // opcode(0x39); /* Opcode 39 /r */ | |
| 10838 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 10839 // //%} | |
| 10840 | |
| 10841 // XXX this is generalized by compP_rReg_mem??? | |
| 10842 // Compare raw pointer (used in out-of-heap check). | |
| 10843 // Only works because non-oop pointers must be raw pointers | |
| 10844 // and raw pointers have no anti-dependencies. | |
| 10845 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 10846 %{ | |
|
6725
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6964458: Reimplement class meta-data storage to use native memory
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10847 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none); |
| 0 | 10848 match(Set cr (CmpP op1 (LoadP op2))); |
| 10849 | |
| 10850 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 10851 opcode(0x3B); /* Opcode 3B /r */ | |
| 10852 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 10853 ins_pipe(ialu_cr_reg_mem); | |
| 10854 %} | |
| 10855 | |
| 10856 // This will generate a signed flags result. This should be OK since | |
| 10857 // any compare to a zero should be eq/neq. | |
| 10858 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 10859 %{ | |
| 10860 match(Set cr (CmpP src zero)); | |
| 10861 | |
| 10862 format %{ "testq $src, $src\t# ptr" %} | |
| 10863 opcode(0x85); | |
| 10864 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 10865 ins_pipe(ialu_cr_reg_imm); | |
| 10866 %} | |
| 10867 | |
| 10868 // This will generate a signed flags result. This should be OK since | |
| 10869 // any compare to a zero should be eq/neq. | |
|
642
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10870 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
|
660978a2a31a
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10871 %{ |
|
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|
10872 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 10873 match(Set cr (CmpP (LoadP op) zero)); |
| 10874 | |
| 10875 ins_cost(500); // XXX | |
| 10876 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 10877 opcode(0xF7); /* Opcode F7 /0 */ | |
| 10878 ins_encode(REX_mem_wide(op), | |
| 10879 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 10880 ins_pipe(ialu_cr_reg_imm); | |
| 10881 %} | |
| 10882 | |
|
642
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10883 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
|
660978a2a31a
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10884 %{ |
|
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|
10885 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL)); |
|
642
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10886 match(Set cr (CmpP (LoadP mem) zero)); |
|
660978a2a31a
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|
10887 |
|
660978a2a31a
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|
10888 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
|
660978a2a31a
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|
10889 ins_encode %{ |
|
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|
10890 __ cmpq(r12, $mem$$Address); |
|
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|
10891 %} |
|
660978a2a31a
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|
10892 ins_pipe(ialu_cr_reg_mem); |
|
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10893 %} |
|
164
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|
10894 |
|
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|
10895 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
|
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10896 %{ |
|
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10897 match(Set cr (CmpN op1 op2)); |
|
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|
10898 |
|
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|
10899 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10900 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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10901 ins_pipe(ialu_cr_reg_reg); |
|
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10902 %} |
|
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|
10903 |
|
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|
10904 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
|
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10905 %{ |
|
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10906 match(Set cr (CmpN src (LoadN mem))); |
|
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|
10907 |
|
642
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|
10908 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
|
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10909 ins_encode %{ |
|
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|
10910 __ cmpl($src$$Register, $mem$$Address); |
|
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|
10911 %} |
|
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10912 ins_pipe(ialu_cr_reg_mem); |
|
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|
10913 %} |
|
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|
10914 |
|
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10915 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
|
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10916 match(Set cr (CmpN op1 op2)); |
|
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|
10917 |
|
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10918 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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10919 ins_encode %{ |
|
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10920 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
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10921 %} |
|
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10922 ins_pipe(ialu_cr_reg_imm); |
|
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|
10923 %} |
|
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|
10924 |
|
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10925 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
|
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10926 %{ |
|
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10927 match(Set cr (CmpN src (LoadN mem))); |
|
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|
10928 |
|
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|
10929 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
|
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10930 ins_encode %{ |
|
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10931 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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10932 %} |
|
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10933 ins_pipe(ialu_cr_reg_mem); |
|
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10934 %} |
|
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|
10935 |
|
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|
10936 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{ |
|
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|
10937 match(Set cr (CmpN op1 op2)); |
|
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|
10938 |
|
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|
10939 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %} |
|
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|
10940 ins_encode %{ |
|
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|
10941 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant); |
|
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|
10942 %} |
|
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|
10943 ins_pipe(ialu_cr_reg_imm); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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diff
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|
10944 %} |
|
8e47bac5643a
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6795
diff
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|
10945 |
|
8e47bac5643a
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diff
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|
10946 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src) |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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6795
diff
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|
10947 %{ |
|
8e47bac5643a
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6795
diff
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|
10948 match(Set cr (CmpN src (LoadNKlass mem))); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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parents:
6795
diff
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|
10949 |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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diff
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|
10950 format %{ "cmpl $mem, $src\t# compressed klass ptr" %} |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
changeset
|
10951 ins_encode %{ |
|
8e47bac5643a
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6795
diff
changeset
|
10952 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
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|
10953 %} |
|
8e47bac5643a
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6795
diff
changeset
|
10954 ins_pipe(ialu_cr_reg_mem); |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
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parents:
6795
diff
changeset
|
10955 %} |
|
8e47bac5643a
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diff
changeset
|
10956 |
|
113
ba764ed4b6f2
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coleenp
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71
diff
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|
10957 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
|
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diff
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|
10958 match(Set cr (CmpN src zero)); |
|
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diff
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|
10959 |
|
164
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|
10960 format %{ "testl $src, $src\t# compressed ptr" %} |
|
113
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|
10961 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
|
ba764ed4b6f2
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diff
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|
10962 ins_pipe(ialu_cr_reg_imm); |
|
ba764ed4b6f2
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71
diff
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|
10963 %} |
|
ba764ed4b6f2
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diff
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|
10964 |
|
642
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kvn
parents:
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|
10965 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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kvn
parents:
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diff
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|
10966 %{ |
|
660978a2a31a
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diff
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|
10967 predicate(Universe::narrow_oop_base() != NULL); |
|
164
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|
10968 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
10969 |
|
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|
10970 ins_cost(500); // XXX |
|
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|
10971 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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|
10972 ins_encode %{ |
|
642
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diff
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|
10973 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
10974 %} |
|
660978a2a31a
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624
diff
changeset
|
10975 ins_pipe(ialu_cr_reg_mem); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10976 %} |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
10977 |
|
660978a2a31a
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kvn
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624
diff
changeset
|
10978 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
660978a2a31a
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kvn
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|
10979 %{ |
|
6848
8e47bac5643a
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diff
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|
10980 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL)); |
|
642
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|
10981 match(Set cr (CmpN (LoadN mem) zero)); |
|
660978a2a31a
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|
10982 |
|
660978a2a31a
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diff
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|
10983 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
660978a2a31a
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|
10984 ins_encode %{ |
|
660978a2a31a
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diff
changeset
|
10985 __ cmpl(r12, $mem$$Address); |
|
164
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|
10986 %} |
|
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|
10987 ins_pipe(ialu_cr_reg_mem); |
|
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|
10988 %} |
|
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|
10989 |
| 0 | 10990 // Yanked all unsigned pointer compare operations. |
| 10991 // Pointer compares are done with CmpP which is already unsigned. | |
| 10992 | |
| 10993 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 10994 %{ | |
| 10995 match(Set cr (CmpL op1 op2)); | |
| 10996 | |
| 10997 format %{ "cmpq $op1, $op2" %} | |
| 10998 opcode(0x3B); /* Opcode 3B /r */ | |
| 10999 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11000 ins_pipe(ialu_cr_reg_reg); | |
| 11001 %} | |
| 11002 | |
| 11003 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 11004 %{ | |
| 11005 match(Set cr (CmpL op1 op2)); | |
| 11006 | |
| 11007 format %{ "cmpq $op1, $op2" %} | |
| 11008 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11009 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11010 ins_pipe(ialu_cr_reg_imm); | |
| 11011 %} | |
| 11012 | |
| 11013 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 11014 %{ | |
| 11015 match(Set cr (CmpL op1 (LoadL op2))); | |
| 11016 | |
| 11017 format %{ "cmpq $op1, $op2" %} | |
| 11018 opcode(0x3B); /* Opcode 3B /r */ | |
| 11019 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11020 ins_pipe(ialu_cr_reg_mem); | |
| 11021 %} | |
| 11022 | |
| 11023 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 11024 %{ | |
| 11025 match(Set cr (CmpL src zero)); | |
| 11026 | |
| 11027 format %{ "testq $src, $src" %} | |
| 11028 opcode(0x85); | |
| 11029 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11030 ins_pipe(ialu_cr_reg_imm); | |
| 11031 %} | |
| 11032 | |
| 11033 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 11034 %{ | |
| 11035 match(Set cr (CmpL (AndL src con) zero)); | |
| 11036 | |
| 11037 format %{ "testq $src, $con\t# long" %} | |
| 11038 opcode(0xF7, 0x00); | |
| 11039 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 11040 ins_pipe(ialu_cr_reg_imm); | |
| 11041 %} | |
| 11042 | |
| 11043 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 11044 %{ | |
| 11045 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 11046 | |
| 11047 format %{ "testq $src, $mem" %} | |
| 11048 opcode(0x85); | |
| 11049 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 11050 ins_pipe(ialu_cr_reg_mem); | |
| 11051 %} | |
| 11052 | |
| 11053 // Manifest a CmpL result in an integer register. Very painful. | |
| 11054 // This is the test to avoid. | |
| 11055 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 11056 %{ | |
| 11057 match(Set dst (CmpL3 src1 src2)); | |
| 11058 effect(KILL flags); | |
| 11059 | |
| 11060 ins_cost(275); // XXX | |
| 11061 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 11062 "movl $dst, -1\n\t" | |
| 11063 "jl,s done\n\t" | |
| 11064 "setne $dst\n\t" | |
| 11065 "movzbl $dst, $dst\n\t" | |
| 11066 "done:" %} | |
| 11067 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 11068 ins_pipe(pipe_slow); | |
| 11069 %} | |
| 11070 | |
| 24206 | 11071 // Unsigned long compare Instructions; really, same as signed long except they |
| 11072 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11073 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2) | |
| 11074 %{ | |
| 11075 match(Set cr (CmpUL op1 op2)); | |
| 11076 | |
| 11077 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11078 opcode(0x3B); /* Opcode 3B /r */ | |
| 11079 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11080 ins_pipe(ialu_cr_reg_reg); | |
| 11081 %} | |
| 11082 | |
| 11083 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2) | |
| 11084 %{ | |
| 11085 match(Set cr (CmpUL op1 op2)); | |
| 11086 | |
| 11087 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11088 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11089 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11090 ins_pipe(ialu_cr_reg_imm); | |
| 11091 %} | |
| 11092 | |
| 11093 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2) | |
| 11094 %{ | |
| 11095 match(Set cr (CmpUL op1 (LoadL op2))); | |
| 11096 | |
| 11097 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11098 opcode(0x3B); /* Opcode 3B /r */ | |
| 11099 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11100 ins_pipe(ialu_cr_reg_mem); | |
| 11101 %} | |
| 11102 | |
| 11103 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero) | |
| 11104 %{ | |
| 11105 match(Set cr (CmpUL src zero)); | |
| 11106 | |
| 11107 format %{ "testq $src, $src\t# unsigned" %} | |
| 11108 opcode(0x85); | |
| 11109 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11110 ins_pipe(ialu_cr_reg_imm); | |
| 11111 %} | |
| 11112 | |
| 0 | 11113 //----------Max and Min-------------------------------------------------------- |
| 11114 // Min Instructions | |
| 11115 | |
| 11116 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11117 %{ | |
| 11118 effect(USE_DEF dst, USE src, USE cr); | |
| 11119 | |
| 11120 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 11121 opcode(0x0F, 0x4F); | |
| 11122 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11123 ins_pipe(pipe_cmov_reg); | |
| 11124 %} | |
| 11125 | |
| 11126 | |
| 11127 instruct minI_rReg(rRegI dst, rRegI src) | |
| 11128 %{ | |
| 11129 match(Set dst (MinI dst src)); | |
| 11130 | |
| 11131 ins_cost(200); | |
| 11132 expand %{ | |
| 11133 rFlagsReg cr; | |
| 11134 compI_rReg(cr, dst, src); | |
| 11135 cmovI_reg_g(dst, src, cr); | |
| 11136 %} | |
| 11137 %} | |
| 11138 | |
| 11139 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 11140 %{ | |
| 11141 effect(USE_DEF dst, USE src, USE cr); | |
| 11142 | |
| 11143 format %{ "cmovllt $dst, $src\t# max" %} | |
| 11144 opcode(0x0F, 0x4C); | |
| 11145 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 11146 ins_pipe(pipe_cmov_reg); | |
| 11147 %} | |
| 11148 | |
| 11149 | |
| 11150 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 11151 %{ | |
| 11152 match(Set dst (MaxI dst src)); | |
| 11153 | |
| 11154 ins_cost(200); | |
| 11155 expand %{ | |
| 11156 rFlagsReg cr; | |
| 11157 compI_rReg(cr, dst, src); | |
| 11158 cmovI_reg_l(dst, src, cr); | |
| 11159 %} | |
| 11160 %} | |
| 11161 | |
| 11162 // ============================================================================ | |
| 11163 // Branch Instructions | |
| 11164 | |
| 11165 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11166 instruct jmpDir(label labl) | |
| 11167 %{ | |
| 11168 match(Goto); | |
| 11169 effect(USE labl); | |
| 11170 | |
| 11171 ins_cost(300); | |
| 11172 format %{ "jmp $labl" %} | |
| 11173 size(5); | |
| 3851 | 11174 ins_encode %{ |
| 11175 Label* L = $labl$$label; | |
| 11176 __ jmp(*L, false); // Always long jump | |
| 11177 %} | |
| 0 | 11178 ins_pipe(pipe_jmp); |
| 11179 %} | |
| 11180 | |
| 11181 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11182 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 11183 %{ | |
| 11184 match(If cop cr); | |
| 11185 effect(USE labl); | |
| 11186 | |
| 11187 ins_cost(300); | |
| 11188 format %{ "j$cop $labl" %} | |
| 11189 size(6); | |
| 3851 | 11190 ins_encode %{ |
| 11191 Label* L = $labl$$label; | |
| 11192 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11193 %} | |
| 0 | 11194 ins_pipe(pipe_jcc); |
| 11195 %} | |
| 11196 | |
| 11197 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11198 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 11199 %{ | |
| 11200 match(CountedLoopEnd cop cr); | |
| 11201 effect(USE labl); | |
| 11202 | |
| 11203 ins_cost(300); | |
| 11204 format %{ "j$cop $labl\t# loop end" %} | |
| 11205 size(6); | |
| 3851 | 11206 ins_encode %{ |
| 11207 Label* L = $labl$$label; | |
| 11208 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11209 %} | |
| 0 | 11210 ins_pipe(pipe_jcc); |
| 11211 %} | |
| 11212 | |
| 11213 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
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|
11214 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11215 match(CountedLoopEnd cop cmp); |
| 11216 effect(USE labl); | |
| 11217 | |
| 11218 ins_cost(300); | |
| 11219 format %{ "j$cop,u $labl\t# loop end" %} | |
| 11220 size(6); | |
| 3851 | 11221 ins_encode %{ |
| 11222 Label* L = $labl$$label; | |
| 11223 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11224 %} | |
| 0 | 11225 ins_pipe(pipe_jcc); |
| 11226 %} | |
| 11227 | |
|
415
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diff
changeset
|
11228 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11229 match(CountedLoopEnd cop cmp); |
|
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diff
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|
11230 effect(USE labl); |
|
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diff
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|
11231 |
|
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diff
changeset
|
11232 ins_cost(200); |
|
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diff
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|
11233 format %{ "j$cop,u $labl\t# loop end" %} |
|
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diff
changeset
|
11234 size(6); |
| 3851 | 11235 ins_encode %{ |
| 11236 Label* L = $labl$$label; | |
| 11237 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11238 %} | |
|
415
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diff
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|
11239 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
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diff
changeset
|
11240 %} |
|
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diff
changeset
|
11241 |
| 0 | 11242 // Jump Direct Conditional - using unsigned comparison |
|
415
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diff
changeset
|
11243 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 11244 match(If cop cmp); |
| 11245 effect(USE labl); | |
| 11246 | |
| 11247 ins_cost(300); | |
|
415
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diff
changeset
|
11248 format %{ "j$cop,u $labl" %} |
|
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diff
changeset
|
11249 size(6); |
| 3851 | 11250 ins_encode %{ |
| 11251 Label* L = $labl$$label; | |
| 11252 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11253 %} | |
|
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11254 ins_pipe(pipe_jcc); |
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|
11255 %} |
|
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|
11256 |
|
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|
11257 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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11258 match(If cop cmp); |
|
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|
11259 effect(USE labl); |
|
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|
11260 |
|
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|
11261 ins_cost(200); |
|
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|
11262 format %{ "j$cop,u $labl" %} |
| 0 | 11263 size(6); |
| 3851 | 11264 ins_encode %{ |
| 11265 Label* L = $labl$$label; | |
| 11266 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11267 %} | |
| 0 | 11268 ins_pipe(pipe_jcc); |
| 11269 %} | |
| 11270 | |
|
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11271 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11272 match(If cop cmp); |
|
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|
11273 effect(USE labl); |
|
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|
11274 |
|
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|
11275 ins_cost(200); |
|
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|
11276 format %{ $$template |
|
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|
11277 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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11278 $$emit$$"jp,u $labl\n\t" |
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11279 $$emit$$"j$cop,u $labl" |
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|
11280 } else { |
|
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|
11281 $$emit$$"jp,u done\n\t" |
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11282 $$emit$$"j$cop,u $labl\n\t" |
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11283 $$emit$$"done:" |
|
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|
11284 } |
|
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|
11285 %} |
|
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|
11286 ins_encode %{ |
|
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|
11287 Label* l = $labl$$label; |
|
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|
11288 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11289 __ jcc(Assembler::parity, *l, false); |
| 11290 __ jcc(Assembler::notEqual, *l, false); | |
|
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|
11291 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11292 Label done; |
| 11293 __ jccb(Assembler::parity, done); | |
| 11294 __ jcc(Assembler::equal, *l, false); | |
| 11295 __ bind(done); | |
|
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|
11296 } else { |
|
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|
11297 ShouldNotReachHere(); |
|
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|
11298 } |
|
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|
11299 %} |
|
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|
11300 ins_pipe(pipe_jcc); |
|
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|
11301 %} |
|
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|
11302 |
| 0 | 11303 // ============================================================================ |
| 11304 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 11305 // superklass array for an instance of the superklass. Set a hidden | |
| 11306 // internal cache on a hit (cache is checked with exposed code in | |
| 11307 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 11308 // encoding ALSO sets flags. | |
| 11309 | |
| 11310 instruct partialSubtypeCheck(rdi_RegP result, | |
| 11311 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11312 rFlagsReg cr) | |
| 11313 %{ | |
| 11314 match(Set result (PartialSubtypeCheck sub super)); | |
| 11315 effect(KILL rcx, KILL cr); | |
| 11316 | |
| 11317 ins_cost(1100); // slightly larger than the next version | |
|
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|
11318 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
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11319 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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11320 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11321 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" |
| 11322 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
|
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|
11323 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11324 "xorq $result, $result\t\t Hit: rdi zero\n\t" |
| 11325 "miss:\t" %} | |
| 11326 | |
| 11327 opcode(0x1); // Force a XOR of RDI | |
| 11328 ins_encode(enc_PartialSubtypeCheck()); | |
| 11329 ins_pipe(pipe_slow); | |
| 11330 %} | |
| 11331 | |
| 11332 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 11333 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 11334 immP0 zero, | |
| 11335 rdi_RegP result) | |
| 11336 %{ | |
| 11337 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 11338 effect(KILL rcx, KILL result); | |
| 11339 | |
| 11340 ins_cost(1000); | |
|
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|
11341 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t" |
|
6725
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|
11342 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t" |
|
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11343 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 11344 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" |
| 11345 "jne,s miss\t\t# Missed: flags nz\n\t" | |
|
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|
11346 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t" |
| 0 | 11347 "miss:\t" %} |
| 11348 | |
| 11349 opcode(0x0); // No need to XOR RDI | |
| 11350 ins_encode(enc_PartialSubtypeCheck()); | |
| 11351 ins_pipe(pipe_slow); | |
| 11352 %} | |
| 11353 | |
| 11354 // ============================================================================ | |
| 11355 // Branch Instructions -- short offset versions | |
| 11356 // | |
| 11357 // These instructions are used to replace jumps of a long offset (the default | |
| 11358 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 11359 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 11360 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 11361 // method in the MachNode which can be used to do in-place replacement of the | |
| 11362 // long variant with the shorter variant. The compiler will determine if a | |
| 11363 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 11364 // specific code section of the file. | |
| 11365 | |
| 11366 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
11367 instruct jmpDir_short(label labl) %{ |
| 0 | 11368 match(Goto); |
| 11369 effect(USE labl); | |
| 11370 | |
| 11371 ins_cost(300); | |
| 11372 format %{ "jmp,s $labl" %} | |
| 11373 size(2); | |
| 3851 | 11374 ins_encode %{ |
| 11375 Label* L = $labl$$label; | |
| 11376 __ jmpb(*L); | |
| 11377 %} | |
| 0 | 11378 ins_pipe(pipe_jmp); |
| 11379 ins_short_branch(1); | |
| 11380 %} | |
| 11381 | |
| 11382 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11383 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11384 match(If cop cr); |
| 11385 effect(USE labl); | |
| 11386 | |
| 11387 ins_cost(300); | |
| 11388 format %{ "j$cop,s $labl" %} | |
| 11389 size(2); | |
| 3851 | 11390 ins_encode %{ |
| 11391 Label* L = $labl$$label; | |
| 11392 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11393 %} | |
| 0 | 11394 ins_pipe(pipe_jcc); |
| 11395 ins_short_branch(1); | |
| 11396 %} | |
| 11397 | |
| 11398 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11399 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 11400 match(CountedLoopEnd cop cr); |
| 11401 effect(USE labl); | |
| 11402 | |
| 11403 ins_cost(300); | |
|
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|
11404 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 11405 size(2); |
| 3851 | 11406 ins_encode %{ |
| 11407 Label* L = $labl$$label; | |
| 11408 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11409 %} | |
| 0 | 11410 ins_pipe(pipe_jcc); |
| 11411 ins_short_branch(1); | |
| 11412 %} | |
| 11413 | |
| 11414 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
11415 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11416 match(CountedLoopEnd cop cmp); |
|
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|
11417 effect(USE labl); |
|
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|
11418 |
|
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|
11419 ins_cost(300); |
|
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|
11420 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11421 size(2); |
| 3851 | 11422 ins_encode %{ |
| 11423 Label* L = $labl$$label; | |
| 11424 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11425 %} | |
|
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|
11426 ins_pipe(pipe_jcc); |
|
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|
11427 ins_short_branch(1); |
|
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|
11428 %} |
|
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|
11429 |
|
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|
11430 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11431 match(CountedLoopEnd cop cmp); |
| 11432 effect(USE labl); | |
| 11433 | |
| 11434 ins_cost(300); | |
|
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|
11435 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
11436 size(2); |
| 3851 | 11437 ins_encode %{ |
| 11438 Label* L = $labl$$label; | |
| 11439 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11440 %} | |
|
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|
11441 ins_pipe(pipe_jcc); |
|
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|
11442 ins_short_branch(1); |
|
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|
11443 %} |
|
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|
11444 |
|
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|
11445 // Jump Direct Conditional - using unsigned comparison |
|
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|
11446 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
11447 match(If cop cmp); |
|
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|
11448 effect(USE labl); |
|
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|
11449 |
|
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|
11450 ins_cost(300); |
| 0 | 11451 format %{ "j$cop,us $labl" %} |
| 11452 size(2); | |
| 3851 | 11453 ins_encode %{ |
| 11454 Label* L = $labl$$label; | |
| 11455 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11456 %} | |
| 0 | 11457 ins_pipe(pipe_jcc); |
| 11458 ins_short_branch(1); | |
| 11459 %} | |
| 11460 | |
|
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|
11461 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 11462 match(If cop cmp); |
| 11463 effect(USE labl); | |
| 11464 | |
| 11465 ins_cost(300); | |
| 11466 format %{ "j$cop,us $labl" %} | |
| 11467 size(2); | |
| 3851 | 11468 ins_encode %{ |
| 11469 Label* L = $labl$$label; | |
| 11470 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 11471 %} | |
| 0 | 11472 ins_pipe(pipe_jcc); |
| 11473 ins_short_branch(1); | |
| 11474 %} | |
| 11475 | |
|
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|
11476 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
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|
11477 match(If cop cmp); |
|
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|
11478 effect(USE labl); |
|
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|
11479 |
|
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|
11480 ins_cost(300); |
|
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|
11481 format %{ $$template |
|
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|
11482 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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11483 $$emit$$"jp,u,s $labl\n\t" |
|
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|
11484 $$emit$$"j$cop,u,s $labl" |
|
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|
11485 } else { |
|
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|
11486 $$emit$$"jp,u,s done\n\t" |
|
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|
11487 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
11488 $$emit$$"done:" |
|
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|
11489 } |
|
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|
11490 %} |
|
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|
11491 size(4); |
|
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|
11492 ins_encode %{ |
|
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diff
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|
11493 Label* l = $labl$$label; |
|
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|
11494 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 11495 __ jccb(Assembler::parity, *l); |
| 11496 __ jccb(Assembler::notEqual, *l); | |
|
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|
11497 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 11498 Label done; |
| 11499 __ jccb(Assembler::parity, done); | |
| 11500 __ jccb(Assembler::equal, *l); | |
| 11501 __ bind(done); | |
|
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|
11502 } else { |
| 3851 | 11503 ShouldNotReachHere(); |
| 11504 } | |
|
415
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|
11505 %} |
|
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|
11506 ins_pipe(pipe_jcc); |
|
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|
11507 ins_short_branch(1); |
|
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|
11508 %} |
|
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|
11509 |
| 0 | 11510 // ============================================================================ |
| 11511 // inlined locking and unlocking | |
| 11512 | |
| 17780 | 11513 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{ |
| 11514 predicate(Compile::current()->use_rtm()); | |
| 11515 match(Set cr (FastLock object box)); | |
| 11516 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); | |
| 11517 ins_cost(300); | |
| 11518 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} | |
| 11519 ins_encode %{ | |
| 11520 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, | |
| 11521 $scr$$Register, $cx1$$Register, $cx2$$Register, | |
| 11522 _counters, _rtm_counters, _stack_rtm_counters, | |
| 11523 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), | |
| 11524 true, ra_->C->profile_rtm()); | |
| 11525 %} | |
| 11526 ins_pipe(pipe_slow); | |
| 11527 %} | |
| 11528 | |
|
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|
11529 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{ |
| 17780 | 11530 predicate(!Compile::current()->use_rtm()); |
| 0 | 11531 match(Set cr (FastLock object box)); |
| 4777 | 11532 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 11533 ins_cost(300); |
| 4777 | 11534 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %} |
|
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|
11535 ins_encode %{ |
| 17780 | 11536 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
| 11537 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); | |
|
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|
11538 %} |
| 0 | 11539 ins_pipe(pipe_slow); |
| 11540 %} | |
| 11541 | |
|
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|
11542 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{ |
| 0 | 11543 match(Set cr (FastUnlock object box)); |
| 4777 | 11544 effect(TEMP tmp, USE_KILL box); |
| 0 | 11545 ins_cost(300); |
| 4777 | 11546 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %} |
|
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|
11547 ins_encode %{ |
| 17780 | 11548 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
|
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|
11549 %} |
| 0 | 11550 ins_pipe(pipe_slow); |
| 11551 %} | |
| 11552 | |
| 11553 | |
| 11554 // ============================================================================ | |
| 11555 // Safepoint Instructions | |
| 11556 instruct safePoint_poll(rFlagsReg cr) | |
| 11557 %{ | |
|
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|
11558 predicate(!Assembler::is_polling_page_far()); |
| 0 | 11559 match(SafePoint); |
| 11560 effect(KILL cr); | |
| 11561 | |
|
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|
11562 format %{ "testl rax, [rip + #offset_to_poll_page]\t" |
| 0 | 11563 "# Safepoint: poll for GC" %} |
| 11564 ins_cost(125); | |
|
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|
11565 ins_encode %{ |
|
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|
11566 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type); |
|
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|
11567 __ testl(rax, addr); |
|
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|
11568 %} |
|
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|
11569 ins_pipe(ialu_reg_mem); |
|
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|
11570 %} |
|
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|
11571 |
|
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|
11572 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll) |
|
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|
11573 %{ |
|
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|
11574 predicate(Assembler::is_polling_page_far()); |
|
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|
11575 match(SafePoint poll); |
|
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|
11576 effect(KILL cr, USE poll); |
|
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|
11577 |
|
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|
11578 format %{ "testl rax, [$poll]\t" |
|
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|
11579 "# Safepoint: poll for GC" %} |
|
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|
11580 ins_cost(125); |
|
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diff
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|
11581 ins_encode %{ |
|
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|
11582 __ relocate(relocInfo::poll_type); |
|
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|
11583 __ testl(rax, Address($poll$$Register, 0)); |
|
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|
11584 %} |
| 0 | 11585 ins_pipe(ialu_reg_mem); |
| 11586 %} | |
| 11587 | |
| 11588 // ============================================================================ | |
| 11589 // Procedure Call/Return Instructions | |
| 11590 // Call Java Static Instruction | |
| 11591 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11592 // compute_padding() functions will have to be adjusted. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
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diff
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|
11593 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 11594 match(CallStaticJava); |
| 11595 effect(USE meth); | |
| 11596 | |
| 11597 ins_cost(300); | |
| 11598 format %{ "call,static " %} | |
| 11599 opcode(0xE8); /* E8 cd */ | |
|
8873
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|
11600 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog); |
| 0 | 11601 ins_pipe(pipe_slow); |
| 11602 ins_alignment(4); | |
| 11603 %} | |
| 11604 | |
| 11605 // Call Java Dynamic Instruction | |
| 11606 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 11607 // compute_padding() functions will have to be adjusted. | |
| 11608 instruct CallDynamicJavaDirect(method meth) | |
| 11609 %{ | |
| 11610 match(CallDynamicJava); | |
| 11611 effect(USE meth); | |
| 11612 | |
| 11613 ins_cost(300); | |
| 11614 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 11615 "call,dynamic " %} | |
|
8873
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|
11616 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog); |
| 0 | 11617 ins_pipe(pipe_slow); |
| 11618 ins_alignment(4); | |
| 11619 %} | |
| 11620 | |
| 11621 // Call Runtime Instruction | |
| 11622 instruct CallRuntimeDirect(method meth) | |
| 11623 %{ | |
| 11624 match(CallRuntime); | |
| 11625 effect(USE meth); | |
| 11626 | |
| 11627 ins_cost(300); | |
| 11628 format %{ "call,runtime " %} | |
|
8873
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diff
changeset
|
11629 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11630 ins_pipe(pipe_slow); |
| 11631 %} | |
| 11632 | |
| 11633 // Call runtime without safepoint | |
| 11634 instruct CallLeafDirect(method meth) | |
| 11635 %{ | |
| 11636 match(CallLeaf); | |
| 11637 effect(USE meth); | |
| 11638 | |
| 11639 ins_cost(300); | |
| 11640 format %{ "call_leaf,runtime " %} | |
|
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|
11641 ins_encode(clear_avx, Java_To_Runtime(meth)); |
| 0 | 11642 ins_pipe(pipe_slow); |
| 11643 %} | |
| 11644 | |
| 11645 // Call runtime without safepoint | |
| 11646 instruct CallLeafNoFPDirect(method meth) | |
| 11647 %{ | |
| 11648 match(CallLeafNoFP); | |
| 11649 effect(USE meth); | |
| 11650 | |
| 11651 ins_cost(300); | |
| 11652 format %{ "call_leaf_nofp,runtime " %} | |
| 11653 ins_encode(Java_To_Runtime(meth)); | |
| 11654 ins_pipe(pipe_slow); | |
| 11655 %} | |
| 11656 | |
| 11657 // Return Instruction | |
| 11658 // Remove the return address & jump to it. | |
| 11659 // Notice: We always emit a nop after a ret to make sure there is room | |
| 11660 // for safepoint patching | |
| 11661 instruct Ret() | |
| 11662 %{ | |
| 11663 match(Return); | |
| 11664 | |
| 11665 format %{ "ret" %} | |
| 11666 opcode(0xC3); | |
| 11667 ins_encode(OpcP); | |
| 11668 ins_pipe(pipe_jmp); | |
| 11669 %} | |
| 11670 | |
| 11671 // Tail Call; Jump from runtime stub to Java code. | |
| 11672 // Also known as an 'interprocedural jump'. | |
| 11673 // Target of jump will eventually return to caller. | |
| 11674 // TailJump below removes the return address. | |
| 11675 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 11676 %{ | |
| 11677 match(TailCall jump_target method_oop); | |
| 11678 | |
| 11679 ins_cost(300); | |
| 11680 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 11681 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11682 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11683 ins_pipe(pipe_jmp); | |
| 11684 %} | |
| 11685 | |
| 11686 // Tail Jump; remove the return address; jump to target. | |
| 11687 // TailCall above leaves the return address around. | |
| 11688 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 11689 %{ | |
| 11690 match(TailJump jump_target ex_oop); | |
| 11691 | |
| 11692 ins_cost(300); | |
| 11693 format %{ "popq rdx\t# pop return address\n\t" | |
| 11694 "jmp $jump_target" %} | |
| 11695 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 11696 ins_encode(Opcode(0x5a), // popq rdx | |
| 11697 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 11698 ins_pipe(pipe_jmp); | |
| 11699 %} | |
| 11700 | |
| 11701 // Create exception oop: created by stack-crawling runtime code. | |
| 11702 // Created exception is now available to this handler, and is setup | |
| 11703 // just prior to jumping to this handler. No code emitted. | |
| 11704 instruct CreateException(rax_RegP ex_oop) | |
| 11705 %{ | |
| 11706 match(Set ex_oop (CreateEx)); | |
| 11707 | |
| 11708 size(0); | |
| 11709 // use the following format syntax | |
| 11710 format %{ "# exception oop is in rax; no code emitted" %} | |
| 11711 ins_encode(); | |
| 11712 ins_pipe(empty); | |
| 11713 %} | |
| 11714 | |
| 11715 // Rethrow exception: | |
| 11716 // The exception oop will come in the first argument position. | |
| 11717 // Then JUMP (not call) to the rethrow stub code. | |
| 11718 instruct RethrowException() | |
| 11719 %{ | |
| 11720 match(Rethrow); | |
| 11721 | |
| 11722 // use the following format syntax | |
| 11723 format %{ "jmp rethrow_stub" %} | |
| 11724 ins_encode(enc_rethrow); | |
| 11725 ins_pipe(pipe_jmp); | |
| 11726 %} | |
| 11727 | |
| 11728 | |
| 4950 | 11729 // ============================================================================ |
| 11730 // This name is KNOWN by the ADLC and cannot be changed. | |
| 11731 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 11732 // for this guy. | |
| 11733 instruct tlsLoadP(r15_RegP dst) %{ | |
| 11734 match(Set dst (ThreadLocal)); | |
| 11735 effect(DEF dst); | |
| 11736 | |
| 11737 size(0); | |
| 11738 format %{ "# TLS is in R15" %} | |
| 11739 ins_encode( /*empty encoding*/ ); | |
| 11740 ins_pipe(ialu_reg_reg); | |
| 11741 %} | |
| 11742 | |
| 11743 | |
| 0 | 11744 //----------PEEPHOLE RULES----------------------------------------------------- |
| 11745 // These must follow all instruction definitions as they use the names | |
| 11746 // defined in the instructions definitions. | |
| 11747 // | |
| 605 | 11748 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 11749 // |
| 11750 // peepconstraint %{ | |
| 11751 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11752 // [, ...] ); | |
| 11753 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11754 // | |
| 11755 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11756 // // provide an instruction_number.operand_name for each operand that appears | |
| 11757 // // in the replacement instruction's match rule | |
| 11758 // | |
| 11759 // ---------VM FLAGS--------------------------------------------------------- | |
| 11760 // | |
| 11761 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11762 // | |
| 11763 // Each peephole rule is given an identifying number starting with zero and | |
| 11764 // increasing by one in the order seen by the parser. An individual peephole | |
| 11765 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11766 // on the command-line. | |
| 11767 // | |
| 11768 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11769 // | |
| 11770 // Only match adjacent instructions in same basic block | |
| 11771 // Only equality constraints | |
| 11772 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 11773 // Only one replacement instruction | |
| 11774 // | |
| 11775 // ---------EXAMPLE---------------------------------------------------------- | |
| 11776 // | |
| 11777 // // pertinent parts of existing instructions in architecture description | |
| 11778 // instruct movI(rRegI dst, rRegI src) | |
| 11779 // %{ | |
| 11780 // match(Set dst (CopyI src)); | |
| 11781 // %} | |
| 11782 // | |
| 11783 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 11784 // %{ | |
| 11785 // match(Set dst (AddI dst src)); | |
| 11786 // effect(KILL cr); | |
| 11787 // %} | |
| 11788 // | |
| 11789 // // Change (inc mov) to lea | |
| 11790 // peephole %{ | |
| 11791 // // increment preceeded by register-register move | |
| 11792 // peepmatch ( incI_rReg movI ); | |
| 11793 // // require that the destination register of the increment | |
| 11794 // // match the destination register of the move | |
| 11795 // peepconstraint ( 0.dst == 1.dst ); | |
| 11796 // // construct a replacement instruction that sets | |
| 11797 // // the destination to ( move's source register + one ) | |
| 11798 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 11799 // %} | |
| 11800 // | |
| 11801 | |
| 11802 // Implementation no longer uses movX instructions since | |
| 11803 // machine-independent system no longer uses CopyX nodes. | |
| 11804 // | |
| 11805 // peephole | |
| 11806 // %{ | |
| 11807 // peepmatch (incI_rReg movI); | |
| 11808 // peepconstraint (0.dst == 1.dst); | |
| 11809 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11810 // %} | |
| 11811 | |
| 11812 // peephole | |
| 11813 // %{ | |
| 11814 // peepmatch (decI_rReg movI); | |
| 11815 // peepconstraint (0.dst == 1.dst); | |
| 11816 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11817 // %} | |
| 11818 | |
| 11819 // peephole | |
| 11820 // %{ | |
| 11821 // peepmatch (addI_rReg_imm movI); | |
| 11822 // peepconstraint (0.dst == 1.dst); | |
| 11823 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 11824 // %} | |
| 11825 | |
| 11826 // peephole | |
| 11827 // %{ | |
| 11828 // peepmatch (incL_rReg movL); | |
| 11829 // peepconstraint (0.dst == 1.dst); | |
| 11830 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11831 // %} | |
| 11832 | |
| 11833 // peephole | |
| 11834 // %{ | |
| 11835 // peepmatch (decL_rReg movL); | |
| 11836 // peepconstraint (0.dst == 1.dst); | |
| 11837 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11838 // %} | |
| 11839 | |
| 11840 // peephole | |
| 11841 // %{ | |
| 11842 // peepmatch (addL_rReg_imm movL); | |
| 11843 // peepconstraint (0.dst == 1.dst); | |
| 11844 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 11845 // %} | |
| 11846 | |
| 11847 // peephole | |
| 11848 // %{ | |
| 11849 // peepmatch (addP_rReg_imm movP); | |
| 11850 // peepconstraint (0.dst == 1.dst); | |
| 11851 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 11852 // %} | |
| 11853 | |
| 11854 // // Change load of spilled value to only a spill | |
| 11855 // instruct storeI(memory mem, rRegI src) | |
| 11856 // %{ | |
| 11857 // match(Set mem (StoreI mem src)); | |
| 11858 // %} | |
| 11859 // | |
| 11860 // instruct loadI(rRegI dst, memory mem) | |
| 11861 // %{ | |
| 11862 // match(Set dst (LoadI mem)); | |
| 11863 // %} | |
| 11864 // | |
| 11865 | |
| 11866 peephole | |
| 11867 %{ | |
| 11868 peepmatch (loadI storeI); | |
| 11869 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11870 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 11871 %} | |
| 11872 | |
| 11873 peephole | |
| 11874 %{ | |
| 11875 peepmatch (loadL storeL); | |
| 11876 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 11877 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 11878 %} | |
| 11879 | |
| 11880 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 11881 // These must follow all instruction definitions as they use the names | |
| 11882 // defined in the instructions definitions. |