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comparison src/cpu/x86/vm/x86_32.ad @ 14428:044b28168e20

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8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation Summary: added ability in C2 to expand mach nodes to several mach nodes after register allocation Reviewed-by: kvn
author goetz
date Thu, 14 Nov 2013 19:24:59 -0800
parents 2b8e28fdf503
children 50fdb38839eb
comparison
equal deleted inserted replaced
14427:eb178e97560c 14428:044b28168e20
483 //============================================================================= 483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; 484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485 485
486 int Compile::ConstantTable::calculate_table_base_offset() const { 486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset 487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
491 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
488 } 493 }
489 494
490 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
491 // Empty encoding 496 // Empty encoding
492 } 497 }
1387 const int Matcher::long_cmove_cost() { return 1; } 1392 const int Matcher::long_cmove_cost() { return 1; }
1388 1393
1389 // No CMOVF/CMOVD with SSE/SSE2 1394 // No CMOVF/CMOVD with SSE/SSE2
1390 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } 1395 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1391 1396
1397 // Does the CPU require late expand (see block.cpp for description of late expand)?
1398 const bool Matcher::require_postalloc_expand = false;
1399
1392 // Should the Matcher clone shifts on addressing modes, expecting them to 1400 // Should the Matcher clone shifts on addressing modes, expecting them to
1393 // be subsumed into complex addressing expressions or compute them into 1401 // be subsumed into complex addressing expressions or compute them into
1394 // registers? True for Intel but false for most RISCs 1402 // registers? True for Intel but false for most RISCs
1395 const bool Matcher::clone_shift_expressions = true; 1403 const bool Matcher::clone_shift_expressions = true;
1396 1404