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comparison src/share/vm/c1/c1_LIR.cpp @ 1681:126ea7725993

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6953477: Increase portability and flexibility of building Hotspot Summary: A collection of portability improvements including shared code support for PPC, ARM platforms, software floating point, cross compilation support and improvements in error crash detail. Reviewed-by: phh, never, coleenp, dholmes
author bobv
date Tue, 03 Aug 2010 08:13:38 -0400
parents e9ff18c4ace7
children d5d065957597
comparison
equal deleted inserted replaced
1680:a64438a2b7e8 1681:126ea7725993
48 return FrameMap::nr2xmmreg(xmm_regnrLo()); 48 return FrameMap::nr2xmmreg(xmm_regnrLo());
49 } 49 }
50 50
51 #endif // X86 51 #endif // X86
52 52
53 53 #if defined(SPARC) || defined(PPC)
54 #ifdef SPARC
55 54
56 FloatRegister LIR_OprDesc::as_float_reg() const { 55 FloatRegister LIR_OprDesc::as_float_reg() const {
57 return FrameMap::nr2floatreg(fpu_regnr()); 56 return FrameMap::nr2floatreg(fpu_regnr());
58 } 57 }
59 58
60 FloatRegister LIR_OprDesc::as_double_reg() const { 59 FloatRegister LIR_OprDesc::as_double_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnrHi()); 60 return FrameMap::nr2floatreg(fpu_regnrHi());
62 } 61 }
63 62
64 #endif 63 #endif
64
65 #ifdef ARM
66
67 FloatRegister LIR_OprDesc::as_float_reg() const {
68 return as_FloatRegister(fpu_regnr());
69 }
70
71 FloatRegister LIR_OprDesc::as_double_reg() const {
72 return as_FloatRegister(fpu_regnrLo());
73 }
74
75 #endif
76
65 77
66 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 78 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
67 79
68 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 80 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
69 ValueTag tag = type->tag(); 81 ValueTag tag = type->tag();
117 } 129 }
118 130
119 131
120 #ifndef PRODUCT 132 #ifndef PRODUCT
121 void LIR_Address::verify() const { 133 void LIR_Address::verify() const {
122 #ifdef SPARC 134 #if defined(SPARC) || defined(PPC)
123 assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used"); 135 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
124 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 136 assert(disp() == 0 || index()->is_illegal(), "can't have both");
137 #endif
138 #ifdef ARM
139 assert(disp() == 0 || index()->is_illegal(), "can't have both");
140 assert(-4096 < disp() && disp() < 4096, "architecture constraint");
125 #endif 141 #endif
126 #ifdef _LP64 142 #ifdef _LP64
127 assert(base()->is_cpu_register(), "wrong base operand"); 143 assert(base()->is_cpu_register(), "wrong base operand");
128 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 144 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
129 assert(base()->type() == T_OBJECT || base()->type() == T_LONG, 145 assert(base()->type() == T_OBJECT || base()->type() == T_LONG,
171 187
172 #ifdef ASSERT 188 #ifdef ASSERT
173 if (!is_pointer() && !is_illegal()) { 189 if (!is_pointer() && !is_illegal()) {
174 switch (as_BasicType(type_field())) { 190 switch (as_BasicType(type_field())) {
175 case T_LONG: 191 case T_LONG:
176 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == double_size, "must match"); 192 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
193 size_field() == double_size, "must match");
177 break; 194 break;
178 case T_FLOAT: 195 case T_FLOAT:
179 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == single_size, "must match"); 196 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
197 assert((kind_field() == fpu_register || kind_field() == stack_value
198 ARM_ONLY(|| kind_field() == cpu_register)
199 PPC_ONLY(|| kind_field() == cpu_register) ) &&
200 size_field() == single_size, "must match");
180 break; 201 break;
181 case T_DOUBLE: 202 case T_DOUBLE:
182 assert((kind_field() == fpu_register || kind_field() == stack_value) && size_field() == double_size, "must match"); 203 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
204 assert((kind_field() == fpu_register || kind_field() == stack_value
205 ARM_ONLY(|| kind_field() == cpu_register)
206 PPC_ONLY(|| kind_field() == cpu_register) ) &&
207 size_field() == double_size, "must match");
183 break; 208 break;
184 case T_BOOLEAN: 209 case T_BOOLEAN:
185 case T_CHAR: 210 case T_CHAR:
186 case T_BYTE: 211 case T_BYTE:
187 case T_SHORT: 212 case T_SHORT:
188 case T_INT: 213 case T_INT:
189 case T_OBJECT: 214 case T_OBJECT:
190 case T_ARRAY: 215 case T_ARRAY:
191 assert((kind_field() == cpu_register || kind_field() == stack_value) && size_field() == single_size, "must match"); 216 assert((kind_field() == cpu_register || kind_field() == stack_value) &&
217 size_field() == single_size, "must match");
192 break; 218 break;
193 219
194 case T_ILLEGAL: 220 case T_ILLEGAL:
195 // XXX TKR also means unknown right now 221 // XXX TKR also means unknown right now
196 // assert(is_illegal(), "must match"); 222 // assert(is_illegal(), "must match");
501 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 527 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
502 528
503 assert(opConvert->_info == NULL, "must be"); 529 assert(opConvert->_info == NULL, "must be");
504 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 530 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
505 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 531 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
532 #ifdef PPC
533 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
534 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
535 #endif
506 do_stub(opConvert->_stub); 536 do_stub(opConvert->_stub);
507 537
508 break; 538 break;
509 } 539 }
510 540
528 { 558 {
529 assert(op->as_OpAllocObj() != NULL, "must be"); 559 assert(op->as_OpAllocObj() != NULL, "must be");
530 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 560 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
531 561
532 if (opAllocObj->_info) do_info(opAllocObj->_info); 562 if (opAllocObj->_info) do_info(opAllocObj->_info);
533 if (opAllocObj->_opr->is_valid()) do_input(opAllocObj->_opr); 563 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
564 do_temp(opAllocObj->_opr);
565 }
534 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 566 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
535 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 567 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
536 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 568 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
537 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 569 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
538 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 570 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
824 case lir_cas_obj: 856 case lir_cas_obj:
825 case lir_cas_int: { 857 case lir_cas_int: {
826 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 858 assert(op->as_OpCompareAndSwap() != NULL, "must be");
827 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 859 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
828 860
861 assert(opCompareAndSwap->_addr->is_valid(), "used");
862 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
863 assert(opCompareAndSwap->_new_value->is_valid(), "used");
829 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 864 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
830 if (opCompareAndSwap->_addr->is_valid()) do_input(opCompareAndSwap->_addr); 865 do_input(opCompareAndSwap->_addr);
831 if (opCompareAndSwap->_cmp_value->is_valid()) do_input(opCompareAndSwap->_cmp_value); 866 do_temp(opCompareAndSwap->_addr);
832 if (opCompareAndSwap->_new_value->is_valid()) do_input(opCompareAndSwap->_new_value); 867 do_input(opCompareAndSwap->_cmp_value);
868 do_temp(opCompareAndSwap->_cmp_value);
869 do_input(opCompareAndSwap->_new_value);
870 do_temp(opCompareAndSwap->_new_value);
833 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 871 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
834 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 872 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
835 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 873 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
836 874
837 break; 875 break;
1301 scratch, 1339 scratch,
1302 stub, 1340 stub,
1303 info)); 1341 info));
1304 } 1342 }
1305 1343
1306 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, CodeStub* stub) { 1344 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1307 append(new LIR_OpLock( 1345 append(new LIR_OpLock(
1308 lir_unlock, 1346 lir_unlock,
1309 hdr, 1347 hdr,
1310 obj, 1348 obj,
1311 lock, 1349 lock,
1312 LIR_OprFact::illegalOpr, 1350 scratch,
1313 stub, 1351 stub,
1314 NULL)); 1352 NULL));
1315 } 1353 }
1316 1354
1317 1355
1340 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) { 1378 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) {
1341 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0)); 1379 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0));
1342 } 1380 }
1343 1381
1344 1382
1345 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1383 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1346 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, 1384 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1347 // implying successful swap of new_value into addr 1385 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1348 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2)); 1386 }
1349 } 1387
1350 1388 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1351 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1389 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1352 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value, 1390 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1353 // implying successful swap of new_value into addr 1391 }
1354 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2)); 1392
1355 } 1393 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1356 1394 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1357 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, LIR_Opr t1, LIR_Opr t2) { 1395 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1358 // Compare and swap produces condition code "zero" if contents_of(addr) == cmp_value,
1359 // implying successful swap of new_value into addr
1360 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2));
1361 } 1396 }
1362 1397
1363 1398
1364 #ifdef PRODUCT 1399 #ifdef PRODUCT
1365 1400
1398 out->print(as_xmm_double_reg()->name()); 1433 out->print(as_xmm_double_reg()->name());
1399 } else if (is_single_fpu()) { 1434 } else if (is_single_fpu()) {
1400 out->print("fpu%d", fpu_regnr()); 1435 out->print("fpu%d", fpu_regnr());
1401 } else if (is_double_fpu()) { 1436 } else if (is_double_fpu()) {
1402 out->print("fpu%d", fpu_regnrLo()); 1437 out->print("fpu%d", fpu_regnrLo());
1438 #elif defined(ARM)
1439 } else if (is_single_fpu()) {
1440 out->print("s%d", fpu_regnr());
1441 } else if (is_double_fpu()) {
1442 out->print("d%d", fpu_regnrLo() >> 1);
1403 #else 1443 #else
1404 } else if (is_single_fpu()) { 1444 } else if (is_single_fpu()) {
1405 out->print(as_float_reg()->name()); 1445 out->print(as_float_reg()->name());
1406 } else if (is_double_fpu()) { 1446 } else if (is_double_fpu()) {
1407 out->print(as_double_reg()->name()); 1447 out->print(as_double_reg()->name());
1754 // LIR_OpConvert 1794 // LIR_OpConvert
1755 void LIR_OpConvert::print_instr(outputStream* out) const { 1795 void LIR_OpConvert::print_instr(outputStream* out) const {
1756 print_bytecode(out, bytecode()); 1796 print_bytecode(out, bytecode());
1757 in_opr()->print(out); out->print(" "); 1797 in_opr()->print(out); out->print(" ");
1758 result_opr()->print(out); out->print(" "); 1798 result_opr()->print(out); out->print(" ");
1799 #ifdef PPC
1800 if(tmp1()->is_valid()) {
1801 tmp1()->print(out); out->print(" ");
1802 tmp2()->print(out); out->print(" ");
1803 }
1804 #endif
1759 } 1805 }
1760 1806
1761 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1807 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1762 switch(code) { 1808 switch(code) {
1763 case Bytecodes::_d2f: out->print("[d2f] "); break; 1809 case Bytecodes::_d2f: out->print("[d2f] "); break;