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comparison src/cpu/x86/vm/vm_version_x86.hpp @ 20438:166d744df0de

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8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM. Reviewed-by: roland
author kvn
date Tue, 02 Sep 2014 12:48:45 -0700
parents 999824269b71
children 7848fc12602b a8c8adf853c2
comparison
equal deleted inserted replaced
20437:bddcb33dadf4 20438:166d744df0de
207 : 2, 207 : 2,
208 bmi2 : 1, 208 bmi2 : 1,
209 erms : 1, 209 erms : 1,
210 : 1, 210 : 1,
211 rtm : 1, 211 rtm : 1,
212 : 20; 212 : 7,
213 adx : 1,
214 : 12;
213 } bits; 215 } bits;
214 }; 216 };
215 217
216 union XemXcr0Eax { 218 union XemXcr0Eax {
217 uint32_t value; 219 uint32_t value;
258 CPU_AES = (1 << 19), 260 CPU_AES = (1 << 19),
259 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 261 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
260 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 262 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
261 CPU_BMI1 = (1 << 22), 263 CPU_BMI1 = (1 << 22),
262 CPU_BMI2 = (1 << 23), 264 CPU_BMI2 = (1 << 23),
263 CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions 265 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
266 CPU_ADX = (1 << 25)
264 } cpuFeatureFlags; 267 } cpuFeatureFlags;
265 268
266 enum { 269 enum {
267 // AMD 270 // AMD
268 CPU_FAMILY_AMD_11H = 0x11, 271 CPU_FAMILY_AMD_11H = 0x11,
463 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 466 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
464 result |= CPU_SSE4A; 467 result |= CPU_SSE4A;
465 } 468 }
466 // Intel features. 469 // Intel features.
467 if(is_intel()) { 470 if(is_intel()) {
471 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
472 result |= CPU_ADX;
468 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 473 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
469 result |= CPU_BMI2; 474 result |= CPU_BMI2;
470 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 475 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
471 result |= CPU_LZCNT; 476 result |= CPU_LZCNT;
477 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
478 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
479 result |= CPU_3DNOW_PREFETCH;
480 }
472 } 481 }
473 482
474 return result; 483 return result;
475 } 484 }
476 485
619 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 628 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; }
620 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 629 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; }
621 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } 630 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; }
622 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } 631 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; }
623 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } 632 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; }
633 static bool supports_adx() { return (_cpuFeatures & CPU_ADX) != 0; }
624 // Intel features 634 // Intel features
625 static bool is_intel_family_core() { return is_intel() && 635 static bool is_intel_family_core() { return is_intel() &&
626 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 636 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
627 637
628 static bool is_intel_tsc_synched_at_init() { 638 static bool is_intel_tsc_synched_at_init() {