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comparison src/cpu/sparc/vm/vm_version_sparc.cpp @ 3854:1af104d6cf99

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7079329: Adjust allocation prefetching for T4 Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes Reviewed-by: iveresov, phh, twisti
author kvn
date Tue, 16 Aug 2011 16:59:46 -0700
parents 95134e034042
children baf763f388e6
comparison
equal deleted inserted replaced
3853:11211f7cb5a0 3854:1af104d6cf99
42 _features = determine_features(); 42 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
45 PrefetchFieldsAhead = prefetch_fields_ahead(); 45 PrefetchFieldsAhead = prefetch_fields_ahead();
46 46
47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
50
47 // Allocation prefetch settings 51 // Allocation prefetch settings
48 intx cache_line_size = L1_data_cache_line_size(); 52 intx cache_line_size = prefetch_data_size();
49 if( cache_line_size > AllocatePrefetchStepSize ) 53 if( cache_line_size > AllocatePrefetchStepSize )
50 AllocatePrefetchStepSize = cache_line_size; 54 AllocatePrefetchStepSize = cache_line_size;
51 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) 55
52 AllocatePrefetchLines = 3; // Optimistic value 56 assert(AllocatePrefetchLines > 0, "invalid value");
53 assert( AllocatePrefetchLines > 0, "invalid value"); 57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
54 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 58 AllocatePrefetchLines = 3;
55 AllocatePrefetchLines = 1; // Conservative value 59 assert(AllocateInstancePrefetchLines > 0, "invalid value");
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
61 AllocateInstancePrefetchLines = 1;
56 62
57 AllocatePrefetchDistance = allocate_prefetch_distance(); 63 AllocatePrefetchDistance = allocate_prefetch_distance();
58 AllocatePrefetchStyle = allocate_prefetch_style(); 64 AllocatePrefetchStyle = allocate_prefetch_style();
59 65
60 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
67 (AllocatePrefetchDistance > 0), "invalid value");
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
69 (AllocatePrefetchDistance <= 0)) {
70 AllocatePrefetchDistance = AllocatePrefetchStepSize;
71 }
61 72
62 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
63 warning("BIS instructions are not available on this CPU"); 74 warning("BIS instructions are not available on this CPU");
64 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
65 } 76 }
66 77
67 UseSSE = 0; // Only on x86 and x64 78 UseSSE = 0; // Only on x86 and x64
68 79
69 _supports_cx8 = has_v9(); 80 _supports_cx8 = has_v9();
70 81
71 if (is_niagara()) { 82 if (is_niagara()) {
72 // Indirect branch is the same cost as direct 83 // Indirect branch is the same cost as direct
73 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 84 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
74 FLAG_SET_DEFAULT(UseInlineCaches, false); 85 FLAG_SET_DEFAULT(UseInlineCaches, false);
97 // aligned on a single instruction boundary 108 // aligned on a single instruction boundary
98 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 109 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
99 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 110 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
100 } 111 }
101 if (is_niagara_plus()) { 112 if (is_niagara_plus()) {
102 if (has_blk_init() && AllocatePrefetchStyle > 0 && 113 if (has_blk_init() && UseTLAB &&
103 FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 114 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
104 // Use BIS instruction for allocation prefetch. 115 // Use BIS instruction for TLAB allocation prefetch.
105 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 116 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
117 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
118 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
119 }
106 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 120 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
107 // Use smaller prefetch distance on N2 with BIS 121 // Use smaller prefetch distance with BIS
108 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 122 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
123 }
124 }
125 if (is_T4()) {
126 // Double number of prefetched cache lines on T4
127 // since L2 cache line size is smaller (32 bytes).
128 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
129 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
130 }
131 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
132 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
109 } 133 }
110 } 134 }
111 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 135 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
112 // Use different prefetch distance without BIS 136 // Use different prefetch distance without BIS
113 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 137 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
138 }
139 if (AllocatePrefetchInstr == 1) {
140 // Need a space at the end of TLAB for BIS since it
141 // will fault when accessing memory outside of heap.
142
143 // +1 for rounding up to next cache line, +1 to be safe
144 int lines = AllocatePrefetchLines + 2;
145 int step_size = AllocatePrefetchStepSize;
146 int distance = AllocatePrefetchDistance;
147 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
114 } 148 }
115 } 149 }
116 #endif 150 #endif
117 } 151 }
118 152
183 if (!has_vis1()) // Drop to 0 if no VIS1 support 217 if (!has_vis1()) // Drop to 0 if no VIS1 support
184 UseVIS = 0; 218 UseVIS = 0;
185 219
186 #ifndef PRODUCT 220 #ifndef PRODUCT
187 if (PrintMiscellaneous && Verbose) { 221 if (PrintMiscellaneous && Verbose) {
188 tty->print("Allocation: "); 222 tty->print("Allocation");
189 if (AllocatePrefetchStyle <= 0) { 223 if (AllocatePrefetchStyle <= 0) {
190 tty->print_cr("no prefetching"); 224 tty->print_cr(": no prefetching");
191 } else { 225 } else {
226 tty->print(" prefetching: ");
227 if (AllocatePrefetchInstr == 0) {
228 tty->print("PREFETCH");
229 } else if (AllocatePrefetchInstr == 1) {
230 tty->print("BIS");
231 }
192 if (AllocatePrefetchLines > 1) { 232 if (AllocatePrefetchLines > 1) {
193 tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); 233 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
194 } else { 234 } else {
195 tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance); 235 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
196 } 236 }
197 } 237 }
198 if (PrefetchCopyIntervalInBytes > 0) { 238 if (PrefetchCopyIntervalInBytes > 0) {
199 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); 239 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
200 } 240 }