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comparison src/cpu/sparc/vm/sparc.ad @ 951:1fbd5d696bf4

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6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711 Reviewed-by: cfang, never
author twisti
date Mon, 31 Aug 2009 02:24:21 -0700
parents 18a08a7e16b5
children 62001a362ce9
comparison
equal deleted inserted replaced
950:8fe1963e3964 951:1fbd5d696bf4
5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5707 effect(TEMP dst, TEMP tmp); 5707 effect(TEMP dst, TEMP tmp);
5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5709 5709
5710 size(3*4); 5710 size((3+1)*4); // set may use two instructions.
5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5712 "SET $mask,$tmp\n\t" 5712 "SET $mask,$tmp\n\t"
5713 "AND $dst,$tmp,$dst" %} 5713 "AND $dst,$tmp,$dst" %}
5714 ins_encode %{ 5714 ins_encode %{
5715 Register Rdst = $dst$$Register; 5715 Register Rdst = $dst$$Register;
5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5851 effect(TEMP dst, TEMP tmp); 5851 effect(TEMP dst, TEMP tmp);
5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5853 5853
5854 size(3*4); 5854 size((3+1)*4); // set may use two instructions.
5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5856 "SET $mask,$tmp\n\t" 5856 "SET $mask,$tmp\n\t"
5857 "AND $dst,$tmp,$dst" %} 5857 "AND $dst,$tmp,$dst" %}
5858 ins_encode %{ 5858 ins_encode %{
5859 Register Rdst = $dst$$Register; 5859 Register Rdst = $dst$$Register;