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comparison src/os_cpu/solaris_sparc/vm/assembler_solaris_sparc.cpp @ 237:1fdb98a17101

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6716785: implicit null checks not triggering with CompressedOops Summary: allocate alignment-sized page(s) below java heap so that memory accesses at heap_base+1page give signal and cause an implicit null check Reviewed-by: kvn, jmasa, phh, jcoomes
author coleenp
date Sat, 19 Jul 2008 17:38:22 -0400
parents a61af66fc99e
children 9ee9cf798b59
comparison
equal deleted inserted replaced
235:9c2ecc2ffb12 237:1fdb98a17101
26 #include "incls/_assembler_solaris_sparc.cpp.incl" 26 #include "incls/_assembler_solaris_sparc.cpp.incl"
27 27
28 #include <sys/trap.h> // For trap numbers 28 #include <sys/trap.h> // For trap numbers
29 #include <v9/sys/psr_compat.h> // For V8 compatibility 29 #include <v9/sys/psr_compat.h> // For V8 compatibility
30 30
31 bool MacroAssembler::needs_explicit_null_check(intptr_t offset) {
32 // The first page of virtual addresses is unmapped on SPARC.
33 // Thus, any access the VM makes through a null pointer with an offset of
34 // less than 4K will get a recognizable SIGSEGV, which the signal handler
35 // will transform into a NullPointerException.
36 // (Actually, the first 64K or so is unmapped, but it's simpler
37 // to depend only on the first 4K or so.)
38
39 bool offset_in_first_page = 0 <= offset && offset < os::vm_page_size();
40 return !offset_in_first_page;
41 }
42
43 void MacroAssembler::read_ccr_trap(Register ccr_save) { 31 void MacroAssembler::read_ccr_trap(Register ccr_save) {
44 // Execute a trap to get the PSR, mask and shift 32 // Execute a trap to get the PSR, mask and shift
45 // to get the condition codes. 33 // to get the condition codes.
46 get_psr_trap(); 34 get_psr_trap();
47 nop(); 35 nop();