graal-jvmci-8: src/cpu/x86/vm/x86

comparison src/cpu/x86/vm/x86_64.ad @ 14422:2b8e28fdf503

Merge

author	kvn
date	Tue, 05 Nov 2013 17:38:04 -0800
parents	6a936747b569 59e8ad757e19
children	044b28168e20

comparison

equal deleted inserted replaced

-:3068270ba476
+:2b8e28fdf503
 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
 #ifdef ASSERT
 if (rspec.reloc()->type() == relocInfo::oop_type &&
 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
-assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
+assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
 }
 #endif
 cbuf.relocate(cbuf.insts_mark(), rspec, format);
 cbuf.insts()->emit_int32(d32);
 }
 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
 #ifdef ASSERT
 if (rspec.reloc()->type() == relocInfo::oop_type &&
 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
-assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
+assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
 "cannot embed scavengable oops in code");
 }
 #endif
 cbuf.relocate(cbuf.insts_mark(), rspec, format);
 cbuf.insts()->emit_int64(d64);
 //=============================================================================
 #ifndef PRODUCT
 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 {
-if (UseCompressedKlassPointers) {
+if (UseCompressedClassPointers) {
 st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
 st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
 } else {
 st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 {
 MacroAssembler masm(&cbuf);
 uint insts_size = cbuf.insts_size();
-if (UseCompressedKlassPointers) {
+if (UseCompressedClassPointers) {
 masm.load_klass(rscratch1, j_rarg0);
 masm.cmpptr(rax, rscratch1);
 } else {
 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
 }
 assert(UseCompressedOops, "only for compressed oops code");
 return (LogMinObjAlignmentInBytes <= 3);
 }
 bool Matcher::narrow_klass_use_complex_address() {
-assert(UseCompressedKlassPointers, "only for compressed klass code");
+assert(UseCompressedClassPointers, "only for compressed klass code");
 return (LogKlassAlignmentInBytes <= 3);
 }
 // Is it better to copy float constants, or load them directly from
 // memory?  Intel can load a float constant from a direct address,
 return LONG_RDX_REG_mask();
 }
 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 return PTR_RBP_REG_mask();
+}
+const RegMask Matcher::mathExactI_result_proj_mask() {
+return INT_RAX_REG_mask();
+}
+const RegMask Matcher::mathExactL_result_proj_mask() {
+return LONG_RAX_REG_mask();
+}
+const RegMask Matcher::mathExactI_flags_proj_mask() {
+return INT_FLAGS_mask();
 }
 %}
 //----------ENCODING BLOCK-----------------------------------------------------
 not_equal(0x5, "ne");
 less(0xC, "l");
 greater_equal(0xD, "ge");
 less_equal(0xE, "le");
 greater(0xF, "g");
+overflow(0x0, "o");
+no_overflow(0x1, "no");
 %}
 %}
 // Comparison Code, unsigned compare.  Used by FP also, with
 // C2 (unordered) turned into GT or LT already.  The other bits
 not_equal(0x5, "ne");
 less(0x2, "b");
 greater_equal(0x3, "nb");
 less_equal(0x6, "be");
 greater(0x7, "nbe");
+overflow(0x0, "o");
+no_overflow(0x1, "no");
 %}
 %}
 // Floating comparisons that don't require any fixup for the unordered case
 not_equal(0x5, "ne");
 less(0x2, "b");
 greater_equal(0x3, "nb");
 less_equal(0x6, "be");
 greater(0x7, "nbe");
+overflow(0x0, "o");
+no_overflow(0x1, "no");
 %}
 %}
 // Floating comparisons that can be fixed up with extra conditional jumps
 not_equal(0x5, "ne");
 less(0x2, "b");
 greater_equal(0x3, "nb");
 less_equal(0x6, "be");
 greater(0x7, "nbe");
+overflow(0x0, "o");
+no_overflow(0x1, "no");
 %}
 %}
 //----------OPERAND CLASSES----------------------------------------------------
 %}
 //----------Arithmetic Instructions--------------------------------------------
 //----------Addition Instructions----------------------------------------------
+instruct addExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
+%{
+match(AddExactI dst src);
+effect(DEF cr);
+format %{ "addl    $dst, $src\t# addExact int" %}
+ins_encode %{
+__ addl($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct addExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
+%{
+match(AddExactI dst src);
+effect(DEF cr);
+format %{ "addl    $dst, $src\t# addExact int" %}
+ins_encode %{
+__ addl($dst$$Register, $src$$constant);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
+%{
+match(AddExactI dst (LoadI src));
+effect(DEF cr);
+ins_cost(125); // XXX
+format %{ "addl    $dst, $src\t# addExact int" %}
+ins_encode %{
+__ addl($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem);
+%}
+instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
+%{
+match(AddExactL dst src);
+effect(DEF cr);
+format %{ "addq    $dst, $src\t# addExact long" %}
+ins_encode %{
+__ addq($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
+%{
+match(AddExactL dst src);
+effect(DEF cr);
+format %{ "addq    $dst, $src\t# addExact long" %}
+ins_encode %{
+__ addq($dst$$Register, $src$$constant);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
+%{
+match(AddExactL dst (LoadL src));
+effect(DEF cr);
+ins_cost(125); // XXX
+format %{ "addq    $dst, $src\t# addExact long" %}
+ins_encode %{
+__ addq($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem);
+%}
 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 %{
 match(Set dst (AddI dst src));
 effect(KILL cr);
 opcode(0x81); /* Opcode 81 /5 id */
 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
 ins_pipe(ialu_mem_imm);
 %}
+instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
+%{
+match(SubExactI dst src);
+effect(DEF cr);
+format %{ "subl    $dst, $src\t# subExact int" %}
+ins_encode %{
+__ subl($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr)
+%{
+match(SubExactI dst src);
+effect(DEF cr);
+format %{ "subl    $dst, $src\t# subExact int" %}
+ins_encode %{
+__ subl($dst$$Register, $src$$constant);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
+%{
+match(SubExactI dst (LoadI src));
+effect(DEF cr);
+ins_cost(125);
+format %{ "subl    $dst, $src\t# subExact int" %}
+ins_encode %{
+__ subl($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem);
+%}
+instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
+%{
+match(SubExactL dst src);
+effect(DEF cr);
+format %{ "subq    $dst, $src\t# subExact long" %}
+ins_encode %{
+__ subq($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr)
+%{
+match(SubExactL dst (LoadL src));
+effect(DEF cr);
+format %{ "subq    $dst, $src\t# subExact long" %}
+ins_encode %{
+__ subq($dst$$Register, $src$$constant);
+%}
+ins_pipe(ialu_reg_reg);
+%}
+instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
+%{
+match(SubExactI dst src);
+effect(DEF cr);
+ins_cost(125);
+format %{ "subq    $dst, $src\t# subExact long" %}
+ins_encode %{
+__ subq($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem);
+%}
 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 %{
 match(Set dst (SubL dst src));
 effect(KILL cr);
 opcode(0xF7, 0x03);  // Opcode F7 /3
 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
 ins_pipe(ialu_reg);
 %}
+instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr)
+%{
+match(NegExactI dst);
+effect(KILL cr);
+format %{ "negl    $dst\t# negExact int" %}
+ins_encode %{
+__ negl($dst$$Register);
+%}
+ins_pipe(ialu_reg);
+%}
+instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr)
+%{
+match(NegExactL dst);
+effect(KILL cr);
+format %{ "negq    $dst\t# negExact long" %}
+ins_encode %{
+__ negq($dst$$Register);
+%}
+ins_pipe(ialu_reg);
+%}
 //----------Multiplication/Division Instructions-------------------------------
 // Integer Multiplication Instructions
 // Multiply Register
 ins_cost(300);
 format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
 opcode(0xF7, 0x5); /* Opcode F7 /5 */
 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
 ins_pipe(ialu_reg_reg_alu0);
+%}
+instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr)
+%{
+match(MulExactI dst src);
+effect(DEF cr);
+ins_cost(300);
+format %{ "imull   $dst, $src\t# mulExact int" %}
+ins_encode %{
+__ imull($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg_alu0);
+%}
+instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr)
+%{
+match(MulExactI src imm);
+effect(DEF cr);
+ins_cost(300);
+format %{ "imull   $dst, $src, $imm\t# mulExact int" %}
+ins_encode %{
+__ imull($dst$$Register, $src$$Register, $imm$$constant);
+%}
+ins_pipe(ialu_reg_reg_alu0);
+%}
+instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr)
+%{
+match(MulExactI dst (LoadI src));
+effect(DEF cr);
+ins_cost(350);
+format %{ "imull   $dst, $src\t# mulExact int" %}
+ins_encode %{
+__ imull($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem_alu0);
+%}
+instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr)
+%{
+match(MulExactL dst src);
+effect(DEF cr);
+ins_cost(300);
+format %{ "imulq   $dst, $src\t# mulExact long" %}
+ins_encode %{
+__ imulq($dst$$Register, $src$$Register);
+%}
+ins_pipe(ialu_reg_reg_alu0);
+%}
+instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr)
+%{
+match(MulExactL src imm);
+effect(DEF cr);
+ins_cost(300);
+format %{ "imulq   $dst, $src, $imm\t# mulExact long" %}
+ins_encode %{
+__ imulq($dst$$Register, $src$$Register, $imm$$constant);
+%}
+ins_pipe(ialu_reg_reg_alu0);
+%}
+instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr)
+%{
+match(MulExactL dst (LoadL src));
+effect(DEF cr);
+ins_cost(350);
+format %{ "imulq   $dst, $src\t# mulExact long" %}
+ins_encode %{
+__ imulq($dst$$Register, $src$$Address);
+%}
+ins_pipe(ialu_reg_mem_alu0);
 %}
 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 rFlagsReg cr)
 %{

Mercurial > hg > graal-jvmci-8

comparison src/cpu/x86/vm/x86_64.ad @ 14422:2b8e28fdf503