Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/x86_64.ad @ 24206:37ba410ffd43 jdk8u141-b08
8173770: Image conversion improvements
Reviewed-by: kvn, vlivanov, dlong, rhalade, mschoene, iignatyev
| author | thartmann |
|---|---|
| date | Thu, 30 Mar 2017 15:28:33 +0200 |
| parents | c3d0bd36ab28 |
| children | 719853999215 |
comparison
equal
deleted
inserted
replaced
| 24205:b1f3fbe39975 | 24206:37ba410ffd43 |
|---|---|
| 11066 "done:" %} | 11066 "done:" %} |
| 11067 ins_encode(cmpl3_flag(src1, src2, dst)); | 11067 ins_encode(cmpl3_flag(src1, src2, dst)); |
| 11068 ins_pipe(pipe_slow); | 11068 ins_pipe(pipe_slow); |
| 11069 %} | 11069 %} |
| 11070 | 11070 |
| 11071 // Unsigned long compare Instructions; really, same as signed long except they | |
| 11072 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11073 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2) | |
| 11074 %{ | |
| 11075 match(Set cr (CmpUL op1 op2)); | |
| 11076 | |
| 11077 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11078 opcode(0x3B); /* Opcode 3B /r */ | |
| 11079 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11080 ins_pipe(ialu_cr_reg_reg); | |
| 11081 %} | |
| 11082 | |
| 11083 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2) | |
| 11084 %{ | |
| 11085 match(Set cr (CmpUL op1 op2)); | |
| 11086 | |
| 11087 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11088 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11089 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 11090 ins_pipe(ialu_cr_reg_imm); | |
| 11091 %} | |
| 11092 | |
| 11093 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2) | |
| 11094 %{ | |
| 11095 match(Set cr (CmpUL op1 (LoadL op2))); | |
| 11096 | |
| 11097 format %{ "cmpq $op1, $op2\t# unsigned" %} | |
| 11098 opcode(0x3B); /* Opcode 3B /r */ | |
| 11099 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11100 ins_pipe(ialu_cr_reg_mem); | |
| 11101 %} | |
| 11102 | |
| 11103 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero) | |
| 11104 %{ | |
| 11105 match(Set cr (CmpUL src zero)); | |
| 11106 | |
| 11107 format %{ "testq $src, $src\t# unsigned" %} | |
| 11108 opcode(0x85); | |
| 11109 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11110 ins_pipe(ialu_cr_reg_imm); | |
| 11111 %} | |
| 11112 | |
| 11071 //----------Max and Min-------------------------------------------------------- | 11113 //----------Max and Min-------------------------------------------------------- |
| 11072 // Min Instructions | 11114 // Min Instructions |
| 11073 | 11115 |
| 11074 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | 11116 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) |
| 11075 %{ | 11117 %{ |