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comparison src/cpu/sparc/vm/vm_version_sparc.hpp @ 3839:3d42f82cd811

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7063628: Use cbcond on T4 Summary: Add new short branch instruction to Hotspot sparc assembler. Reviewed-by: never, twisti, jrose
author kvn
date Thu, 21 Jul 2011 11:25:07 -0700
parents c04052fd6ae1
children 1af104d6cf99
comparison
equal deleted inserted replaced
3838:6a991dcb52bb 3839:3d42f82cd811
29 #include "runtime/vm_version.hpp" 29 #include "runtime/vm_version.hpp"
30 30
31 class VM_Version: public Abstract_VM_Version { 31 class VM_Version: public Abstract_VM_Version {
32 protected: 32 protected:
33 enum Feature_Flag { 33 enum Feature_Flag {
34 v8_instructions = 0, 34 v8_instructions = 0,
35 hardware_mul32 = 1, 35 hardware_mul32 = 1,
36 hardware_div32 = 2, 36 hardware_div32 = 2,
37 hardware_fsmuld = 3, 37 hardware_fsmuld = 3,
38 hardware_popc = 4, 38 hardware_popc = 4,
39 v9_instructions = 5, 39 v9_instructions = 5,
40 vis1_instructions = 6, 40 vis1_instructions = 6,
41 vis2_instructions = 7, 41 vis2_instructions = 7,
42 sun4v_instructions = 8, 42 sun4v_instructions = 8,
43 blk_init_instructions = 9, 43 blk_init_instructions = 9,
44 fmaf_instructions = 10, 44 fmaf_instructions = 10,
45 fmau_instructions = 11, 45 fmau_instructions = 11,
46 vis3_instructions = 12, 46 vis3_instructions = 12,
47 sparc64_family = 13, 47 sparc64_family = 13,
48 T_family = 14, 48 T_family = 14,
49 T1_model = 15 49 T1_model = 15,
50 cbcond_instructions = 16
50 }; 51 };
51 52
52 enum Feature_Flag_Set { 53 enum Feature_Flag_Set {
53 unknown_m = 0, 54 unknown_m = 0,
54 all_features_m = -1, 55 all_features_m = -1,
55 56
56 v8_instructions_m = 1 << v8_instructions, 57 v8_instructions_m = 1 << v8_instructions,
57 hardware_mul32_m = 1 << hardware_mul32, 58 hardware_mul32_m = 1 << hardware_mul32,
58 hardware_div32_m = 1 << hardware_div32, 59 hardware_div32_m = 1 << hardware_div32,
59 hardware_fsmuld_m = 1 << hardware_fsmuld, 60 hardware_fsmuld_m = 1 << hardware_fsmuld,
60 hardware_popc_m = 1 << hardware_popc, 61 hardware_popc_m = 1 << hardware_popc,
61 v9_instructions_m = 1 << v9_instructions, 62 v9_instructions_m = 1 << v9_instructions,
62 vis1_instructions_m = 1 << vis1_instructions, 63 vis1_instructions_m = 1 << vis1_instructions,
63 vis2_instructions_m = 1 << vis2_instructions, 64 vis2_instructions_m = 1 << vis2_instructions,
64 sun4v_m = 1 << sun4v_instructions, 65 sun4v_m = 1 << sun4v_instructions,
65 blk_init_instructions_m = 1 << blk_init_instructions, 66 blk_init_instructions_m = 1 << blk_init_instructions,
66 fmaf_instructions_m = 1 << fmaf_instructions, 67 fmaf_instructions_m = 1 << fmaf_instructions,
67 fmau_instructions_m = 1 << fmau_instructions, 68 fmau_instructions_m = 1 << fmau_instructions,
68 vis3_instructions_m = 1 << vis3_instructions, 69 vis3_instructions_m = 1 << vis3_instructions,
69 sparc64_family_m = 1 << sparc64_family, 70 sparc64_family_m = 1 << sparc64_family,
70 T_family_m = 1 << T_family, 71 T_family_m = 1 << T_family,
71 T1_model_m = 1 << T1_model, 72 T1_model_m = 1 << T1_model,
73 cbcond_instructions_m = 1 << cbcond_instructions,
72 74
73 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 75 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
74 generic_v9_m = generic_v8_m | v9_instructions_m, 76 generic_v9_m = generic_v8_m | v9_instructions_m,
75 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 77 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
76 78
109 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } 111 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
110 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } 112 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
111 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } 113 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
112 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } 114 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
113 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } 115 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
116 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
114 117
115 static bool supports_compare_and_exchange() 118 static bool supports_compare_and_exchange()
116 { return has_v9(); } 119 { return has_v9(); }
117 120
118 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; }
119 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
120 // Returns true if the platform is in the niagara line (T series) 121 // Returns true if the platform is in the niagara line (T series)
121 // and newer than the niagara1. 122 // and newer than the niagara1.
122 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } 123 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
124
123 // Fujitsu SPARC64 125 // Fujitsu SPARC64
124 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } 126 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
125 127
128 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
129 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
130
126 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } 131 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
127 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } 132 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
133 // T4 and newer Sparc have fast RDPC instruction.
134 static bool has_fast_rdpc() { return is_niagara_plus() && has_cbcond(); }
128 135
129 static const char* cpu_features() { return _features_str; } 136 static const char* cpu_features() { return _features_str; }
130 137
131 static intx L1_data_cache_line_size() { 138 static intx L1_data_cache_line_size() {
132 return 64; // default prefetch block size on sparc 139 return 64; // default prefetch block size on sparc