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comparison src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp @ 17917:63c5920a038d

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8042309: Some bugfixes for the ppc64 port. Reviewed-by: kvn
author goetz
date Fri, 02 May 2014 14:53:06 +0200
parents 67fa91961822
children ce8f6bb717c9
comparison
equal deleted inserted replaced
17916:34862ced4a87 17917:63c5920a038d
51 inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } 51 inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; }
52 inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; } 52 inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; }
53 53
54 inline jlong Atomic::load(volatile jlong* src) { return *src; } 54 inline jlong Atomic::load(volatile jlong* src) { return *src; }
55 55
56 /* 56 //
57 machine barrier instructions: 57 // machine barrier instructions:
58 58 //
59 - sync two-way memory barrier, aka fence 59 // - sync two-way memory barrier, aka fence
60 - lwsync orders Store|Store, 60 // - lwsync orders Store|Store,
61 Load|Store, 61 // Load|Store,
62 Load|Load, 62 // Load|Load,
63 but not Store|Load 63 // but not Store|Load
64 - eieio orders memory accesses for device memory (only) 64 // - eieio orders memory accesses for device memory (only)
65 - isync invalidates speculatively executed instructions 65 // - isync invalidates speculatively executed instructions
66 From the POWER ISA 2.06 documentation: 66 // From the POWER ISA 2.06 documentation:
67 "[...] an isync instruction prevents the execution of 67 // "[...] an isync instruction prevents the execution of
68 instructions following the isync until instructions 68 // instructions following the isync until instructions
69 preceding the isync have completed, [...]" 69 // preceding the isync have completed, [...]"
70 From IBM's AIX assembler reference: 70 // From IBM's AIX assembler reference:
71 "The isync [...] instructions causes the processor to 71 // "The isync [...] instructions causes the processor to
72 refetch any instructions that might have been fetched 72 // refetch any instructions that might have been fetched
73 prior to the isync instruction. The instruction isync 73 // prior to the isync instruction. The instruction isync
74 causes the processor to wait for all previous instructions 74 // causes the processor to wait for all previous instructions
75 to complete. Then any instructions already fetched are 75 // to complete. Then any instructions already fetched are
76 discarded and instruction processing continues in the 76 // discarded and instruction processing continues in the
77 environment established by the previous instructions." 77 // environment established by the previous instructions."
78 78 //
79 semantic barrier instructions: 79 // semantic barrier instructions:
80 (as defined in orderAccess.hpp) 80 // (as defined in orderAccess.hpp)
81 81 //
82 - release orders Store|Store, (maps to lwsync) 82 // - release orders Store|Store, (maps to lwsync)
83 Load|Store 83 // Load|Store
84 - acquire orders Load|Store, (maps to lwsync) 84 // - acquire orders Load|Store, (maps to lwsync)
85 Load|Load 85 // Load|Load
86 - fence orders Store|Store, (maps to sync) 86 // - fence orders Store|Store, (maps to sync)
87 Load|Store, 87 // Load|Store,
88 Load|Load, 88 // Load|Load,
89 Store|Load 89 // Store|Load
90 */ 90 //
91 91
92 #define strasm_sync "\n sync \n" 92 #define strasm_sync "\n sync \n"
93 #define strasm_lwsync "\n lwsync \n" 93 #define strasm_lwsync "\n lwsync \n"
94 #define strasm_isync "\n isync \n" 94 #define strasm_isync "\n isync \n"
95 #define strasm_release strasm_lwsync 95 #define strasm_release strasm_lwsync