Mercurial > hg > graal-jvmci-8
comparison src/cpu/sparc/vm/sparc.ad @ 4114:6729bbc1fcd6
7003454: order constants in constant table by number of references in code
Reviewed-by: kvn, never, bdelsart
author | twisti |
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date | Wed, 16 Nov 2011 01:39:50 -0800 |
parents | d8cb48376797 |
children | db2e64ca2d5a |
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4113:8c57262447d3 | 4114:6729bbc1fcd6 |
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564 else | 564 else |
565 klass_load_size = 3*BytesPerInstWord; | 565 klass_load_size = 3*BytesPerInstWord; |
566 } else { | 566 } else { |
567 klass_load_size = 1*BytesPerInstWord; | 567 klass_load_size = 1*BytesPerInstWord; |
568 } | 568 } |
569 if( Assembler::is_simm13(v_off) ) { | 569 if (Assembler::is_simm13(v_off)) { |
570 return klass_load_size + | 570 return klass_load_size + |
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr | 571 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
572 NativeCall::instruction_size); // call; delay slot | 572 NativeCall::instruction_size); // call; delay slot |
573 } else { | 573 } else { |
574 return klass_load_size + | 574 return klass_load_size + |
1017 void emit_lo(CodeBuffer &cbuf, int val) { } | 1017 void emit_lo(CodeBuffer &cbuf, int val) { } |
1018 void emit_hi(CodeBuffer &cbuf, int val) { } | 1018 void emit_hi(CodeBuffer &cbuf, int val) { } |
1019 | 1019 |
1020 | 1020 |
1021 //============================================================================= | 1021 //============================================================================= |
1022 const bool Matcher::constant_table_absolute_addressing = false; | |
1023 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | 1022 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; |
1023 | |
1024 int Compile::ConstantTable::calculate_table_base_offset() const { | |
1025 if (UseRDPCForConstantTableBase) { | |
1026 // The table base offset might be less but then it fits into | |
1027 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). | |
1028 return Assembler::min_simm13(); | |
1029 } else { | |
1030 int offset = -(size() / 2); | |
1031 if (!Assembler::is_simm13(offset)) { | |
1032 offset = Assembler::min_simm13(); | |
1033 } | |
1034 return offset; | |
1035 } | |
1036 } | |
1024 | 1037 |
1025 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | 1038 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
1026 Compile* C = ra_->C; | 1039 Compile* C = ra_->C; |
1027 Compile::ConstantTable& constant_table = C->constant_table(); | 1040 Compile::ConstantTable& constant_table = C->constant_table(); |
1028 MacroAssembler _masm(&cbuf); | 1041 MacroAssembler _masm(&cbuf); |
1029 | 1042 |
1030 Register r = as_Register(ra_->get_encode(this)); | 1043 Register r = as_Register(ra_->get_encode(this)); |
1031 CodeSection* cs = __ code()->consts(); | 1044 CodeSection* consts_section = __ code()->consts(); |
1032 int consts_size = cs->align_at_start(cs->size()); | 1045 int consts_size = consts_section->align_at_start(consts_section->size()); |
1046 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
1033 | 1047 |
1034 if (UseRDPCForConstantTableBase) { | 1048 if (UseRDPCForConstantTableBase) { |
1035 // For the following RDPC logic to work correctly the consts | 1049 // For the following RDPC logic to work correctly the consts |
1036 // section must be allocated right before the insts section. This | 1050 // section must be allocated right before the insts section. This |
1037 // assert checks for that. The layout and the SECT_* constants | 1051 // assert checks for that. The layout and the SECT_* constants |
1038 // are defined in src/share/vm/asm/codeBuffer.hpp. | 1052 // are defined in src/share/vm/asm/codeBuffer.hpp. |
1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | 1053 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); |
1040 int offset = __ offset(); | 1054 int insts_offset = __ offset(); |
1055 | |
1056 // Layout: | |
1057 // | |
1058 // |----------- consts section ------------|----------- insts section -----------... | |
1059 // |------ constant table -----|- padding -|------------------x---- | |
1060 // \ current PC (RDPC instruction) | |
1061 // |<------------- consts_size ----------->|<- insts_offset ->| | |
1062 // \ table base | |
1063 // The table base offset is later added to the load displacement | |
1064 // so it has to be negative. | |
1065 int table_base_offset = -(consts_size + insts_offset); | |
1041 int disp; | 1066 int disp; |
1042 | 1067 |
1043 // If the displacement from the current PC to the constant table | 1068 // If the displacement from the current PC to the constant table |
1044 // base fits into simm13 we set the constant table base to the | 1069 // base fits into simm13 we set the constant table base to the |
1045 // current PC. | 1070 // current PC. |
1046 if (__ is_simm13(-(consts_size + offset))) { | 1071 if (Assembler::is_simm13(table_base_offset)) { |
1047 constant_table.set_table_base_offset(-(consts_size + offset)); | 1072 constant_table.set_table_base_offset(table_base_offset); |
1048 disp = 0; | 1073 disp = 0; |
1049 } else { | 1074 } else { |
1050 // If the offset of the top constant (last entry in the table) | 1075 // Otherwise we set the constant table base offset to the |
1051 // fits into simm13 we set the constant table base to the actual | 1076 // maximum negative displacement of load instructions to keep |
1052 // table base. | 1077 // the disp as small as possible: |
1053 if (__ is_simm13(constant_table.top_offset())) { | 1078 // |
1054 constant_table.set_table_base_offset(0); | 1079 // |<------------- consts_size ----------->|<- insts_offset ->| |
1055 disp = consts_size + offset; | 1080 // |<--------- min_simm13 --------->|<-------- disp --------->| |
1056 } else { | 1081 // \ table base |
1057 // Otherwise we set the constant table base in the middle of the | 1082 table_base_offset = Assembler::min_simm13(); |
1058 // constant table. | 1083 constant_table.set_table_base_offset(table_base_offset); |
1059 int half_consts_size = consts_size / 2; | 1084 disp = (consts_size + insts_offset) + table_base_offset; |
1060 assert(half_consts_size * 2 == consts_size, "sanity"); | |
1061 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
1062 disp = half_consts_size + offset; | |
1063 } | |
1064 } | 1085 } |
1065 | 1086 |
1066 __ rdpc(r); | 1087 __ rdpc(r); |
1067 | 1088 |
1068 if (disp != 0) { | 1089 if (disp != 0) { |
1070 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | 1091 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); |
1071 } | 1092 } |
1072 } | 1093 } |
1073 else { | 1094 else { |
1074 // Materialize the constant table base. | 1095 // Materialize the constant table base. |
1075 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | 1096 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); |
1076 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
1077 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | 1097 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); |
1078 AddressLiteral base(baseaddr, rspec); | 1098 AddressLiteral base(baseaddr, rspec); |
1079 __ set(base, r); | 1099 __ set(base, r); |
1080 } | 1100 } |
1081 } | 1101 } |
1167 __ sethi(-framesize & ~0x3ff, G3); | 1187 __ sethi(-framesize & ~0x3ff, G3); |
1168 __ add(G3, -framesize & 0x3ff, G3); | 1188 __ add(G3, -framesize & 0x3ff, G3); |
1169 __ save(SP, G3, SP); | 1189 __ save(SP, G3, SP); |
1170 } | 1190 } |
1171 C->set_frame_complete( __ offset() ); | 1191 C->set_frame_complete( __ offset() ); |
1192 | |
1193 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { | |
1194 // NOTE: We set the table base offset here because users might be | |
1195 // emitted before MachConstantBaseNode. | |
1196 Compile::ConstantTable& constant_table = C->constant_table(); | |
1197 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); | |
1198 } | |
1172 } | 1199 } |
1173 | 1200 |
1174 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | 1201 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { |
1175 return MachNode::size(ra_); | 1202 return MachNode::size(ra_); |
1176 } | 1203 } |
1841 // NOTE: If the platform does not provide any short branch variants, then | 1868 // NOTE: If the platform does not provide any short branch variants, then |
1842 // this method should return false for offset 0. | 1869 // this method should return false for offset 0. |
1843 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { | 1870 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1844 // The passed offset is relative to address of the branch. | 1871 // The passed offset is relative to address of the branch. |
1845 // Don't need to adjust the offset. | 1872 // Don't need to adjust the offset. |
1846 return UseCBCond && Assembler::is_simm(offset, 12); | 1873 return UseCBCond && Assembler::is_simm12(offset); |
1847 } | 1874 } |
1848 | 1875 |
1849 const bool Matcher::isSimpleConstant64(jlong value) { | 1876 const bool Matcher::isSimpleConstant64(jlong value) { |
1850 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | 1877 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. |
1851 // Depends on optimizations in MacroAssembler::setx. | 1878 // Depends on optimizations in MacroAssembler::setx. |
2070 emit_form3_mem_reg(cbuf, this, $primary, -1, | 2097 emit_form3_mem_reg(cbuf, this, $primary, -1, |
2071 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); | 2098 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
2072 %} | 2099 %} |
2073 | 2100 |
2074 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | 2101 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ |
2075 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | 2102 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
2076 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | 2103 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
2077 guarantee($mem$$index == R_G0_enc, "double index?"); | 2104 guarantee($mem$$index == R_G0_enc, "double index?"); |
2078 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); | 2105 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
2079 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); | 2106 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
2080 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); | 2107 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
2081 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | 2108 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); |
2082 %} | 2109 %} |
2083 | 2110 |
2084 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | 2111 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ |
2085 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | 2112 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); |
2086 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | 2113 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); |
2087 guarantee($mem$$index == R_G0_enc, "double index?"); | 2114 guarantee($mem$$index == R_G0_enc, "double index?"); |
2088 // Load long with 2 instructions | 2115 // Load long with 2 instructions |
2089 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); | 2116 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
2090 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); | 2117 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
2091 %} | 2118 %} |
2561 } else { | 2588 } else { |
2562 klass_load_size = 1*BytesPerInstWord; | 2589 klass_load_size = 1*BytesPerInstWord; |
2563 } | 2590 } |
2564 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | 2591 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2565 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | 2592 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); |
2566 if( __ is_simm13(v_off) ) { | 2593 if (Assembler::is_simm13(v_off)) { |
2567 __ ld_ptr(G3, v_off, G5_method); | 2594 __ ld_ptr(G3, v_off, G5_method); |
2568 } else { | 2595 } else { |
2569 // Generate 2 instructions | 2596 // Generate 2 instructions |
2570 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | 2597 __ Assembler::sethi(v_off & ~0x3ff, G5_method); |
2571 __ or3(G5_method, v_off & 0x3ff, G5_method); | 2598 __ or3(G5_method, v_off & 0x3ff, G5_method); |
3334 interface(CONST_INTER); | 3361 interface(CONST_INTER); |
3335 %} | 3362 %} |
3336 | 3363 |
3337 // Integer Immediate: 8-bit | 3364 // Integer Immediate: 8-bit |
3338 operand immI8() %{ | 3365 operand immI8() %{ |
3339 predicate(Assembler::is_simm(n->get_int(), 8)); | 3366 predicate(Assembler::is_simm8(n->get_int())); |
3340 match(ConI); | 3367 match(ConI); |
3341 op_cost(0); | 3368 op_cost(0); |
3342 format %{ %} | 3369 format %{ %} |
3343 interface(CONST_INTER); | 3370 interface(CONST_INTER); |
3344 %} | 3371 %} |
3363 interface(CONST_INTER); | 3390 interface(CONST_INTER); |
3364 %} | 3391 %} |
3365 | 3392 |
3366 // Integer Immediate: 16-bit | 3393 // Integer Immediate: 16-bit |
3367 operand immI16() %{ | 3394 operand immI16() %{ |
3368 predicate(Assembler::is_simm(n->get_int(), 16)); | 3395 predicate(Assembler::is_simm16(n->get_int())); |
3369 match(ConI); | 3396 match(ConI); |
3370 op_cost(0); | 3397 op_cost(0); |
3371 format %{ %} | 3398 format %{ %} |
3372 interface(CONST_INTER); | 3399 interface(CONST_INTER); |
3373 %} | 3400 %} |
3391 interface(CONST_INTER); | 3418 interface(CONST_INTER); |
3392 %} | 3419 %} |
3393 | 3420 |
3394 // Integer Immediate: 11-bit | 3421 // Integer Immediate: 11-bit |
3395 operand immI11() %{ | 3422 operand immI11() %{ |
3396 predicate(Assembler::is_simm(n->get_int(),11)); | 3423 predicate(Assembler::is_simm11(n->get_int())); |
3397 match(ConI); | 3424 match(ConI); |
3398 op_cost(0); | 3425 op_cost(0); |
3399 format %{ %} | 3426 format %{ %} |
3400 interface(CONST_INTER); | 3427 interface(CONST_INTER); |
3401 %} | 3428 %} |
3402 | 3429 |
3403 // Integer Immediate: 5-bit | 3430 // Integer Immediate: 5-bit |
3404 operand immI5() %{ | 3431 operand immI5() %{ |
3405 predicate(Assembler::is_simm(n->get_int(), 5)); | 3432 predicate(Assembler::is_simm5(n->get_int())); |
3406 match(ConI); | 3433 match(ConI); |
3407 op_cost(0); | 3434 op_cost(0); |
3408 format %{ %} | 3435 format %{ %} |
3409 interface(CONST_INTER); | 3436 interface(CONST_INTER); |
3410 %} | 3437 %} |
3632 interface(CONST_INTER); | 3659 interface(CONST_INTER); |
3633 %} | 3660 %} |
3634 | 3661 |
3635 // Integer Immediate: 5-bit | 3662 // Integer Immediate: 5-bit |
3636 operand immL5() %{ | 3663 operand immL5() %{ |
3637 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5)); | 3664 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); |
3638 match(ConL); | 3665 match(ConL); |
3639 op_cost(0); | 3666 op_cost(0); |
3640 format %{ %} | 3667 format %{ %} |
3641 interface(CONST_INTER); | 3668 interface(CONST_INTER); |
3642 %} | 3669 %} |
9249 | 9276 |
9250 ins_cost(350); | 9277 ins_cost(350); |
9251 | 9278 |
9252 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" | 9279 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
9253 "LD [O7 + $switch_val], O7\n\t" | 9280 "LD [O7 + $switch_val], O7\n\t" |
9254 "JUMP O7" | 9281 "JUMP O7" %} |
9255 %} | |
9256 ins_encode %{ | 9282 ins_encode %{ |
9257 // Calculate table address into a register. | 9283 // Calculate table address into a register. |
9258 Register table_reg; | 9284 Register table_reg; |
9259 Register label_reg = O7; | 9285 Register label_reg = O7; |
9260 if (constant_offset() == 0) { | 9286 // If we are calculating the size of this instruction don't trust |
9287 // zero offsets because they might change when | |
9288 // MachConstantBaseNode decides to optimize the constant table | |
9289 // base. | |
9290 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { | |
9261 table_reg = $constanttablebase; | 9291 table_reg = $constanttablebase; |
9262 } else { | 9292 } else { |
9263 table_reg = O7; | 9293 table_reg = O7; |
9264 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); | 9294 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
9265 __ add($constanttablebase, con_offset, table_reg); | 9295 __ add($constanttablebase, con_offset, table_reg); |