Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/c1_LinearScan_x86.cpp @ 6084:6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
Summary: use x87 instructions to implement exp() and pow() in interpreter/c1/c2.
Reviewed-by: kvn, never, twisti
author | roland |
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date | Tue, 15 May 2012 10:10:23 +0200 |
parents | f95d63e2154a |
children | b9a9ed0f8eeb |
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6057:8f972594effc | 6084:6759698e3140 |
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688 break; | 688 break; |
689 } | 689 } |
690 | 690 |
691 case lir_mul_strictfp: | 691 case lir_mul_strictfp: |
692 case lir_div_strictfp: { | 692 case lir_div_strictfp: { |
693 assert(op2->tmp_opr()->is_fpu_register(), "strict operations need temporary fpu stack slot"); | 693 assert(op2->tmp1_opr()->is_fpu_register(), "strict operations need temporary fpu stack slot"); |
694 insert_free_if_dead(op2->tmp_opr()); | 694 insert_free_if_dead(op2->tmp1_opr()); |
695 assert(sim()->stack_size() <= 7, "at least one stack slot must be free"); | 695 assert(sim()->stack_size() <= 7, "at least one stack slot must be free"); |
696 // fall-through: continue with the normal handling of lir_mul and lir_div | 696 // fall-through: continue with the normal handling of lir_mul and lir_div |
697 } | 697 } |
698 case lir_add: | 698 case lir_add: |
699 case lir_sub: | 699 case lir_sub: |
785 break; | 785 break; |
786 } | 786 } |
787 | 787 |
788 case lir_log: | 788 case lir_log: |
789 case lir_log10: { | 789 case lir_log10: { |
790 // log and log10 needs one temporary fpu stack slot, so there is ontemporary | 790 // log and log10 need one temporary fpu stack slot, so |
791 // registers stored in temp of the operation. | 791 // there is one temporary registers stored in temp of the |
792 // the stack allocator must guarantee that the stack slots are really free, | 792 // operation. the stack allocator must guarantee that the stack |
793 // otherwise there might be a stack overflow. | 793 // slots are really free, otherwise there might be a stack |
794 // overflow. | |
794 assert(right->is_illegal(), "must be"); | 795 assert(right->is_illegal(), "must be"); |
795 assert(left->is_fpu_register(), "must be"); | 796 assert(left->is_fpu_register(), "must be"); |
796 assert(res->is_fpu_register(), "must be"); | 797 assert(res->is_fpu_register(), "must be"); |
797 assert(op2->tmp_opr()->is_fpu_register(), "must be"); | 798 assert(op2->tmp1_opr()->is_fpu_register(), "must be"); |
798 | 799 |
799 insert_free_if_dead(op2->tmp_opr()); | 800 insert_free_if_dead(op2->tmp1_opr()); |
800 insert_free_if_dead(res, left); | 801 insert_free_if_dead(res, left); |
801 insert_exchange(left); | 802 insert_exchange(left); |
802 do_rename(left, res); | 803 do_rename(left, res); |
803 | 804 |
804 new_left = to_fpu_stack_top(res); | 805 new_left = to_fpu_stack_top(res); |
810 } | 811 } |
811 | 812 |
812 | 813 |
813 case lir_tan: | 814 case lir_tan: |
814 case lir_sin: | 815 case lir_sin: |
815 case lir_cos: { | 816 case lir_cos: |
816 // sin and cos need two temporary fpu stack slots, so there are two temporary | 817 case lir_exp: { |
818 // sin, cos and exp need two temporary fpu stack slots, so there are two temporary | |
817 // registers (stored in right and temp of the operation). | 819 // registers (stored in right and temp of the operation). |
818 // the stack allocator must guarantee that the stack slots are really free, | 820 // the stack allocator must guarantee that the stack slots are really free, |
819 // otherwise there might be a stack overflow. | 821 // otherwise there might be a stack overflow. |
820 assert(left->is_fpu_register(), "must be"); | 822 assert(left->is_fpu_register(), "must be"); |
821 assert(res->is_fpu_register(), "must be"); | 823 assert(res->is_fpu_register(), "must be"); |
822 // assert(left->is_last_use(), "old value gets destroyed"); | 824 // assert(left->is_last_use(), "old value gets destroyed"); |
823 assert(right->is_fpu_register(), "right is used as the first temporary register"); | 825 assert(right->is_fpu_register(), "right is used as the first temporary register"); |
824 assert(op2->tmp_opr()->is_fpu_register(), "temp is used as the second temporary register"); | 826 assert(op2->tmp1_opr()->is_fpu_register(), "temp is used as the second temporary register"); |
825 assert(fpu_num(left) != fpu_num(right) && fpu_num(right) != fpu_num(op2->tmp_opr()) && fpu_num(op2->tmp_opr()) != fpu_num(res), "need distinct temp registers"); | 827 assert(fpu_num(left) != fpu_num(right) && fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers"); |
826 | 828 |
827 insert_free_if_dead(right); | 829 insert_free_if_dead(right); |
828 insert_free_if_dead(op2->tmp_opr()); | 830 insert_free_if_dead(op2->tmp1_opr()); |
829 | 831 |
830 insert_free_if_dead(res, left); | 832 insert_free_if_dead(res, left); |
831 insert_exchange(left); | 833 insert_exchange(left); |
832 do_rename(left, res); | 834 do_rename(left, res); |
833 | 835 |
834 new_left = to_fpu_stack_top(res); | 836 new_left = to_fpu_stack_top(res); |
835 new_res = new_left; | 837 new_res = new_left; |
836 | 838 |
837 op2->set_fpu_stack_size(sim()->stack_size()); | 839 op2->set_fpu_stack_size(sim()->stack_size()); |
838 assert(sim()->stack_size() <= 6, "at least two stack slots must be free"); | 840 assert(sim()->stack_size() <= 6, "at least two stack slots must be free"); |
841 break; | |
842 } | |
843 | |
844 case lir_pow: { | |
845 // pow needs two temporary fpu stack slots, so there are two temporary | |
846 // registers (stored in tmp1 and tmp2 of the operation). | |
847 // the stack allocator must guarantee that the stack slots are really free, | |
848 // otherwise there might be a stack overflow. | |
849 assert(left->is_fpu_register(), "must be"); | |
850 assert(right->is_fpu_register(), "must be"); | |
851 assert(res->is_fpu_register(), "must be"); | |
852 | |
853 assert(op2->tmp1_opr()->is_fpu_register(), "tmp1 is the first temporary register"); | |
854 assert(op2->tmp2_opr()->is_fpu_register(), "tmp2 is the second temporary register"); | |
855 assert(fpu_num(left) != fpu_num(right) && fpu_num(left) != fpu_num(op2->tmp1_opr()) && fpu_num(left) != fpu_num(op2->tmp2_opr()) && fpu_num(left) != fpu_num(res), "need distinct temp registers"); | |
856 assert(fpu_num(right) != fpu_num(op2->tmp1_opr()) && fpu_num(right) != fpu_num(op2->tmp2_opr()) && fpu_num(right) != fpu_num(res), "need distinct temp registers"); | |
857 assert(fpu_num(op2->tmp1_opr()) != fpu_num(op2->tmp2_opr()) && fpu_num(op2->tmp1_opr()) != fpu_num(res), "need distinct temp registers"); | |
858 assert(fpu_num(op2->tmp2_opr()) != fpu_num(res), "need distinct temp registers"); | |
859 | |
860 insert_free_if_dead(op2->tmp1_opr()); | |
861 insert_free_if_dead(op2->tmp2_opr()); | |
862 | |
863 // Must bring both operands to top of stack with following operand ordering: | |
864 // * fpu stack before pow: ... right left | |
865 // * fpu stack after pow: ... left | |
866 | |
867 insert_free_if_dead(res, right); | |
868 | |
869 if (tos_offset(right) != 1) { | |
870 insert_exchange(right); | |
871 insert_exchange(1); | |
872 } | |
873 insert_exchange(left); | |
874 assert(tos_offset(right) == 1, "check"); | |
875 assert(tos_offset(left) == 0, "check"); | |
876 | |
877 new_left = to_fpu_stack_top(left); | |
878 new_right = to_fpu_stack(right); | |
879 | |
880 op2->set_fpu_stack_size(sim()->stack_size()); | |
881 assert(sim()->stack_size() <= 6, "at least two stack slots must be free"); | |
882 | |
883 sim()->pop(); | |
884 | |
885 do_rename(right, res); | |
886 | |
887 new_res = to_fpu_stack_top(res); | |
839 break; | 888 break; |
840 } | 889 } |
841 | 890 |
842 default: { | 891 default: { |
843 assert(false, "missed a fpu-operation"); | 892 assert(false, "missed a fpu-operation"); |