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comparison src/share/vm/opto/mulnode.cpp @ 6891:67f4c477c9ab

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8000805: JMM issue: short loads are non-atomic Summary: perform transforms during IGVN phase when Load has a single user. Reviewed-by: jrose, kvn, twisti
author vlivanov
date Mon, 22 Oct 2012 11:44:30 -0700
parents d804e148cff8
children 2113136690bc
comparison
equal deleted inserted replaced
6890:aaeb9add1ab3 6891:67f4c477c9ab
477 if( lop == Op_LoadUS && 477 if( lop == Op_LoadUS &&
478 (mask & 0xFFFF0000) ) // Can we make a smaller mask? 478 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
479 return new (phase->C) AndINode(load,phase->intcon(mask&0xFFFF)); 479 return new (phase->C) AndINode(load,phase->intcon(mask&0xFFFF));
480 480
481 // Masking bits off of a Short? Loading a Character does some masking 481 // Masking bits off of a Short? Loading a Character does some masking
482 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) { 482 if (can_reshape &&
483 Node *ldus = new (phase->C) LoadUSNode(load->in(MemNode::Control), 483 load->outcnt() == 1 && load->unique_out() == this) {
484 load->in(MemNode::Memory), 484 if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) {
485 load->in(MemNode::Address), 485 Node *ldus = new (phase->C) LoadUSNode(load->in(MemNode::Control),
486 load->adr_type()); 486 load->in(MemNode::Memory),
487 ldus = phase->transform(ldus); 487 load->in(MemNode::Address),
488 return new (phase->C) AndINode(ldus, phase->intcon(mask & 0xFFFF)); 488 load->adr_type());
489 } 489 ldus = phase->transform(ldus);
490 490 return new (phase->C) AndINode(ldus, phase->intcon(mask & 0xFFFF));
491 // Masking sign bits off of a Byte? Do an unsigned byte load plus 491 }
492 // an and. 492
493 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) { 493 // Masking sign bits off of a Byte? Do an unsigned byte load plus
494 Node* ldub = new (phase->C) LoadUBNode(load->in(MemNode::Control), 494 // an and.
495 load->in(MemNode::Memory), 495 if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) {
496 load->in(MemNode::Address), 496 Node* ldub = new (phase->C) LoadUBNode(load->in(MemNode::Control),
497 load->adr_type()); 497 load->in(MemNode::Memory),
498 ldub = phase->transform(ldub); 498 load->in(MemNode::Address),
499 return new (phase->C) AndINode(ldub, phase->intcon(mask)); 499 load->adr_type());
500 ldub = phase->transform(ldub);
501 return new (phase->C) AndINode(ldub, phase->intcon(mask));
502 }
500 } 503 }
501 504
502 // Masking off sign bits? Dont make them! 505 // Masking off sign bits? Dont make them!
503 if( lop == Op_RShiftI ) { 506 if( lop == Op_RShiftI ) {
504 const TypeInt *t12 = phase->type(load->in(2))->isa_int(); 507 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
921 // combined optimization requires Identity only return direct inputs. 924 // combined optimization requires Identity only return direct inputs.
922 set_req(1, ld); 925 set_req(1, ld);
923 set_req(2, phase->intcon(0)); 926 set_req(2, phase->intcon(0));
924 return this; 927 return this;
925 } 928 }
926 else if( ld->Opcode() == Op_LoadUS ) 929 else if( can_reshape &&
930 ld->Opcode() == Op_LoadUS &&
931 ld->outcnt() == 1 && ld->unique_out() == shl)
927 // Replace zero-extension-load with sign-extension-load 932 // Replace zero-extension-load with sign-extension-load
928 return new (phase->C) LoadSNode( ld->in(MemNode::Control), 933 return new (phase->C) LoadSNode( ld->in(MemNode::Control),
929 ld->in(MemNode::Memory), 934 ld->in(MemNode::Memory),
930 ld->in(MemNode::Address), 935 ld->in(MemNode::Address),
931 ld->adr_type()); 936 ld->adr_type());