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comparison src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp @ 14445:67fa91961822

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8029940: PPC64 (part 122): C2 compiler port Reviewed-by: kvn
author goetz
date Wed, 11 Dec 2013 00:06:11 +0100
parents ec28f9c041ff
children 63c5920a038d
comparison
equal deleted inserted replaced
14444:492e67693373 14445:67fa91961822
56 /* 56 /*
57 machine barrier instructions: 57 machine barrier instructions:
58 58
59 - sync two-way memory barrier, aka fence 59 - sync two-way memory barrier, aka fence
60 - lwsync orders Store|Store, 60 - lwsync orders Store|Store,
61 Load|Store, 61 Load|Store,
62 Load|Load, 62 Load|Load,
63 but not Store|Load 63 but not Store|Load
64 - eieio orders memory accesses for device memory (only) 64 - eieio orders memory accesses for device memory (only)
65 - isync invalidates speculatively executed instructions 65 - isync invalidates speculatively executed instructions
66 From the POWER ISA 2.06 documentation: 66 From the POWER ISA 2.06 documentation:
67 "[...] an isync instruction prevents the execution of 67 "[...] an isync instruction prevents the execution of
68 instructions following the isync until instructions 68 instructions following the isync until instructions
69 preceding the isync have completed, [...]" 69 preceding the isync have completed, [...]"
70 From IBM's AIX assembler reference: 70 From IBM's AIX assembler reference:
71 "The isync [...] instructions causes the processor to 71 "The isync [...] instructions causes the processor to
72 refetch any instructions that might have been fetched 72 refetch any instructions that might have been fetched
73 prior to the isync instruction. The instruction isync 73 prior to the isync instruction. The instruction isync
74 causes the processor to wait for all previous instructions 74 causes the processor to wait for all previous instructions
75 to complete. Then any instructions already fetched are 75 to complete. Then any instructions already fetched are
76 discarded and instruction processing continues in the 76 discarded and instruction processing continues in the
77 environment established by the previous instructions." 77 environment established by the previous instructions."
78 78
79 semantic barrier instructions: 79 semantic barrier instructions:
80 (as defined in orderAccess.hpp) 80 (as defined in orderAccess.hpp)
81 81
82 - release orders Store|Store, (maps to lwsync) 82 - release orders Store|Store, (maps to lwsync)
83 Load|Store 83 Load|Store
84 - acquire orders Load|Store, (maps to lwsync) 84 - acquire orders Load|Store, (maps to lwsync)
85 Load|Load 85 Load|Load
86 - fence orders Store|Store, (maps to sync) 86 - fence orders Store|Store, (maps to sync)
87 Load|Store, 87 Load|Store,
88 Load|Load, 88 Load|Load,
89 Store|Load 89 Store|Load
90 */ 90 */
91 91
92 #define strasm_sync "\n sync \n" 92 #define strasm_sync "\n sync \n"
93 #define strasm_lwsync "\n lwsync \n" 93 #define strasm_lwsync "\n lwsync \n"
94 #define strasm_isync "\n isync \n" 94 #define strasm_isync "\n isync \n"