Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/vm_version_x86.cpp @ 20804:7848fc12602b
Merge with jdk8u40-b25
author | Gilles Duboscq <gilles.m.duboscq@oracle.com> |
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date | Tue, 07 Apr 2015 14:58:49 +0200 |
parents | 52b4284cb496 e48395e6a91b |
children | 2e35a4ea22ac |
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20184:84105dcdb05b | 20804:7848fc12602b |
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491 // HT processor could be installed on a system which doesn't support HT. | 491 // HT processor could be installed on a system which doesn't support HT. |
492 _cpuFeatures &= ~CPU_HT; | 492 _cpuFeatures &= ~CPU_HT; |
493 } | 493 } |
494 | 494 |
495 char buf[256]; | 495 char buf[256]; |
496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", | 496 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
497 cores_per_cpu(), threads_per_core(), | 497 cores_per_cpu(), threads_per_core(), |
498 cpu_family(), _model, _stepping, | 498 cpu_family(), _model, _stepping, |
499 (supports_cmov() ? ", cmov" : ""), | 499 (supports_cmov() ? ", cmov" : ""), |
500 (supports_cmpxchg8() ? ", cx8" : ""), | 500 (supports_cmpxchg8() ? ", cx8" : ""), |
501 (supports_fxsr() ? ", fxsr" : ""), | 501 (supports_fxsr() ? ", fxsr" : ""), |
520 (supports_ht() ? ", ht": ""), | 520 (supports_ht() ? ", ht": ""), |
521 (supports_tsc() ? ", tsc": ""), | 521 (supports_tsc() ? ", tsc": ""), |
522 (supports_tscinv_bit() ? ", tscinvbit": ""), | 522 (supports_tscinv_bit() ? ", tscinvbit": ""), |
523 (supports_tscinv() ? ", tscinv": ""), | 523 (supports_tscinv() ? ", tscinv": ""), |
524 (supports_bmi1() ? ", bmi1" : ""), | 524 (supports_bmi1() ? ", bmi1" : ""), |
525 (supports_bmi2() ? ", bmi2" : "")); | 525 (supports_bmi2() ? ", bmi2" : ""), |
526 (supports_adx() ? ", adx" : "")); | |
526 _features_str = strdup(buf); | 527 _features_str = strdup(buf); |
527 | 528 |
528 // UseSSE is set to the smaller of what hardware supports and what | 529 // UseSSE is set to the smaller of what hardware supports and what |
529 // the command line requires. I.e., you cannot set UseSSE to 2 on | 530 // the command line requires. I.e., you cannot set UseSSE to 2 on |
530 // older Pentiums which do not support it. | 531 // older Pentiums which do not support it. |
566 if (!FLAG_IS_DEFAULT(UseCLMUL)) | 567 if (!FLAG_IS_DEFAULT(UseCLMUL)) |
567 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); | 568 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
568 FLAG_SET_DEFAULT(UseCLMUL, false); | 569 FLAG_SET_DEFAULT(UseCLMUL, false); |
569 } | 570 } |
570 | 571 |
571 if (UseCLMUL && (UseAVX > 0) && (UseSSE > 2)) { | 572 if (UseCLMUL && (UseSSE > 2)) { |
572 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { | 573 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
573 UseCRC32Intrinsics = true; | 574 UseCRC32Intrinsics = true; |
574 } | 575 } |
575 } else if (UseCRC32Intrinsics) { | 576 } else if (UseCRC32Intrinsics) { |
576 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) | 577 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
577 warning("CRC32 Intrinsics requires AVX and CLMUL instructions (not available on this CPU)"); | 578 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); |
578 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); | 579 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
579 } | 580 } |
580 | 581 |
581 // The AES intrinsic stubs require AES instruction support (of course) | 582 // The AES intrinsic stubs require AES instruction support (of course) |
582 // but also require sse3 mode for instructions it use. | 583 // but also require sse3 mode for instructions it use. |
586 } | 587 } |
587 } else if (UseAESIntrinsics) { | 588 } else if (UseAESIntrinsics) { |
588 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) | 589 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) |
589 warning("AES intrinsics are not available on this CPU"); | 590 warning("AES intrinsics are not available on this CPU"); |
590 FLAG_SET_DEFAULT(UseAESIntrinsics, false); | 591 FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
592 } | |
593 | |
594 if (UseSHA) { | |
595 warning("SHA instructions are not available on this CPU"); | |
596 FLAG_SET_DEFAULT(UseSHA, false); | |
597 } | |
598 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { | |
599 warning("SHA intrinsics are not available on this CPU"); | |
600 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); | |
601 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); | |
602 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); | |
591 } | 603 } |
592 | 604 |
593 // Adjust RTM (Restricted Transactional Memory) flags | 605 // Adjust RTM (Restricted Transactional Memory) flags |
594 if (!supports_rtm() && UseRTMLocking) { | 606 if (!supports_rtm() && UseRTMLocking) { |
595 // Can't continue because UseRTMLocking affects UseBiasedLocking flag | 607 // Can't continue because UseRTMLocking affects UseBiasedLocking flag |
599 vm_exit_during_initialization("RTM instructions are not available on this CPU"); | 611 vm_exit_during_initialization("RTM instructions are not available on this CPU"); |
600 } | 612 } |
601 | 613 |
602 #if INCLUDE_RTM_OPT | 614 #if INCLUDE_RTM_OPT |
603 if (UseRTMLocking) { | 615 if (UseRTMLocking) { |
616 if (is_intel_family_core()) { | |
617 if ((_model == CPU_MODEL_HASWELL_E3) || | |
618 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || | |
619 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) { | |
620 if (!UnlockExperimentalVMOptions) { | |
621 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); | |
622 } else { | |
623 warning("UseRTMLocking is only available as experimental option on this platform."); | |
624 } | |
625 } | |
626 } | |
604 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { | 627 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { |
605 // RTM locking should be used only for applications with | 628 // RTM locking should be used only for applications with |
606 // high lock contention. For now we do not use it by default. | 629 // high lock contention. For now we do not use it by default. |
607 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); | 630 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); |
608 } | 631 } |
673 tty->cr(); | 696 tty->cr(); |
674 } | 697 } |
675 } | 698 } |
676 #endif | 699 #endif |
677 } | 700 } |
678 #endif | 701 |
702 #ifdef _LP64 | |
703 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { | |
704 UseMultiplyToLenIntrinsic = true; | |
705 } | |
706 #else | |
707 if (UseMultiplyToLenIntrinsic) { | |
708 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { | |
709 warning("multiplyToLen intrinsic is not available in 32-bit VM"); | |
710 } | |
711 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); | |
712 } | |
713 #endif | |
714 #endif // COMPILER2 | |
679 | 715 |
680 // On new cpus instructions which update whole XMM register should be used | 716 // On new cpus instructions which update whole XMM register should be used |
681 // to prevent partial register stall due to dependencies on high half. | 717 // to prevent partial register stall due to dependencies on high half. |
682 // | 718 // |
683 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | 719 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
801 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | 837 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
802 UseSSE42Intrinsics = true; | 838 UseSSE42Intrinsics = true; |
803 } | 839 } |
804 } | 840 } |
805 } | 841 } |
842 if ((cpu_family() == 0x06) && | |
843 ((extended_cpu_model() == 0x36) || // Centerton | |
844 (extended_cpu_model() == 0x37) || // Silvermont | |
845 (extended_cpu_model() == 0x4D))) { | |
846 #ifdef COMPILER2 | |
847 if (FLAG_IS_DEFAULT(OptoScheduling)) { | |
848 OptoScheduling = true; | |
849 } | |
850 #endif | |
851 if (supports_sse4_2()) { // Silvermont | |
852 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { | |
853 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
854 } | |
855 } | |
856 } | |
857 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { | |
858 AllocatePrefetchInstr = 3; | |
859 } | |
806 } | 860 } |
807 | 861 |
808 // Use count leading zeros count instruction if available. | 862 // Use count leading zeros count instruction if available. |
809 if (supports_lzcnt()) { | 863 if (supports_lzcnt()) { |
810 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { | 864 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
813 } else if (UseCountLeadingZerosInstruction) { | 867 } else if (UseCountLeadingZerosInstruction) { |
814 warning("lzcnt instruction is not available on this CPU"); | 868 warning("lzcnt instruction is not available on this CPU"); |
815 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); | 869 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
816 } | 870 } |
817 | 871 |
818 if (supports_bmi1()) { | |
819 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { | |
820 UseBMI1Instructions = true; | |
821 } | |
822 } else if (UseBMI1Instructions) { | |
823 warning("BMI1 instructions are not available on this CPU"); | |
824 FLAG_SET_DEFAULT(UseBMI1Instructions, false); | |
825 } | |
826 | |
827 // Use count trailing zeros instruction if available | 872 // Use count trailing zeros instruction if available |
828 if (supports_bmi1()) { | 873 if (supports_bmi1()) { |
874 // tzcnt does not require VEX prefix | |
829 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { | 875 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
830 UseCountTrailingZerosInstruction = UseBMI1Instructions; | 876 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
877 // Don't use tzcnt if BMI1 is switched off on command line. | |
878 UseCountTrailingZerosInstruction = false; | |
879 } else { | |
880 UseCountTrailingZerosInstruction = true; | |
881 } | |
831 } | 882 } |
832 } else if (UseCountTrailingZerosInstruction) { | 883 } else if (UseCountTrailingZerosInstruction) { |
833 warning("tzcnt instruction is not available on this CPU"); | 884 warning("tzcnt instruction is not available on this CPU"); |
834 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); | 885 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
886 } | |
887 | |
888 // BMI instructions (except tzcnt) use an encoding with VEX prefix. | |
889 // VEX prefix is generated only when AVX > 0. | |
890 if (supports_bmi1() && supports_avx()) { | |
891 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { | |
892 UseBMI1Instructions = true; | |
893 } | |
894 } else if (UseBMI1Instructions) { | |
895 warning("BMI1 instructions are not available on this CPU (AVX is also required)"); | |
896 FLAG_SET_DEFAULT(UseBMI1Instructions, false); | |
897 } | |
898 | |
899 if (supports_bmi2() && supports_avx()) { | |
900 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { | |
901 UseBMI2Instructions = true; | |
902 } | |
903 } else if (UseBMI2Instructions) { | |
904 warning("BMI2 instructions are not available on this CPU (AVX is also required)"); | |
905 FLAG_SET_DEFAULT(UseBMI2Instructions, false); | |
835 } | 906 } |
836 | 907 |
837 // Use population count instruction if available. | 908 // Use population count instruction if available. |
838 if (supports_popcnt()) { | 909 if (supports_popcnt()) { |
839 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { | 910 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
888 AllocateInstancePrefetchLines = 1; | 959 AllocateInstancePrefetchLines = 1; |
889 | 960 |
890 AllocatePrefetchDistance = allocate_prefetch_distance(); | 961 AllocatePrefetchDistance = allocate_prefetch_distance(); |
891 AllocatePrefetchStyle = allocate_prefetch_style(); | 962 AllocatePrefetchStyle = allocate_prefetch_style(); |
892 | 963 |
893 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { | 964 if (is_intel() && cpu_family() == 6 && supports_sse3()) { |
894 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | 965 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core |
895 #ifdef _LP64 | 966 #ifdef _LP64 |
896 AllocatePrefetchDistance = 384; | 967 AllocatePrefetchDistance = 384; |
897 #else | 968 #else |
898 AllocatePrefetchDistance = 320; | 969 AllocatePrefetchDistance = 320; |
899 #endif | 970 #endif |
900 } | 971 } |
901 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | 972 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
902 AllocatePrefetchDistance = 192; | 973 AllocatePrefetchDistance = 192; |
903 AllocatePrefetchLines = 4; | 974 AllocatePrefetchLines = 4; |
975 } | |
904 #ifdef COMPILER2 | 976 #ifdef COMPILER2 |
905 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { | 977 if (supports_sse4_2()) { |
978 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { | |
906 FLAG_SET_DEFAULT(UseFPUForSpilling, true); | 979 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
907 } | 980 } |
908 #endif | 981 } |
909 } | 982 #endif |
910 } | 983 } |
911 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | 984 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
912 | 985 |
913 #ifdef _LP64 | 986 #ifdef _LP64 |
914 // Prefetch settings | 987 // Prefetch settings |