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comparison src/share/vm/utilities/globalDefinitions.hpp @ 14460:8a9bb7821e28

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Merge
author kvn
date Wed, 19 Feb 2014 12:08:49 -0800
parents 63a4eb8bcd23 c6d7e7406136
children d8041d695d19
comparison
equal deleted inserted replaced
14360:e8ef156f0bc9 14460:8a9bb7821e28
36 # include "utilities/globalDefinitions_visCPP.hpp" 36 # include "utilities/globalDefinitions_visCPP.hpp"
37 #endif 37 #endif
38 #ifdef TARGET_COMPILER_sparcWorks 38 #ifdef TARGET_COMPILER_sparcWorks
39 # include "utilities/globalDefinitions_sparcWorks.hpp" 39 # include "utilities/globalDefinitions_sparcWorks.hpp"
40 #endif 40 #endif
41 #ifdef TARGET_COMPILER_xlc
42 # include "utilities/globalDefinitions_xlc.hpp"
43 #endif
41 44
42 #include "utilities/macros.hpp" 45 #include "utilities/macros.hpp"
43 46
44 // This file holds all globally used constants & types, class (forward) 47 // This file holds all globally used constants & types, class (forward)
45 // declarations and a few frequently used utility functions. 48 // declarations and a few frequently used utility functions.
391 * the platform specific globalDefinitions (above) 394 * the platform specific globalDefinitions (above)
392 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0 395 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0
393 */ 396 */
394 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 397 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED
395 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 398 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1
399 #endif
400
401 // To assure the IRIW property on processors that are not multiple copy
402 // atomic, sync instructions must be issued between volatile reads to
403 // assure their ordering, instead of after volatile stores.
404 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
405 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
406 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
407 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
408 #else
409 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
396 #endif 410 #endif
397 411
398 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. 412 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348.
399 // Note: this value must be a power of 2 413 // Note: this value must be a power of 2
400 414