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comparison src/cpu/x86/vm/vm_version_x86.cpp @ 6794:8ae8f9dd7099

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7199010: incorrect vector alignment Summary: Fixed vectors alignment when several arrays are accessed in one loop. Reviewed-by: roland, twisti
author kvn
date Wed, 19 Sep 2012 16:50:26 -0700
parents 2c368ea3e844
children 7eca5de9e0b6
comparison
equal deleted inserted replaced
6793:9d89c76b0505 6794:8ae8f9dd7099
560 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW 560 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
561 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 561 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
562 AllocatePrefetchInstr = 3; 562 AllocatePrefetchInstr = 3;
563 } 563 }
564 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy 564 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
565 if( supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { 565 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
566 UseXMMForArrayCopy = true; 566 UseXMMForArrayCopy = true;
567 } 567 }
568 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { 568 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
569 UseUnalignedLoadStores = true; 569 UseUnalignedLoadStores = true;
570 } 570 }
571 } 571 }
572 572
573 #ifdef COMPILER2 573 #ifdef COMPILER2
610 // generated NOP instructions. 11 is the largest size of one 610 // generated NOP instructions. 11 is the largest size of one
611 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 611 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
612 MaxLoopPad = 11; 612 MaxLoopPad = 11;
613 } 613 }
614 #endif // COMPILER2 614 #endif // COMPILER2
615 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { 615 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
616 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus 616 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
617 } 617 }
618 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus 618 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
619 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { 619 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
620 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 620 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
621 } 621 }
622 } 622 }
623 if( supports_sse4_2() && UseSSE >= 4 ) { 623 if (supports_sse4_2() && UseSSE >= 4) {
624 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 624 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
625 UseSSE42Intrinsics = true; 625 UseSSE42Intrinsics = true;
626 } 626 }
627 } 627 }
628 } 628 }
629 } 629 }
635 } 635 }
636 } else if (UsePopCountInstruction) { 636 } else if (UsePopCountInstruction) {
637 warning("POPCNT instruction is not available on this CPU"); 637 warning("POPCNT instruction is not available on this CPU");
638 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 638 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
639 } 639 }
640
641 #ifdef COMPILER2
642 if (FLAG_IS_DEFAULT(AlignVector)) {
643 // Modern processors allow misaligned memory operations for vectors.
644 AlignVector = !UseUnalignedLoadStores;
645 }
646 #endif // COMPILER2
640 647
641 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); 648 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
642 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); 649 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
643 650
644 // set valid Prefetch instruction 651 // set valid Prefetch instruction