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comparison src/share/vm/opto/ifg.cpp @ 6179:8c92982cbbc4

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7119644: Increase superword's vector size up to 256 bits Summary: Increase vector size up to 256-bits for YMM AVX registers on x86. Reviewed-by: never, twisti, roland
author kvn
date Fri, 15 Jun 2012 01:25:19 -0700
parents f95d63e2154a
children 2aff40cb4703
comparison
equal deleted inserted replaced
6146:eba1d5bce9e8 6179:8c92982cbbc4
1 /* 1 /*
2 * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
414 uint cnt = 0; 414 uint cnt = 0;
415 while ((lidx = elements.next()) != 0) { 415 while ((lidx = elements.next()) != 0) {
416 if( lrgs(lidx).mask().is_UP() && 416 if( lrgs(lidx).mask().is_UP() &&
417 lrgs(lidx).mask_size() && 417 lrgs(lidx).mask_size() &&
418 !lrgs(lidx)._is_float && 418 !lrgs(lidx)._is_float &&
419 !lrgs(lidx)._is_vector &&
419 lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) ) 420 lrgs(lidx).mask().overlap(*Matcher::idealreg2regmask[Op_RegI]) )
420 cnt += lrgs(lidx).reg_pressure(); 421 cnt += lrgs(lidx).reg_pressure();
421 } 422 }
422 return cnt; 423 return cnt;
423 } 424 }
428 uint lidx; 429 uint lidx;
429 uint cnt = 0; 430 uint cnt = 0;
430 while ((lidx = elements.next()) != 0) { 431 while ((lidx = elements.next()) != 0) {
431 if( lrgs(lidx).mask().is_UP() && 432 if( lrgs(lidx).mask().is_UP() &&
432 lrgs(lidx).mask_size() && 433 lrgs(lidx).mask_size() &&
433 lrgs(lidx)._is_float ) 434 (lrgs(lidx)._is_float || lrgs(lidx)._is_vector))
434 cnt += lrgs(lidx).reg_pressure(); 435 cnt += lrgs(lidx).reg_pressure();
435 } 436 }
436 return cnt; 437 return cnt;
437 } 438 }
438 439
439 //------------------------------lower_pressure--------------------------------- 440 //------------------------------lower_pressure---------------------------------
440 // Adjust register pressure down by 1. Capture last hi-to-low transition, 441 // Adjust register pressure down by 1. Capture last hi-to-low transition,
441 static void lower_pressure( LRG *lrg, uint where, Block *b, uint *pressure, uint *hrp_index ) { 442 static void lower_pressure( LRG *lrg, uint where, Block *b, uint *pressure, uint *hrp_index ) {
442 if( lrg->mask().is_UP() && lrg->mask_size() ) { 443 if (lrg->mask().is_UP() && lrg->mask_size()) {
443 if( lrg->_is_float ) { 444 if (lrg->_is_float || lrg->_is_vector) {
444 pressure[1] -= lrg->reg_pressure(); 445 pressure[1] -= lrg->reg_pressure();
445 if( pressure[1] == (uint)FLOATPRESSURE ) { 446 if( pressure[1] == (uint)FLOATPRESSURE ) {
446 hrp_index[1] = where; 447 hrp_index[1] = where;
447 #ifdef EXACT_PRESSURE 448 #ifdef EXACT_PRESSURE
448 if( pressure[1] > b->_freg_pressure ) 449 if( pressure[1] > b->_freg_pressure )
520 uint lidx; 521 uint lidx;
521 while ((lidx = elements.next()) != 0) { 522 while ((lidx = elements.next()) != 0) {
522 LRG &lrg = lrgs(lidx); 523 LRG &lrg = lrgs(lidx);
523 lrg._area += cost; 524 lrg._area += cost;
524 // Compute initial register pressure 525 // Compute initial register pressure
525 if( lrg.mask().is_UP() && lrg.mask_size() ) { 526 if (lrg.mask().is_UP() && lrg.mask_size()) {
526 if( lrg._is_float ) { // Count float pressure 527 if (lrg._is_float || lrg._is_vector) { // Count float pressure
527 pressure[1] += lrg.reg_pressure(); 528 pressure[1] += lrg.reg_pressure();
528 #ifdef EXACT_PRESSURE 529 #ifdef EXACT_PRESSURE
529 if( pressure[1] > b->_freg_pressure ) 530 if( pressure[1] > b->_freg_pressure )
530 b->_freg_pressure = pressure[1]; 531 b->_freg_pressure = pressure[1];
531 #endif 532 #endif
679 // DEFs are not bound but the live range is, some uses must be bound. 680 // DEFs are not bound but the live range is, some uses must be bound.
680 // If we spill live range 'r', it can rematerialize at each use site 681 // If we spill live range 'r', it can rematerialize at each use site
681 // according to its bindings. 682 // according to its bindings.
682 const RegMask &rmask = lrgs(r).mask(); 683 const RegMask &rmask = lrgs(r).mask();
683 if( lrgs(r).is_bound() && !(n->rematerialize()) && rmask.is_NotEmpty() ) { 684 if( lrgs(r).is_bound() && !(n->rematerialize()) && rmask.is_NotEmpty() ) {
684 // Smear odd bits; leave only aligned pairs of bits.
685 RegMask r2mask = rmask;
686 r2mask.SmearToPairs();
687 // Check for common case 685 // Check for common case
688 int r_size = lrgs(r).num_regs(); 686 int r_size = lrgs(r).num_regs();
689 OptoReg::Name r_reg = (r_size == 1) ? rmask.find_first_elem() : OptoReg::Physical; 687 OptoReg::Name r_reg = (r_size == 1) ? rmask.find_first_elem() : OptoReg::Physical;
690 688 // Smear odd bits
691 IndexSetIterator elements(&liveout); 689 IndexSetIterator elements(&liveout);
692 uint l; 690 uint l;
693 while ((l = elements.next()) != 0) { 691 while ((l = elements.next()) != 0) {
694 LRG &lrg = lrgs(l); 692 LRG &lrg = lrgs(l);
695 // If 'l' must spill already, do not further hack his bits. 693 // If 'l' must spill already, do not further hack his bits.
699 RegMask old = lrg.mask(); 697 RegMask old = lrg.mask();
700 uint old_size = lrg.mask_size(); 698 uint old_size = lrg.mask_size();
701 // Remove the bits from LRG 'r' from LRG 'l' so 'l' no 699 // Remove the bits from LRG 'r' from LRG 'l' so 'l' no
702 // longer interferes with 'r'. If 'l' requires aligned 700 // longer interferes with 'r'. If 'l' requires aligned
703 // adjacent pairs, subtract out bit pairs. 701 // adjacent pairs, subtract out bit pairs.
704 if( lrg.num_regs() == 2 && !lrg._fat_proj ) { 702 assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
703 if (lrg.num_regs() > 1 && !lrg._fat_proj) {
704 RegMask r2mask = rmask;
705 // Leave only aligned set of bits.
706 r2mask.smear_to_sets(lrg.num_regs());
707 // It includes vector case.
705 lrg.SUBTRACT( r2mask ); 708 lrg.SUBTRACT( r2mask );
706 lrg.compute_set_mask_size(); 709 lrg.compute_set_mask_size();
707 } else if( r_size != 1 ) { 710 } else if( r_size != 1 ) { // fat proj
708 lrg.SUBTRACT( rmask ); 711 lrg.SUBTRACT( rmask );
709 lrg.compute_set_mask_size(); 712 lrg.compute_set_mask_size();
710 } else { // Common case: size 1 bound removal 713 } else { // Common case: size 1 bound removal
711 if( lrg.mask().Member(r_reg) ) { 714 if( lrg.mask().Member(r_reg) ) {
712 lrg.Remove(r_reg); 715 lrg.Remove(r_reg);
761 // It is live now 764 // It is live now
762 if( liveout.insert( x ) ) { 765 if( liveout.insert( x ) ) {
763 // Newly live things assumed live from here to top of block 766 // Newly live things assumed live from here to top of block
764 lrg._area += cost; 767 lrg._area += cost;
765 // Adjust register pressure 768 // Adjust register pressure
766 if( lrg.mask().is_UP() && lrg.mask_size() ) { 769 if (lrg.mask().is_UP() && lrg.mask_size()) {
767 if( lrg._is_float ) { 770 if (lrg._is_float || lrg._is_vector) {
768 pressure[1] += lrg.reg_pressure(); 771 pressure[1] += lrg.reg_pressure();
769 #ifdef EXACT_PRESSURE 772 #ifdef EXACT_PRESSURE
770 if( pressure[1] > b->_freg_pressure ) 773 if( pressure[1] > b->_freg_pressure )
771 b->_freg_pressure = pressure[1]; 774 b->_freg_pressure = pressure[1];
772 #endif 775 #endif