Mercurial > hg > graal-jvmci-8
comparison src/cpu/sparc/vm/sparc.ad @ 3851:95134e034042
7063629: use cbcond in C2 generated code on T4
Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never
author | kvn |
---|---|
date | Thu, 11 Aug 2011 12:08:11 -0700 |
parents | f1c12354c3f7 |
children | 1af104d6cf99 |
comparison
equal
deleted
inserted
replaced
3850:6987871cfb9b | 3851:95134e034042 |
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1832 | 1832 |
1833 // Is this branch offset short enough that a short branch can be used? | 1833 // Is this branch offset short enough that a short branch can be used? |
1834 // | 1834 // |
1835 // NOTE: If the platform does not provide any short branch variants, then | 1835 // NOTE: If the platform does not provide any short branch variants, then |
1836 // this method should return false for offset 0. | 1836 // this method should return false for offset 0. |
1837 bool Matcher::is_short_branch_offset(int rule, int offset) { | 1837 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
1838 return false; | 1838 // The passed offset is relative to address of the branch. |
1839 // Don't need to adjust the offset. | |
1840 return UseCBCond && Assembler::is_simm(offset, 12); | |
1839 } | 1841 } |
1840 | 1842 |
1841 const bool Matcher::isSimpleConstant64(jlong value) { | 1843 const bool Matcher::isSimpleConstant64(jlong value) { |
1842 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | 1844 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. |
1843 // Depends on optimizations in MacroAssembler::setx. | 1845 // Depends on optimizations in MacroAssembler::setx. |
3313 op_attrib op_cost(1); // Required cost attribute | 3315 op_attrib op_cost(1); // Required cost attribute |
3314 | 3316 |
3315 //----------Instruction Attributes--------------------------------------------- | 3317 //----------Instruction Attributes--------------------------------------------- |
3316 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | 3318 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute |
3317 ins_attrib ins_size(32); // Required size attribute (in bits) | 3319 ins_attrib ins_size(32); // Required size attribute (in bits) |
3320 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back | |
3318 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | 3321 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
3319 // non-matching short branch variant of some | 3322 // non-matching short branch variant of some |
3320 // long branch? | 3323 // long branch? |
3321 | 3324 |
3322 //----------OPERANDS----------------------------------------------------------- | 3325 //----------OPERANDS----------------------------------------------------------- |
3400 op_cost(0); | 3403 op_cost(0); |
3401 format %{ %} | 3404 format %{ %} |
3402 interface(CONST_INTER); | 3405 interface(CONST_INTER); |
3403 %} | 3406 %} |
3404 | 3407 |
3408 // Integer Immediate: 5-bit | |
3409 operand immI5() %{ | |
3410 predicate(Assembler::is_simm(n->get_int(), 5)); | |
3411 match(ConI); | |
3412 op_cost(0); | |
3413 format %{ %} | |
3414 interface(CONST_INTER); | |
3415 %} | |
3416 | |
3405 // Integer Immediate: 0-bit | 3417 // Integer Immediate: 0-bit |
3406 operand immI0() %{ | 3418 operand immI0() %{ |
3407 predicate(n->get_int() == 0); | 3419 predicate(n->get_int() == 0); |
3408 match(ConI); | 3420 match(ConI); |
3409 op_cost(0); | 3421 op_cost(0); |
3619 operand immL0() %{ | 3631 operand immL0() %{ |
3620 predicate(n->get_long() == 0L); | 3632 predicate(n->get_long() == 0L); |
3621 match(ConL); | 3633 match(ConL); |
3622 op_cost(0); | 3634 op_cost(0); |
3623 // formats are generated automatically for constants and base registers | 3635 // formats are generated automatically for constants and base registers |
3636 format %{ %} | |
3637 interface(CONST_INTER); | |
3638 %} | |
3639 | |
3640 // Integer Immediate: 5-bit | |
3641 operand immL5() %{ | |
3642 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5)); | |
3643 match(ConL); | |
3644 op_cost(0); | |
3624 format %{ %} | 3645 format %{ %} |
3625 interface(CONST_INTER); | 3646 interface(CONST_INTER); |
3626 %} | 3647 %} |
3627 | 3648 |
3628 // Long Immediate: 13-bit | 3649 // Long Immediate: 13-bit |
5155 op1 : E(read); | 5176 op1 : E(read); |
5156 BR : R; | 5177 BR : R; |
5157 MS : R; | 5178 MS : R; |
5158 %} | 5179 %} |
5159 | 5180 |
5181 // Compare and branch | |
5182 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
5183 instruction_count(2); has_delay_slot; | |
5184 cr : E(write); | |
5185 src1 : R(read); | |
5186 src2 : R(read); | |
5187 IALU : R; | |
5188 BR : R; | |
5189 %} | |
5190 | |
5191 // Compare and branch | |
5192 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
5193 instruction_count(2); has_delay_slot; | |
5194 cr : E(write); | |
5195 src1 : R(read); | |
5196 IALU : R; | |
5197 BR : R; | |
5198 %} | |
5199 | |
5200 // Compare and branch using cbcond | |
5201 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
5202 single_instruction; | |
5203 src1 : E(read); | |
5204 src2 : E(read); | |
5205 IALU : R; | |
5206 BR : R; | |
5207 %} | |
5208 | |
5209 // Compare and branch using cbcond | |
5210 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
5211 single_instruction; | |
5212 src1 : E(read); | |
5213 IALU : R; | |
5214 BR : R; | |
5215 %} | |
5216 | |
5160 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | 5217 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
5161 single_instruction_with_delay_slot; | 5218 single_instruction_with_delay_slot; |
5162 cr : E(read); | 5219 cr : E(read); |
5163 BR : R; | 5220 BR : R; |
5164 %} | 5221 %} |
9196 __ delayed()->nop(); | 9253 __ delayed()->nop(); |
9197 %} | 9254 %} |
9198 ins_pipe(br); | 9255 ins_pipe(br); |
9199 %} | 9256 %} |
9200 | 9257 |
9258 // Direct Branch, short with no delay slot | |
9259 instruct branch_short(label labl) %{ | |
9260 match(Goto); | |
9261 predicate(UseCBCond); | |
9262 effect(USE labl); | |
9263 | |
9264 size(4); | |
9265 ins_cost(BRANCH_COST); | |
9266 format %{ "BA $labl\t! short branch" %} | |
9267 ins_encode %{ | |
9268 Label* L = $labl$$label; | |
9269 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9270 __ ba_short(*L); | |
9271 %} | |
9272 ins_short_branch(1); | |
9273 ins_avoid_back_to_back(1); | |
9274 ins_pipe(cbcond_reg_imm); | |
9275 %} | |
9276 | |
9201 // Conditional Direct Branch | 9277 // Conditional Direct Branch |
9202 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | 9278 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ |
9203 match(If cmp icc); | 9279 match(If cmp icc); |
9204 effect(USE labl); | 9280 effect(USE labl); |
9205 | 9281 |
9207 ins_cost(BRANCH_COST); | 9283 ins_cost(BRANCH_COST); |
9208 format %{ "BP$cmp $icc,$labl" %} | 9284 format %{ "BP$cmp $icc,$labl" %} |
9209 // Prim = bits 24-22, Secnd = bits 31-30 | 9285 // Prim = bits 24-22, Secnd = bits 31-30 |
9210 ins_encode( enc_bp( labl, cmp, icc ) ); | 9286 ins_encode( enc_bp( labl, cmp, icc ) ); |
9211 ins_pipe(br_cc); | 9287 ins_pipe(br_cc); |
9288 %} | |
9289 | |
9290 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9291 match(If cmp icc); | |
9292 effect(USE labl); | |
9293 | |
9294 ins_cost(BRANCH_COST); | |
9295 format %{ "BP$cmp $icc,$labl" %} | |
9296 // Prim = bits 24-22, Secnd = bits 31-30 | |
9297 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9298 ins_pipe(br_cc); | |
9299 %} | |
9300 | |
9301 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9302 match(If cmp pcc); | |
9303 effect(USE labl); | |
9304 | |
9305 size(8); | |
9306 ins_cost(BRANCH_COST); | |
9307 format %{ "BP$cmp $pcc,$labl" %} | |
9308 ins_encode %{ | |
9309 Label* L = $labl$$label; | |
9310 Assembler::Predict predict_taken = | |
9311 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9312 | |
9313 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9314 __ delayed()->nop(); | |
9315 %} | |
9316 ins_pipe(br_cc); | |
9317 %} | |
9318 | |
9319 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9320 match(If cmp fcc); | |
9321 effect(USE labl); | |
9322 | |
9323 size(8); | |
9324 ins_cost(BRANCH_COST); | |
9325 format %{ "FBP$cmp $fcc,$labl" %} | |
9326 ins_encode %{ | |
9327 Label* L = $labl$$label; | |
9328 Assembler::Predict predict_taken = | |
9329 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9330 | |
9331 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9332 __ delayed()->nop(); | |
9333 %} | |
9334 ins_pipe(br_fcc); | |
9335 %} | |
9336 | |
9337 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9338 match(CountedLoopEnd cmp icc); | |
9339 effect(USE labl); | |
9340 | |
9341 size(8); | |
9342 ins_cost(BRANCH_COST); | |
9343 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9344 // Prim = bits 24-22, Secnd = bits 31-30 | |
9345 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9346 ins_pipe(br_cc); | |
9347 %} | |
9348 | |
9349 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9350 match(CountedLoopEnd cmp icc); | |
9351 effect(USE labl); | |
9352 | |
9353 size(8); | |
9354 ins_cost(BRANCH_COST); | |
9355 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9356 // Prim = bits 24-22, Secnd = bits 31-30 | |
9357 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9358 ins_pipe(br_cc); | |
9359 %} | |
9360 | |
9361 // Compare and branch instructions | |
9362 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9363 match(If cmp (CmpI op1 op2)); | |
9364 effect(USE labl, KILL icc); | |
9365 | |
9366 size(12); | |
9367 ins_cost(BRANCH_COST); | |
9368 format %{ "CMP $op1,$op2\t! int\n\t" | |
9369 "BP$cmp $labl" %} | |
9370 ins_encode %{ | |
9371 Label* L = $labl$$label; | |
9372 Assembler::Predict predict_taken = | |
9373 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9374 __ cmp($op1$$Register, $op2$$Register); | |
9375 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9376 __ delayed()->nop(); | |
9377 %} | |
9378 ins_pipe(cmp_br_reg_reg); | |
9379 %} | |
9380 | |
9381 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9382 match(If cmp (CmpI op1 op2)); | |
9383 effect(USE labl, KILL icc); | |
9384 | |
9385 size(12); | |
9386 ins_cost(BRANCH_COST); | |
9387 format %{ "CMP $op1,$op2\t! int\n\t" | |
9388 "BP$cmp $labl" %} | |
9389 ins_encode %{ | |
9390 Label* L = $labl$$label; | |
9391 Assembler::Predict predict_taken = | |
9392 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9393 __ cmp($op1$$Register, $op2$$constant); | |
9394 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9395 __ delayed()->nop(); | |
9396 %} | |
9397 ins_pipe(cmp_br_reg_imm); | |
9398 %} | |
9399 | |
9400 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9401 match(If cmp (CmpU op1 op2)); | |
9402 effect(USE labl, KILL icc); | |
9403 | |
9404 size(12); | |
9405 ins_cost(BRANCH_COST); | |
9406 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9407 "BP$cmp $labl" %} | |
9408 ins_encode %{ | |
9409 Label* L = $labl$$label; | |
9410 Assembler::Predict predict_taken = | |
9411 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9412 __ cmp($op1$$Register, $op2$$Register); | |
9413 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9414 __ delayed()->nop(); | |
9415 %} | |
9416 ins_pipe(cmp_br_reg_reg); | |
9417 %} | |
9418 | |
9419 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9420 match(If cmp (CmpU op1 op2)); | |
9421 effect(USE labl, KILL icc); | |
9422 | |
9423 size(12); | |
9424 ins_cost(BRANCH_COST); | |
9425 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
9426 "BP$cmp $labl" %} | |
9427 ins_encode %{ | |
9428 Label* L = $labl$$label; | |
9429 Assembler::Predict predict_taken = | |
9430 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9431 __ cmp($op1$$Register, $op2$$constant); | |
9432 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9433 __ delayed()->nop(); | |
9434 %} | |
9435 ins_pipe(cmp_br_reg_imm); | |
9436 %} | |
9437 | |
9438 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9439 match(If cmp (CmpL op1 op2)); | |
9440 effect(USE labl, KILL xcc); | |
9441 | |
9442 size(12); | |
9443 ins_cost(BRANCH_COST); | |
9444 format %{ "CMP $op1,$op2\t! long\n\t" | |
9445 "BP$cmp $labl" %} | |
9446 ins_encode %{ | |
9447 Label* L = $labl$$label; | |
9448 Assembler::Predict predict_taken = | |
9449 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9450 __ cmp($op1$$Register, $op2$$Register); | |
9451 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9452 __ delayed()->nop(); | |
9453 %} | |
9454 ins_pipe(cmp_br_reg_reg); | |
9455 %} | |
9456 | |
9457 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9458 match(If cmp (CmpL op1 op2)); | |
9459 effect(USE labl, KILL xcc); | |
9460 | |
9461 size(12); | |
9462 ins_cost(BRANCH_COST); | |
9463 format %{ "CMP $op1,$op2\t! long\n\t" | |
9464 "BP$cmp $labl" %} | |
9465 ins_encode %{ | |
9466 Label* L = $labl$$label; | |
9467 Assembler::Predict predict_taken = | |
9468 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9469 __ cmp($op1$$Register, $op2$$constant); | |
9470 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
9471 __ delayed()->nop(); | |
9472 %} | |
9473 ins_pipe(cmp_br_reg_imm); | |
9474 %} | |
9475 | |
9476 // Compare Pointers and branch | |
9477 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9478 match(If cmp (CmpP op1 op2)); | |
9479 effect(USE labl, KILL pcc); | |
9480 | |
9481 size(12); | |
9482 ins_cost(BRANCH_COST); | |
9483 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
9484 "B$cmp $labl" %} | |
9485 ins_encode %{ | |
9486 Label* L = $labl$$label; | |
9487 Assembler::Predict predict_taken = | |
9488 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9489 __ cmp($op1$$Register, $op2$$Register); | |
9490 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9491 __ delayed()->nop(); | |
9492 %} | |
9493 ins_pipe(cmp_br_reg_reg); | |
9494 %} | |
9495 | |
9496 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9497 match(If cmp (CmpP op1 null)); | |
9498 effect(USE labl, KILL pcc); | |
9499 | |
9500 size(12); | |
9501 ins_cost(BRANCH_COST); | |
9502 format %{ "CMP $op1,0\t! ptr\n\t" | |
9503 "B$cmp $labl" %} | |
9504 ins_encode %{ | |
9505 Label* L = $labl$$label; | |
9506 Assembler::Predict predict_taken = | |
9507 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9508 __ cmp($op1$$Register, G0); | |
9509 // bpr() is not used here since it has shorter distance. | |
9510 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9511 __ delayed()->nop(); | |
9512 %} | |
9513 ins_pipe(cmp_br_reg_reg); | |
9514 %} | |
9515 | |
9516 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9517 match(If cmp (CmpN op1 op2)); | |
9518 effect(USE labl, KILL icc); | |
9519 | |
9520 size(12); | |
9521 ins_cost(BRANCH_COST); | |
9522 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
9523 "BP$cmp $labl" %} | |
9524 ins_encode %{ | |
9525 Label* L = $labl$$label; | |
9526 Assembler::Predict predict_taken = | |
9527 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9528 __ cmp($op1$$Register, $op2$$Register); | |
9529 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9530 __ delayed()->nop(); | |
9531 %} | |
9532 ins_pipe(cmp_br_reg_reg); | |
9533 %} | |
9534 | |
9535 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9536 match(If cmp (CmpN op1 null)); | |
9537 effect(USE labl, KILL icc); | |
9538 | |
9539 size(12); | |
9540 ins_cost(BRANCH_COST); | |
9541 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
9542 "BP$cmp $labl" %} | |
9543 ins_encode %{ | |
9544 Label* L = $labl$$label; | |
9545 Assembler::Predict predict_taken = | |
9546 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9547 __ cmp($op1$$Register, G0); | |
9548 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9549 __ delayed()->nop(); | |
9550 %} | |
9551 ins_pipe(cmp_br_reg_reg); | |
9552 %} | |
9553 | |
9554 // Loop back branch | |
9555 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9556 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9557 effect(USE labl, KILL icc); | |
9558 | |
9559 size(12); | |
9560 ins_cost(BRANCH_COST); | |
9561 format %{ "CMP $op1,$op2\t! int\n\t" | |
9562 "BP$cmp $labl\t! Loop end" %} | |
9563 ins_encode %{ | |
9564 Label* L = $labl$$label; | |
9565 Assembler::Predict predict_taken = | |
9566 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9567 __ cmp($op1$$Register, $op2$$Register); | |
9568 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9569 __ delayed()->nop(); | |
9570 %} | |
9571 ins_pipe(cmp_br_reg_reg); | |
9572 %} | |
9573 | |
9574 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9575 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9576 effect(USE labl, KILL icc); | |
9577 | |
9578 size(12); | |
9579 ins_cost(BRANCH_COST); | |
9580 format %{ "CMP $op1,$op2\t! int\n\t" | |
9581 "BP$cmp $labl\t! Loop end" %} | |
9582 ins_encode %{ | |
9583 Label* L = $labl$$label; | |
9584 Assembler::Predict predict_taken = | |
9585 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9586 __ cmp($op1$$Register, $op2$$constant); | |
9587 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
9588 __ delayed()->nop(); | |
9589 %} | |
9590 ins_pipe(cmp_br_reg_imm); | |
9591 %} | |
9592 | |
9593 // Short compare and branch instructions | |
9594 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9595 match(If cmp (CmpI op1 op2)); | |
9596 predicate(UseCBCond); | |
9597 effect(USE labl, KILL icc); | |
9598 | |
9599 size(4); | |
9600 ins_cost(BRANCH_COST); | |
9601 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9602 ins_encode %{ | |
9603 Label* L = $labl$$label; | |
9604 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9605 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9606 %} | |
9607 ins_short_branch(1); | |
9608 ins_avoid_back_to_back(1); | |
9609 ins_pipe(cbcond_reg_reg); | |
9610 %} | |
9611 | |
9612 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9613 match(If cmp (CmpI op1 op2)); | |
9614 predicate(UseCBCond); | |
9615 effect(USE labl, KILL icc); | |
9616 | |
9617 size(4); | |
9618 ins_cost(BRANCH_COST); | |
9619 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
9620 ins_encode %{ | |
9621 Label* L = $labl$$label; | |
9622 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9623 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9624 %} | |
9625 ins_short_branch(1); | |
9626 ins_avoid_back_to_back(1); | |
9627 ins_pipe(cbcond_reg_imm); | |
9628 %} | |
9629 | |
9630 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
9631 match(If cmp (CmpU op1 op2)); | |
9632 predicate(UseCBCond); | |
9633 effect(USE labl, KILL icc); | |
9634 | |
9635 size(4); | |
9636 ins_cost(BRANCH_COST); | |
9637 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9638 ins_encode %{ | |
9639 Label* L = $labl$$label; | |
9640 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9641 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9642 %} | |
9643 ins_short_branch(1); | |
9644 ins_avoid_back_to_back(1); | |
9645 ins_pipe(cbcond_reg_reg); | |
9646 %} | |
9647 | |
9648 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
9649 match(If cmp (CmpU op1 op2)); | |
9650 predicate(UseCBCond); | |
9651 effect(USE labl, KILL icc); | |
9652 | |
9653 size(4); | |
9654 ins_cost(BRANCH_COST); | |
9655 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
9656 ins_encode %{ | |
9657 Label* L = $labl$$label; | |
9658 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9659 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9660 %} | |
9661 ins_short_branch(1); | |
9662 ins_avoid_back_to_back(1); | |
9663 ins_pipe(cbcond_reg_imm); | |
9664 %} | |
9665 | |
9666 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
9667 match(If cmp (CmpL op1 op2)); | |
9668 predicate(UseCBCond); | |
9669 effect(USE labl, KILL xcc); | |
9670 | |
9671 size(4); | |
9672 ins_cost(BRANCH_COST); | |
9673 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9674 ins_encode %{ | |
9675 Label* L = $labl$$label; | |
9676 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9677 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
9678 %} | |
9679 ins_short_branch(1); | |
9680 ins_avoid_back_to_back(1); | |
9681 ins_pipe(cbcond_reg_reg); | |
9682 %} | |
9683 | |
9684 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
9685 match(If cmp (CmpL op1 op2)); | |
9686 predicate(UseCBCond); | |
9687 effect(USE labl, KILL xcc); | |
9688 | |
9689 size(4); | |
9690 ins_cost(BRANCH_COST); | |
9691 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
9692 ins_encode %{ | |
9693 Label* L = $labl$$label; | |
9694 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
9696 %} | |
9697 ins_short_branch(1); | |
9698 ins_avoid_back_to_back(1); | |
9699 ins_pipe(cbcond_reg_imm); | |
9700 %} | |
9701 | |
9702 // Compare Pointers and branch | |
9703 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
9704 match(If cmp (CmpP op1 op2)); | |
9705 predicate(UseCBCond); | |
9706 effect(USE labl, KILL pcc); | |
9707 | |
9708 size(4); | |
9709 ins_cost(BRANCH_COST); | |
9710 #ifdef _LP64 | |
9711 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
9712 #else | |
9713 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
9714 #endif | |
9715 ins_encode %{ | |
9716 Label* L = $labl$$label; | |
9717 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9718 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
9719 %} | |
9720 ins_short_branch(1); | |
9721 ins_avoid_back_to_back(1); | |
9722 ins_pipe(cbcond_reg_reg); | |
9723 %} | |
9724 | |
9725 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
9726 match(If cmp (CmpP op1 null)); | |
9727 predicate(UseCBCond); | |
9728 effect(USE labl, KILL pcc); | |
9729 | |
9730 size(4); | |
9731 ins_cost(BRANCH_COST); | |
9732 #ifdef _LP64 | |
9733 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
9734 #else | |
9735 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
9736 #endif | |
9737 ins_encode %{ | |
9738 Label* L = $labl$$label; | |
9739 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9740 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
9741 %} | |
9742 ins_short_branch(1); | |
9743 ins_avoid_back_to_back(1); | |
9744 ins_pipe(cbcond_reg_reg); | |
9745 %} | |
9746 | |
9747 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
9748 match(If cmp (CmpN op1 op2)); | |
9749 predicate(UseCBCond); | |
9750 effect(USE labl, KILL icc); | |
9751 | |
9752 size(4); | |
9753 ins_cost(BRANCH_COST); | |
9754 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
9755 ins_encode %{ | |
9756 Label* L = $labl$$label; | |
9757 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9758 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9759 %} | |
9760 ins_short_branch(1); | |
9761 ins_avoid_back_to_back(1); | |
9762 ins_pipe(cbcond_reg_reg); | |
9763 %} | |
9764 | |
9765 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
9766 match(If cmp (CmpN op1 null)); | |
9767 predicate(UseCBCond); | |
9768 effect(USE labl, KILL icc); | |
9769 | |
9770 size(4); | |
9771 ins_cost(BRANCH_COST); | |
9772 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
9773 ins_encode %{ | |
9774 Label* L = $labl$$label; | |
9775 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9776 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
9777 %} | |
9778 ins_short_branch(1); | |
9779 ins_avoid_back_to_back(1); | |
9780 ins_pipe(cbcond_reg_reg); | |
9781 %} | |
9782 | |
9783 // Loop back branch | |
9784 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
9785 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9786 predicate(UseCBCond); | |
9787 effect(USE labl, KILL icc); | |
9788 | |
9789 size(4); | |
9790 ins_cost(BRANCH_COST); | |
9791 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9792 ins_encode %{ | |
9793 Label* L = $labl$$label; | |
9794 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9795 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
9796 %} | |
9797 ins_short_branch(1); | |
9798 ins_avoid_back_to_back(1); | |
9799 ins_pipe(cbcond_reg_reg); | |
9800 %} | |
9801 | |
9802 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
9803 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
9804 predicate(UseCBCond); | |
9805 effect(USE labl, KILL icc); | |
9806 | |
9807 size(4); | |
9808 ins_cost(BRANCH_COST); | |
9809 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
9810 ins_encode %{ | |
9811 Label* L = $labl$$label; | |
9812 assert(__ use_cbcond(*L), "back to back cbcond"); | |
9813 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
9814 %} | |
9815 ins_short_branch(1); | |
9816 ins_avoid_back_to_back(1); | |
9817 ins_pipe(cbcond_reg_imm); | |
9212 %} | 9818 %} |
9213 | 9819 |
9214 // Branch-on-register tests all 64 bits. We assume that values | 9820 // Branch-on-register tests all 64 bits. We assume that values |
9215 // in 64-bit registers always remains zero or sign extended | 9821 // in 64-bit registers always remains zero or sign extended |
9216 // unless our code munges the high bits. Interrupts can chop | 9822 // unless our code munges the high bits. Interrupts can chop |
9249 format %{ "BR$cmp $op1,$labl" %} | 9855 format %{ "BR$cmp $op1,$labl" %} |
9250 ins_encode( enc_bpr( labl, cmp, op1 ) ); | 9856 ins_encode( enc_bpr( labl, cmp, op1 ) ); |
9251 ins_pipe(br_reg); | 9857 ins_pipe(br_reg); |
9252 %} | 9858 %} |
9253 | 9859 |
9254 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9255 match(If cmp icc); | |
9256 effect(USE labl); | |
9257 | |
9258 format %{ "BP$cmp $icc,$labl" %} | |
9259 // Prim = bits 24-22, Secnd = bits 31-30 | |
9260 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9261 ins_pipe(br_cc); | |
9262 %} | |
9263 | |
9264 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9265 match(If cmp pcc); | |
9266 effect(USE labl); | |
9267 | |
9268 size(8); | |
9269 ins_cost(BRANCH_COST); | |
9270 format %{ "BP$cmp $pcc,$labl" %} | |
9271 ins_encode %{ | |
9272 Label* L = $labl$$label; | |
9273 Assembler::Predict predict_taken = | |
9274 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9275 | |
9276 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
9277 __ delayed()->nop(); | |
9278 %} | |
9279 ins_pipe(br_cc); | |
9280 %} | |
9281 | |
9282 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9283 match(If cmp fcc); | |
9284 effect(USE labl); | |
9285 | |
9286 size(8); | |
9287 ins_cost(BRANCH_COST); | |
9288 format %{ "FBP$cmp $fcc,$labl" %} | |
9289 ins_encode %{ | |
9290 Label* L = $labl$$label; | |
9291 Assembler::Predict predict_taken = | |
9292 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
9293 | |
9294 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
9295 __ delayed()->nop(); | |
9296 %} | |
9297 ins_pipe(br_fcc); | |
9298 %} | |
9299 | |
9300 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9301 match(CountedLoopEnd cmp icc); | |
9302 effect(USE labl); | |
9303 | |
9304 size(8); | |
9305 ins_cost(BRANCH_COST); | |
9306 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9307 // Prim = bits 24-22, Secnd = bits 31-30 | |
9308 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9309 ins_pipe(br_cc); | |
9310 %} | |
9311 | |
9312 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9313 match(CountedLoopEnd cmp icc); | |
9314 effect(USE labl); | |
9315 | |
9316 size(8); | |
9317 ins_cost(BRANCH_COST); | |
9318 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9319 // Prim = bits 24-22, Secnd = bits 31-30 | |
9320 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9321 ins_pipe(br_cc); | |
9322 %} | |
9323 | 9860 |
9324 // ============================================================================ | 9861 // ============================================================================ |
9325 // Long Compare | 9862 // Long Compare |
9326 // | 9863 // |
9327 // Currently we hold longs in 2 registers. Comparing such values efficiently | 9864 // Currently we hold longs in 2 registers. Comparing such values efficiently |