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comparison src/cpu/x86/vm/nativeInst_x86.hpp @ 5000:b5dc2403c1e7

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add option to inline VTable stubs
author Lukas Stadler <lukas.stadler@jku.at>
date Thu, 01 Mar 2012 12:11:19 +0100
parents 33df1aeaebbf
children f565e8d4d200
comparison
equal deleted inserted replaced
4999:71bcf0a9e875 5000:b5dc2403c1e7
59 }; 59 };
60 60
61 bool is_nop() { return ubyte_at(0) == nop_instruction_code; } 61 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
62 bool is_dtrace_trap(); 62 bool is_dtrace_trap();
63 inline bool is_call(); 63 inline bool is_call();
64 inline bool is_call_reg();
64 inline bool is_illegal(); 65 inline bool is_illegal();
65 inline bool is_return(); 66 inline bool is_return();
66 inline bool is_jump(); 67 inline bool is_jump();
67 inline bool is_cond_jump(); 68 inline bool is_cond_jump();
68 inline bool is_safepoint_poll(); 69 inline bool is_safepoint_poll();
178 #ifdef ASSERT 179 #ifdef ASSERT
179 call->verify(); 180 call->verify();
180 #endif 181 #endif
181 return call; 182 return call;
182 } 183 }
184
185 class NativeCallReg: public NativeInstruction {
186 public:
187 enum Intel_specific_constants {
188 instruction_code = 0xFF,
189 instruction_size = 2,
190 instruction_offset = 0,
191 return_address_offset = 2
192 };
193
194 address instruction_address() const { return addr_at(instruction_offset); }
195 address next_instruction_address() const { return addr_at(return_address_offset); }
196
197
198 static bool is_call_reg_at(address instr) {
199 return ((*instr) & 0xFF) == NativeCallReg::instruction_code;
200 }
201
202 static bool is_call_reg_before(address return_address) {
203 return is_call_reg_at(return_address - NativeCallReg::return_address_offset);
204 }
205 };
183 206
184 // An interface for accessing/manipulating native mov reg, imm32 instructions. 207 // An interface for accessing/manipulating native mov reg, imm32 instructions.
185 // (used to manipulate inlined 32bit data dll calls, etc.) 208 // (used to manipulate inlined 32bit data dll calls, etc.)
186 class NativeMovConstReg: public NativeInstruction { 209 class NativeMovConstReg: public NativeInstruction {
187 #ifdef AMD64 210 #ifdef AMD64
530 }; 553 };
531 }; 554 };
532 555
533 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } 556 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
534 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } 557 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
558 inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code; }
535 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || 559 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
536 ubyte_at(0) == NativeReturnX::instruction_code; } 560 ubyte_at(0) == NativeReturnX::instruction_code; }
537 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || 561 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
538 ubyte_at(0) == 0xEB; /* short jump */ } 562 ubyte_at(0) == 0xEB; /* short jump */ }
539 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || 563 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||