Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/assembler_x86.cpp @ 6646:c38f13903fdf
Merge with http://hg.openjdk.java.net/hsx/hsx25/hotspot/ just before the NPG (no perm gen) changeset
author | Doug Simon <doug.simon@oracle.com> |
---|---|
date | Mon, 29 Oct 2012 21:10:04 +0100 |
parents | 957c266d8bc5 006050192a5a |
children | e522a00b91aa |
comparison
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6590:dc5eec61daba | 6646:c38f13903fdf |
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997 emit_long(0); // 32-bits offset (4 bytes) | 997 emit_long(0); // 32-bits offset (4 bytes) |
998 } | 998 } |
999 | 999 |
1000 void Assembler::addsd(XMMRegister dst, XMMRegister src) { | 1000 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
1001 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1001 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1002 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1002 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
1003 emit_byte(0x58); | |
1004 emit_byte(0xC0 | encode); | |
1005 } | 1003 } |
1006 | 1004 |
1007 void Assembler::addsd(XMMRegister dst, Address src) { | 1005 void Assembler::addsd(XMMRegister dst, Address src) { |
1008 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1009 InstructionMark im(this); | 1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
1010 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1011 emit_byte(0x58); | |
1012 emit_operand(dst, src); | |
1013 } | 1008 } |
1014 | 1009 |
1015 void Assembler::addss(XMMRegister dst, XMMRegister src) { | 1010 void Assembler::addss(XMMRegister dst, XMMRegister src) { |
1016 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1011 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1017 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1012 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
1018 emit_byte(0x58); | |
1019 emit_byte(0xC0 | encode); | |
1020 } | 1013 } |
1021 | 1014 |
1022 void Assembler::addss(XMMRegister dst, Address src) { | 1015 void Assembler::addss(XMMRegister dst, Address src) { |
1023 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1016 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1024 InstructionMark im(this); | 1017 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
1025 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1026 emit_byte(0x58); | |
1027 emit_operand(dst, src); | |
1028 } | 1018 } |
1029 | 1019 |
1030 void Assembler::andl(Address dst, int32_t imm32) { | 1020 void Assembler::andl(Address dst, int32_t imm32) { |
1031 InstructionMark im(this); | 1021 InstructionMark im(this); |
1032 prefix(dst); | 1022 prefix(dst); |
1048 } | 1038 } |
1049 | 1039 |
1050 void Assembler::andl(Register dst, Register src) { | 1040 void Assembler::andl(Register dst, Register src) { |
1051 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 1041 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
1052 emit_arith(0x23, 0xC0, dst, src); | 1042 emit_arith(0x23, 0xC0, dst, src); |
1053 } | |
1054 | |
1055 void Assembler::andpd(XMMRegister dst, Address src) { | |
1056 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1057 InstructionMark im(this); | |
1058 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
1059 emit_byte(0x54); | |
1060 emit_operand(dst, src); | |
1061 } | |
1062 | |
1063 void Assembler::andpd(XMMRegister dst, XMMRegister src) { | |
1064 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1065 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
1066 emit_byte(0x54); | |
1067 emit_byte(0xC0 | encode); | |
1068 } | |
1069 | |
1070 void Assembler::andps(XMMRegister dst, Address src) { | |
1071 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1072 InstructionMark im(this); | |
1073 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
1074 emit_byte(0x54); | |
1075 emit_operand(dst, src); | |
1076 } | |
1077 | |
1078 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
1079 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1080 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
1081 emit_byte(0x54); | |
1082 emit_byte(0xC0 | encode); | |
1083 } | 1043 } |
1084 | 1044 |
1085 void Assembler::bsfl(Register dst, Register src) { | 1045 void Assembler::bsfl(Register dst, Register src) { |
1086 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | 1046 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
1087 emit_byte(0x0F); | 1047 emit_byte(0x0F); |
1244 | 1204 |
1245 void Assembler::comisd(XMMRegister dst, Address src) { | 1205 void Assembler::comisd(XMMRegister dst, Address src) { |
1246 // NOTE: dbx seems to decode this as comiss even though the | 1206 // NOTE: dbx seems to decode this as comiss even though the |
1247 // 0x66 is there. Strangly ucomisd comes out correct | 1207 // 0x66 is there. Strangly ucomisd comes out correct |
1248 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1208 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1249 InstructionMark im(this); | 1209 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
1250 simd_prefix(dst, src, VEX_SIMD_66); | |
1251 emit_byte(0x2F); | |
1252 emit_operand(dst, src); | |
1253 } | 1210 } |
1254 | 1211 |
1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | 1212 void Assembler::comisd(XMMRegister dst, XMMRegister src) { |
1256 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1213 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1257 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 1214 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
1258 emit_byte(0x2F); | |
1259 emit_byte(0xC0 | encode); | |
1260 } | 1215 } |
1261 | 1216 |
1262 void Assembler::comiss(XMMRegister dst, Address src) { | 1217 void Assembler::comiss(XMMRegister dst, Address src) { |
1263 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1218 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1264 InstructionMark im(this); | 1219 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
1265 simd_prefix(dst, src, VEX_SIMD_NONE); | |
1266 emit_byte(0x2F); | |
1267 emit_operand(dst, src); | |
1268 } | 1220 } |
1269 | 1221 |
1270 void Assembler::comiss(XMMRegister dst, XMMRegister src) { | 1222 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
1271 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1223 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1272 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | 1224 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
1273 emit_byte(0x2F); | |
1274 emit_byte(0xC0 | encode); | |
1275 } | 1225 } |
1276 | 1226 |
1277 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | 1227 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1278 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1279 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); | 1229 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
1280 emit_byte(0xE6); | |
1281 emit_byte(0xC0 | encode); | |
1282 } | 1230 } |
1283 | 1231 |
1284 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | 1232 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { |
1285 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1233 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1286 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | 1234 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
1287 emit_byte(0x5B); | |
1288 emit_byte(0xC0 | encode); | |
1289 } | 1235 } |
1290 | 1236 |
1291 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | 1237 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
1292 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1238 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1239 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
1294 emit_byte(0x5A); | |
1295 emit_byte(0xC0 | encode); | |
1296 } | 1240 } |
1297 | 1241 |
1298 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { | 1242 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
1299 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1243 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1300 InstructionMark im(this); | 1244 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
1301 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1302 emit_byte(0x5A); | |
1303 emit_operand(dst, src); | |
1304 } | 1245 } |
1305 | 1246 |
1306 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | 1247 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1307 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1248 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1308 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1249 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
1310 emit_byte(0xC0 | encode); | 1251 emit_byte(0xC0 | encode); |
1311 } | 1252 } |
1312 | 1253 |
1313 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { | 1254 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1314 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1255 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1315 InstructionMark im(this); | 1256 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
1316 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1317 emit_byte(0x2A); | |
1318 emit_operand(dst, src); | |
1319 } | 1257 } |
1320 | 1258 |
1321 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | 1259 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1322 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1260 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
1325 emit_byte(0xC0 | encode); | 1263 emit_byte(0xC0 | encode); |
1326 } | 1264 } |
1327 | 1265 |
1328 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { | 1266 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1329 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1267 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1330 InstructionMark im(this); | 1268 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
1331 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1332 emit_byte(0x2A); | |
1333 emit_operand(dst, src); | |
1334 } | 1269 } |
1335 | 1270 |
1336 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | 1271 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1337 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1272 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1338 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1273 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
1339 emit_byte(0x5A); | |
1340 emit_byte(0xC0 | encode); | |
1341 } | 1274 } |
1342 | 1275 |
1343 void Assembler::cvtss2sd(XMMRegister dst, Address src) { | 1276 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
1344 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1277 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1345 InstructionMark im(this); | 1278 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
1346 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1347 emit_byte(0x5A); | |
1348 emit_operand(dst, src); | |
1349 } | 1279 } |
1350 | 1280 |
1351 | 1281 |
1352 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | 1282 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1353 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1371 emit_operand(rcx, dst); | 1301 emit_operand(rcx, dst); |
1372 } | 1302 } |
1373 | 1303 |
1374 void Assembler::divsd(XMMRegister dst, Address src) { | 1304 void Assembler::divsd(XMMRegister dst, Address src) { |
1375 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1305 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1376 InstructionMark im(this); | 1306 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
1377 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
1378 emit_byte(0x5E); | |
1379 emit_operand(dst, src); | |
1380 } | 1307 } |
1381 | 1308 |
1382 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | 1309 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
1383 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1310 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1311 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
1385 emit_byte(0x5E); | |
1386 emit_byte(0xC0 | encode); | |
1387 } | 1312 } |
1388 | 1313 |
1389 void Assembler::divss(XMMRegister dst, Address src) { | 1314 void Assembler::divss(XMMRegister dst, Address src) { |
1390 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1315 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1391 InstructionMark im(this); | 1316 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
1392 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
1393 emit_byte(0x5E); | |
1394 emit_operand(dst, src); | |
1395 } | 1317 } |
1396 | 1318 |
1397 void Assembler::divss(XMMRegister dst, XMMRegister src) { | 1319 void Assembler::divss(XMMRegister dst, XMMRegister src) { |
1398 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1320 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1399 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1321 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
1400 emit_byte(0x5E); | |
1401 emit_byte(0xC0 | encode); | |
1402 } | 1322 } |
1403 | 1323 |
1404 void Assembler::emms() { | 1324 void Assembler::emms() { |
1405 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | 1325 NOT_LP64(assert(VM_Version::supports_mmx(), "")); |
1406 emit_byte(0x0F); | 1326 emit_byte(0x0F); |
1632 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | 1552 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); |
1633 } | 1553 } |
1634 | 1554 |
1635 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | 1555 void Assembler::movapd(XMMRegister dst, XMMRegister src) { |
1636 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1556 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1637 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 1557 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
1638 emit_byte(0x28); | |
1639 emit_byte(0xC0 | encode); | |
1640 } | 1558 } |
1641 | 1559 |
1642 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | 1560 void Assembler::movaps(XMMRegister dst, XMMRegister src) { |
1643 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1561 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1644 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | 1562 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
1645 emit_byte(0x28); | |
1646 emit_byte(0xC0 | encode); | |
1647 } | 1563 } |
1648 | 1564 |
1649 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { | 1565 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
1650 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1566 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1651 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); | 1567 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
1710 emit_operand(src, dst); | 1626 emit_operand(src, dst); |
1711 } | 1627 } |
1712 | 1628 |
1713 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | 1629 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1714 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1630 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1715 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 1631 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
1716 emit_byte(0x6F); | |
1717 emit_byte(0xC0 | encode); | |
1718 } | 1632 } |
1719 | 1633 |
1720 void Assembler::movdqu(XMMRegister dst, Address src) { | 1634 void Assembler::movdqu(XMMRegister dst, Address src) { |
1721 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1635 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1722 InstructionMark im(this); | 1636 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
1723 simd_prefix(dst, src, VEX_SIMD_F3); | |
1724 emit_byte(0x6F); | |
1725 emit_operand(dst, src); | |
1726 } | 1637 } |
1727 | 1638 |
1728 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | 1639 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { |
1729 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1640 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1730 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); | 1641 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
1731 emit_byte(0x6F); | |
1732 emit_byte(0xC0 | encode); | |
1733 } | 1642 } |
1734 | 1643 |
1735 void Assembler::movdqu(Address dst, XMMRegister src) { | 1644 void Assembler::movdqu(Address dst, XMMRegister src) { |
1736 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1645 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1737 InstructionMark im(this); | 1646 InstructionMark im(this); |
1808 // New cpus require to use movsd and movss to avoid partial register stall | 1717 // New cpus require to use movsd and movss to avoid partial register stall |
1809 // when loading from memory. But for old Opteron use movlpd instead of movsd. | 1718 // when loading from memory. But for old Opteron use movlpd instead of movsd. |
1810 // The selection is done in MacroAssembler::movdbl() and movflt(). | 1719 // The selection is done in MacroAssembler::movdbl() and movflt(). |
1811 void Assembler::movlpd(XMMRegister dst, Address src) { | 1720 void Assembler::movlpd(XMMRegister dst, Address src) { |
1812 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1721 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1813 InstructionMark im(this); | 1722 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
1814 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
1815 emit_byte(0x12); | |
1816 emit_operand(dst, src); | |
1817 } | 1723 } |
1818 | 1724 |
1819 void Assembler::movq( MMXRegister dst, Address src ) { | 1725 void Assembler::movq( MMXRegister dst, Address src ) { |
1820 assert( VM_Version::supports_mmx(), "" ); | 1726 assert( VM_Version::supports_mmx(), "" ); |
1821 emit_byte(0x0F); | 1727 emit_byte(0x0F); |
1868 emit_byte(0xC0 | encode); | 1774 emit_byte(0xC0 | encode); |
1869 } | 1775 } |
1870 | 1776 |
1871 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | 1777 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
1872 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1778 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1873 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1779 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
1874 emit_byte(0x10); | |
1875 emit_byte(0xC0 | encode); | |
1876 } | 1780 } |
1877 | 1781 |
1878 void Assembler::movsd(XMMRegister dst, Address src) { | 1782 void Assembler::movsd(XMMRegister dst, Address src) { |
1879 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1880 InstructionMark im(this); | 1784 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
1881 simd_prefix(dst, src, VEX_SIMD_F2); | |
1882 emit_byte(0x10); | |
1883 emit_operand(dst, src); | |
1884 } | 1785 } |
1885 | 1786 |
1886 void Assembler::movsd(Address dst, XMMRegister src) { | 1787 void Assembler::movsd(Address dst, XMMRegister src) { |
1887 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1788 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
1888 InstructionMark im(this); | 1789 InstructionMark im(this); |
1891 emit_operand(src, dst); | 1792 emit_operand(src, dst); |
1892 } | 1793 } |
1893 | 1794 |
1894 void Assembler::movss(XMMRegister dst, XMMRegister src) { | 1795 void Assembler::movss(XMMRegister dst, XMMRegister src) { |
1895 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1796 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1797 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
1897 emit_byte(0x10); | |
1898 emit_byte(0xC0 | encode); | |
1899 } | 1798 } |
1900 | 1799 |
1901 void Assembler::movss(XMMRegister dst, Address src) { | 1800 void Assembler::movss(XMMRegister dst, Address src) { |
1902 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1801 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1903 InstructionMark im(this); | 1802 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
1904 simd_prefix(dst, src, VEX_SIMD_F3); | |
1905 emit_byte(0x10); | |
1906 emit_operand(dst, src); | |
1907 } | 1803 } |
1908 | 1804 |
1909 void Assembler::movss(Address dst, XMMRegister src) { | 1805 void Assembler::movss(Address dst, XMMRegister src) { |
1910 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
1911 InstructionMark im(this); | 1807 InstructionMark im(this); |
1999 emit_byte(0xE0 | encode); | 1895 emit_byte(0xE0 | encode); |
2000 } | 1896 } |
2001 | 1897 |
2002 void Assembler::mulsd(XMMRegister dst, Address src) { | 1898 void Assembler::mulsd(XMMRegister dst, Address src) { |
2003 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1899 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2004 InstructionMark im(this); | 1900 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
2005 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
2006 emit_byte(0x59); | |
2007 emit_operand(dst, src); | |
2008 } | 1901 } |
2009 | 1902 |
2010 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | 1903 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
2011 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 1904 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2012 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 1905 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
2013 emit_byte(0x59); | |
2014 emit_byte(0xC0 | encode); | |
2015 } | 1906 } |
2016 | 1907 |
2017 void Assembler::mulss(XMMRegister dst, Address src) { | 1908 void Assembler::mulss(XMMRegister dst, Address src) { |
2018 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1909 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2019 InstructionMark im(this); | 1910 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
2020 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
2021 emit_byte(0x59); | |
2022 emit_operand(dst, src); | |
2023 } | 1911 } |
2024 | 1912 |
2025 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | 1913 void Assembler::mulss(XMMRegister dst, XMMRegister src) { |
2026 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 1914 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2027 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 1915 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
2028 emit_byte(0x59); | |
2029 emit_byte(0xC0 | encode); | |
2030 } | 1916 } |
2031 | 1917 |
2032 void Assembler::negl(Register dst) { | 1918 void Assembler::negl(Register dst) { |
2033 int encode = prefix_and_encode(dst->encoding()); | 1919 int encode = prefix_and_encode(dst->encoding()); |
2034 emit_byte(0xF7); | 1920 emit_byte(0xF7); |
2313 } | 2199 } |
2314 | 2200 |
2315 void Assembler::packuswb(XMMRegister dst, Address src) { | 2201 void Assembler::packuswb(XMMRegister dst, Address src) { |
2316 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2202 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2317 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2203 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2318 InstructionMark im(this); | 2204 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
2319 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2320 emit_byte(0x67); | |
2321 emit_operand(dst, src); | |
2322 } | 2205 } |
2323 | 2206 |
2324 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | 2207 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { |
2325 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2208 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2326 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | 2209 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
2327 emit_byte(0x67); | |
2328 emit_byte(0xC0 | encode); | |
2329 } | 2210 } |
2330 | 2211 |
2331 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { | 2212 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2332 assert(VM_Version::supports_sse4_2(), ""); | 2213 assert(VM_Version::supports_sse4_2(), ""); |
2333 InstructionMark im(this); | 2214 InstructionMark im(this); |
2337 emit_byte(imm8); | 2218 emit_byte(imm8); |
2338 } | 2219 } |
2339 | 2220 |
2340 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | 2221 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { |
2341 assert(VM_Version::supports_sse4_2(), ""); | 2222 assert(VM_Version::supports_sse4_2(), ""); |
2342 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | 2223 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
2343 emit_byte(0x61); | 2224 emit_byte(0x61); |
2344 emit_byte(0xC0 | encode); | 2225 emit_byte(0xC0 | encode); |
2345 emit_byte(imm8); | 2226 emit_byte(imm8); |
2346 } | 2227 } |
2347 | 2228 |
2353 emit_operand(dst, src); | 2234 emit_operand(dst, src); |
2354 } | 2235 } |
2355 | 2236 |
2356 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | 2237 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { |
2357 assert(VM_Version::supports_sse4_1(), ""); | 2238 assert(VM_Version::supports_sse4_1(), ""); |
2358 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2239 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2359 emit_byte(0x30); | 2240 emit_byte(0x30); |
2360 emit_byte(0xC0 | encode); | 2241 emit_byte(0xC0 | encode); |
2361 } | 2242 } |
2362 | 2243 |
2363 // generic | 2244 // generic |
2454 | 2335 |
2455 void Assembler::prefix(Prefix p) { | 2336 void Assembler::prefix(Prefix p) { |
2456 a_byte(p); | 2337 a_byte(p); |
2457 } | 2338 } |
2458 | 2339 |
2459 void Assembler::por(XMMRegister dst, XMMRegister src) { | |
2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2461 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2462 emit_byte(0xEB); | |
2463 emit_byte(0xC0 | encode); | |
2464 } | |
2465 | |
2466 void Assembler::por(XMMRegister dst, Address src) { | |
2467 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2468 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2469 InstructionMark im(this); | |
2470 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2471 emit_byte(0xEB); | |
2472 emit_operand(dst, src); | |
2473 } | |
2474 | |
2475 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | 2340 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2476 assert(isByte(mode), "invalid value"); | 2341 assert(isByte(mode), "invalid value"); |
2477 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2478 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 2343 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
2479 emit_byte(0x70); | |
2480 emit_byte(0xC0 | encode); | |
2481 emit_byte(mode & 0xFF); | 2344 emit_byte(mode & 0xFF); |
2482 | 2345 |
2483 } | 2346 } |
2484 | 2347 |
2485 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | 2348 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { |
2494 } | 2357 } |
2495 | 2358 |
2496 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | 2359 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { |
2497 assert(isByte(mode), "invalid value"); | 2360 assert(isByte(mode), "invalid value"); |
2498 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2361 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2499 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); | 2362 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
2500 emit_byte(0x70); | |
2501 emit_byte(0xC0 | encode); | |
2502 emit_byte(mode & 0xFF); | 2363 emit_byte(mode & 0xFF); |
2503 } | 2364 } |
2504 | 2365 |
2505 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | 2366 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { |
2506 assert(isByte(mode), "invalid value"); | 2367 assert(isByte(mode), "invalid value"); |
2509 InstructionMark im(this); | 2370 InstructionMark im(this); |
2510 simd_prefix(dst, src, VEX_SIMD_F2); | 2371 simd_prefix(dst, src, VEX_SIMD_F2); |
2511 emit_byte(0x70); | 2372 emit_byte(0x70); |
2512 emit_operand(dst, src); | 2373 emit_operand(dst, src); |
2513 emit_byte(mode & 0xFF); | 2374 emit_byte(mode & 0xFF); |
2514 } | |
2515 | |
2516 void Assembler::psrlq(XMMRegister dst, int shift) { | |
2517 // Shift 64 bit value logically right by specified number of bits. | |
2518 // HMM Table D-1 says sse2 or mmx. | |
2519 // Do not confuse it with psrldq SSE2 instruction which | |
2520 // shifts 128 bit value in xmm register by number of bytes. | |
2521 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2522 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
2523 emit_byte(0x73); | |
2524 emit_byte(0xC0 | encode); | |
2525 emit_byte(shift); | |
2526 } | 2375 } |
2527 | 2376 |
2528 void Assembler::psrldq(XMMRegister dst, int shift) { | 2377 void Assembler::psrldq(XMMRegister dst, int shift) { |
2529 // Shift 128 bit value in xmm register by number of bytes. | 2378 // Shift 128 bit value in xmm register by number of bytes. |
2530 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2379 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2543 emit_operand(dst, src); | 2392 emit_operand(dst, src); |
2544 } | 2393 } |
2545 | 2394 |
2546 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | 2395 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2547 assert(VM_Version::supports_sse4_1(), ""); | 2396 assert(VM_Version::supports_sse4_1(), ""); |
2548 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | 2397 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
2549 emit_byte(0x17); | 2398 emit_byte(0x17); |
2550 emit_byte(0xC0 | encode); | 2399 emit_byte(0xC0 | encode); |
2551 } | 2400 } |
2552 | 2401 |
2553 void Assembler::punpcklbw(XMMRegister dst, Address src) { | 2402 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2554 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2403 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2555 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2404 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2556 InstructionMark im(this); | 2405 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
2557 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2558 emit_byte(0x60); | |
2559 emit_operand(dst, src); | |
2560 } | 2406 } |
2561 | 2407 |
2562 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | 2408 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2563 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2409 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2564 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | 2410 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
2565 emit_byte(0x60); | |
2566 emit_byte(0xC0 | encode); | |
2567 } | 2411 } |
2568 | 2412 |
2569 void Assembler::punpckldq(XMMRegister dst, Address src) { | 2413 void Assembler::punpckldq(XMMRegister dst, Address src) { |
2570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2414 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2571 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | 2415 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2572 InstructionMark im(this); | 2416 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
2573 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2574 emit_byte(0x62); | |
2575 emit_operand(dst, src); | |
2576 } | 2417 } |
2577 | 2418 |
2578 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | 2419 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { |
2579 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2420 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2580 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | 2421 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
2581 emit_byte(0x62); | |
2582 emit_byte(0xC0 | encode); | |
2583 } | 2422 } |
2584 | 2423 |
2585 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { | 2424 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
2586 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2425 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2587 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | 2426 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
2588 emit_byte(0x6C); | |
2589 emit_byte(0xC0 | encode); | |
2590 } | 2427 } |
2591 | 2428 |
2592 void Assembler::push(int32_t imm32) { | 2429 void Assembler::push(int32_t imm32) { |
2593 // in 64bits we push 64bits onto the stack but only | 2430 // in 64bits we push 64bits onto the stack but only |
2594 // take a 32bit immediate | 2431 // take a 32bit immediate |
2613 prefix(src); | 2450 prefix(src); |
2614 emit_byte(0xFF); | 2451 emit_byte(0xFF); |
2615 emit_operand(rsi, src); | 2452 emit_operand(rsi, src); |
2616 } | 2453 } |
2617 #endif | 2454 #endif |
2618 | |
2619 void Assembler::pxor(XMMRegister dst, Address src) { | |
2620 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2621 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
2622 InstructionMark im(this); | |
2623 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
2624 emit_byte(0xEF); | |
2625 emit_operand(dst, src); | |
2626 } | |
2627 | |
2628 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
2629 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2630 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | |
2631 emit_byte(0xEF); | |
2632 emit_byte(0xC0 | encode); | |
2633 } | |
2634 | 2455 |
2635 void Assembler::rcll(Register dst, int imm8) { | 2456 void Assembler::rcll(Register dst, int imm8) { |
2636 assert(isShiftCount(imm8), "illegal shift count"); | 2457 assert(isShiftCount(imm8), "illegal shift count"); |
2637 int encode = prefix_and_encode(dst->encoding()); | 2458 int encode = prefix_and_encode(dst->encoding()); |
2638 if (imm8 == 1) { | 2459 if (imm8 == 1) { |
2788 emit_byte(0xA5); | 2609 emit_byte(0xA5); |
2789 } | 2610 } |
2790 | 2611 |
2791 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2612 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2792 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2613 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 2614 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2794 emit_byte(0x51); | |
2795 emit_byte(0xC0 | encode); | |
2796 } | 2615 } |
2797 | 2616 |
2798 void Assembler::sqrtsd(XMMRegister dst, Address src) { | 2617 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2799 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2618 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2800 InstructionMark im(this); | 2619 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2801 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
2802 emit_byte(0x51); | |
2803 emit_operand(dst, src); | |
2804 } | 2620 } |
2805 | 2621 |
2806 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | 2622 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { |
2807 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2623 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2808 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 2624 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2809 emit_byte(0x51); | |
2810 emit_byte(0xC0 | encode); | |
2811 } | 2625 } |
2812 | 2626 |
2813 void Assembler::sqrtss(XMMRegister dst, Address src) { | 2627 void Assembler::sqrtss(XMMRegister dst, Address src) { |
2814 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2628 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2815 InstructionMark im(this); | 2629 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2816 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
2817 emit_byte(0x51); | |
2818 emit_operand(dst, src); | |
2819 } | 2630 } |
2820 | 2631 |
2821 void Assembler::stmxcsr( Address dst) { | 2632 void Assembler::stmxcsr( Address dst) { |
2822 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2633 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2823 InstructionMark im(this); | 2634 InstructionMark im(this); |
2863 emit_arith(0x2B, 0xC0, dst, src); | 2674 emit_arith(0x2B, 0xC0, dst, src); |
2864 } | 2675 } |
2865 | 2676 |
2866 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | 2677 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2867 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2678 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); | 2679 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
2869 emit_byte(0x5C); | |
2870 emit_byte(0xC0 | encode); | |
2871 } | 2680 } |
2872 | 2681 |
2873 void Assembler::subsd(XMMRegister dst, Address src) { | 2682 void Assembler::subsd(XMMRegister dst, Address src) { |
2874 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2683 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2875 InstructionMark im(this); | 2684 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
2876 simd_prefix(dst, dst, src, VEX_SIMD_F2); | |
2877 emit_byte(0x5C); | |
2878 emit_operand(dst, src); | |
2879 } | 2685 } |
2880 | 2686 |
2881 void Assembler::subss(XMMRegister dst, XMMRegister src) { | 2687 void Assembler::subss(XMMRegister dst, XMMRegister src) { |
2882 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2688 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); | 2689 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
2884 emit_byte(0x5C); | |
2885 emit_byte(0xC0 | encode); | |
2886 } | 2690 } |
2887 | 2691 |
2888 void Assembler::subss(XMMRegister dst, Address src) { | 2692 void Assembler::subss(XMMRegister dst, Address src) { |
2889 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2693 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2890 InstructionMark im(this); | 2694 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
2891 simd_prefix(dst, dst, src, VEX_SIMD_F3); | |
2892 emit_byte(0x5C); | |
2893 emit_operand(dst, src); | |
2894 } | 2695 } |
2895 | 2696 |
2896 void Assembler::testb(Register dst, int imm8) { | 2697 void Assembler::testb(Register dst, int imm8) { |
2897 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | 2698 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); |
2898 (void) prefix_and_encode(dst->encoding(), true); | 2699 (void) prefix_and_encode(dst->encoding(), true); |
2926 emit_operand(dst, src); | 2727 emit_operand(dst, src); |
2927 } | 2728 } |
2928 | 2729 |
2929 void Assembler::ucomisd(XMMRegister dst, Address src) { | 2730 void Assembler::ucomisd(XMMRegister dst, Address src) { |
2930 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2731 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2931 InstructionMark im(this); | 2732 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
2932 simd_prefix(dst, src, VEX_SIMD_66); | |
2933 emit_byte(0x2E); | |
2934 emit_operand(dst, src); | |
2935 } | 2733 } |
2936 | 2734 |
2937 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | 2735 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2938 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 2736 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
2939 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); | 2737 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
2940 emit_byte(0x2E); | |
2941 emit_byte(0xC0 | encode); | |
2942 } | 2738 } |
2943 | 2739 |
2944 void Assembler::ucomiss(XMMRegister dst, Address src) { | 2740 void Assembler::ucomiss(XMMRegister dst, Address src) { |
2945 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2741 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2946 InstructionMark im(this); | 2742 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
2947 simd_prefix(dst, src, VEX_SIMD_NONE); | |
2948 emit_byte(0x2E); | |
2949 emit_operand(dst, src); | |
2950 } | 2743 } |
2951 | 2744 |
2952 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | 2745 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { |
2953 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 2746 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
2954 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE); | 2747 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
2955 emit_byte(0x2E); | |
2956 emit_byte(0xC0 | encode); | |
2957 } | 2748 } |
2958 | 2749 |
2959 | 2750 |
2960 void Assembler::xaddl(Address dst, Register src) { | 2751 void Assembler::xaddl(Address dst, Register src) { |
2961 InstructionMark im(this); | 2752 InstructionMark im(this); |
2993 void Assembler::xorl(Register dst, Register src) { | 2784 void Assembler::xorl(Register dst, Register src) { |
2994 (void) prefix_and_encode(dst->encoding(), src->encoding()); | 2785 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
2995 emit_arith(0x33, 0xC0, dst, src); | 2786 emit_arith(0x33, 0xC0, dst, src); |
2996 } | 2787 } |
2997 | 2788 |
2789 | |
2790 // AVX 3-operands scalar float-point arithmetic instructions | |
2791 | |
2792 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2793 assert(VM_Version::supports_avx(), ""); | |
2794 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2795 } | |
2796 | |
2797 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2798 assert(VM_Version::supports_avx(), ""); | |
2799 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2800 } | |
2801 | |
2802 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { | |
2803 assert(VM_Version::supports_avx(), ""); | |
2804 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2805 } | |
2806 | |
2807 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2808 assert(VM_Version::supports_avx(), ""); | |
2809 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2810 } | |
2811 | |
2812 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2813 assert(VM_Version::supports_avx(), ""); | |
2814 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2815 } | |
2816 | |
2817 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2818 assert(VM_Version::supports_avx(), ""); | |
2819 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2820 } | |
2821 | |
2822 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { | |
2823 assert(VM_Version::supports_avx(), ""); | |
2824 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2825 } | |
2826 | |
2827 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2828 assert(VM_Version::supports_avx(), ""); | |
2829 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2830 } | |
2831 | |
2832 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2833 assert(VM_Version::supports_avx(), ""); | |
2834 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2835 } | |
2836 | |
2837 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2838 assert(VM_Version::supports_avx(), ""); | |
2839 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2840 } | |
2841 | |
2842 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { | |
2843 assert(VM_Version::supports_avx(), ""); | |
2844 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2845 } | |
2846 | |
2847 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2848 assert(VM_Version::supports_avx(), ""); | |
2849 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2850 } | |
2851 | |
2852 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { | |
2853 assert(VM_Version::supports_avx(), ""); | |
2854 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2855 } | |
2856 | |
2857 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2858 assert(VM_Version::supports_avx(), ""); | |
2859 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); | |
2860 } | |
2861 | |
2862 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { | |
2863 assert(VM_Version::supports_avx(), ""); | |
2864 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2865 } | |
2866 | |
2867 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
2868 assert(VM_Version::supports_avx(), ""); | |
2869 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); | |
2870 } | |
2871 | |
2872 //====================VECTOR ARITHMETIC===================================== | |
2873 | |
2874 // Float-point vector arithmetic | |
2875 | |
2876 void Assembler::addpd(XMMRegister dst, XMMRegister src) { | |
2877 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2878 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); | |
2879 } | |
2880 | |
2881 void Assembler::addps(XMMRegister dst, XMMRegister src) { | |
2882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2883 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); | |
2884 } | |
2885 | |
2886 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2887 assert(VM_Version::supports_avx(), ""); | |
2888 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); | |
2889 } | |
2890 | |
2891 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2892 assert(VM_Version::supports_avx(), ""); | |
2893 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2894 } | |
2895 | |
2896 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2897 assert(VM_Version::supports_avx(), ""); | |
2898 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); | |
2899 } | |
2900 | |
2901 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2902 assert(VM_Version::supports_avx(), ""); | |
2903 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2904 } | |
2905 | |
2906 void Assembler::subpd(XMMRegister dst, XMMRegister src) { | |
2907 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2908 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); | |
2909 } | |
2910 | |
2911 void Assembler::subps(XMMRegister dst, XMMRegister src) { | |
2912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2913 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); | |
2914 } | |
2915 | |
2916 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2917 assert(VM_Version::supports_avx(), ""); | |
2918 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); | |
2919 } | |
2920 | |
2921 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2922 assert(VM_Version::supports_avx(), ""); | |
2923 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2924 } | |
2925 | |
2926 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2927 assert(VM_Version::supports_avx(), ""); | |
2928 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); | |
2929 } | |
2930 | |
2931 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2932 assert(VM_Version::supports_avx(), ""); | |
2933 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2934 } | |
2935 | |
2936 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { | |
2937 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2938 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); | |
2939 } | |
2940 | |
2941 void Assembler::mulps(XMMRegister dst, XMMRegister src) { | |
2942 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2943 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); | |
2944 } | |
2945 | |
2946 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2947 assert(VM_Version::supports_avx(), ""); | |
2948 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); | |
2949 } | |
2950 | |
2951 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2952 assert(VM_Version::supports_avx(), ""); | |
2953 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2954 } | |
2955 | |
2956 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2957 assert(VM_Version::supports_avx(), ""); | |
2958 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); | |
2959 } | |
2960 | |
2961 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2962 assert(VM_Version::supports_avx(), ""); | |
2963 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2964 } | |
2965 | |
2966 void Assembler::divpd(XMMRegister dst, XMMRegister src) { | |
2967 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2968 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); | |
2969 } | |
2970 | |
2971 void Assembler::divps(XMMRegister dst, XMMRegister src) { | |
2972 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2973 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); | |
2974 } | |
2975 | |
2976 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2977 assert(VM_Version::supports_avx(), ""); | |
2978 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); | |
2979 } | |
2980 | |
2981 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
2982 assert(VM_Version::supports_avx(), ""); | |
2983 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2984 } | |
2985 | |
2986 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2987 assert(VM_Version::supports_avx(), ""); | |
2988 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); | |
2989 } | |
2990 | |
2991 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
2992 assert(VM_Version::supports_avx(), ""); | |
2993 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); | |
2994 } | |
2995 | |
2996 void Assembler::andpd(XMMRegister dst, XMMRegister src) { | |
2997 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2998 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); | |
2999 } | |
3000 | |
3001 void Assembler::andps(XMMRegister dst, XMMRegister src) { | |
3002 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3003 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); | |
3004 } | |
3005 | |
3006 void Assembler::andps(XMMRegister dst, Address src) { | |
3007 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3008 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); | |
3009 } | |
3010 | |
3011 void Assembler::andpd(XMMRegister dst, Address src) { | |
3012 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3013 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); | |
3014 } | |
3015 | |
3016 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3017 assert(VM_Version::supports_avx(), ""); | |
3018 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); | |
3019 } | |
3020 | |
3021 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3022 assert(VM_Version::supports_avx(), ""); | |
3023 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); | |
3024 } | |
3025 | |
3026 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3027 assert(VM_Version::supports_avx(), ""); | |
3028 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); | |
3029 } | |
3030 | |
3031 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3032 assert(VM_Version::supports_avx(), ""); | |
3033 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); | |
3034 } | |
3035 | |
2998 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | 3036 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2999 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3037 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66); | 3038 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
3001 emit_byte(0x57); | 3039 } |
3002 emit_byte(0xC0 | encode); | 3040 |
3041 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
3042 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3043 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); | |
3003 } | 3044 } |
3004 | 3045 |
3005 void Assembler::xorpd(XMMRegister dst, Address src) { | 3046 void Assembler::xorpd(XMMRegister dst, Address src) { |
3006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | 3047 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
3007 InstructionMark im(this); | 3048 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
3008 simd_prefix(dst, dst, src, VEX_SIMD_66); | |
3009 emit_byte(0x57); | |
3010 emit_operand(dst, src); | |
3011 } | |
3012 | |
3013 | |
3014 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
3015 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE); | |
3017 emit_byte(0x57); | |
3018 emit_byte(0xC0 | encode); | |
3019 } | 3049 } |
3020 | 3050 |
3021 void Assembler::xorps(XMMRegister dst, Address src) { | 3051 void Assembler::xorps(XMMRegister dst, Address src) { |
3022 NOT_LP64(assert(VM_Version::supports_sse(), "")); | 3052 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
3023 InstructionMark im(this); | 3053 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
3024 simd_prefix(dst, dst, src, VEX_SIMD_NONE); | |
3025 emit_byte(0x57); | |
3026 emit_operand(dst, src); | |
3027 } | |
3028 | |
3029 // AVX 3-operands non destructive source instructions (encoded with VEX prefix) | |
3030 | |
3031 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3032 assert(VM_Version::supports_avx(), ""); | |
3033 InstructionMark im(this); | |
3034 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3035 emit_byte(0x58); | |
3036 emit_operand(dst, src); | |
3037 } | |
3038 | |
3039 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3040 assert(VM_Version::supports_avx(), ""); | |
3041 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3042 emit_byte(0x58); | |
3043 emit_byte(0xC0 | encode); | |
3044 } | |
3045 | |
3046 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { | |
3047 assert(VM_Version::supports_avx(), ""); | |
3048 InstructionMark im(this); | |
3049 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3050 emit_byte(0x58); | |
3051 emit_operand(dst, src); | |
3052 } | |
3053 | |
3054 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3055 assert(VM_Version::supports_avx(), ""); | |
3056 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3057 emit_byte(0x58); | |
3058 emit_byte(0xC0 | encode); | |
3059 } | |
3060 | |
3061 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) { | |
3062 assert(VM_Version::supports_avx(), ""); | |
3063 InstructionMark im(this); | |
3064 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
3065 emit_byte(0x54); | |
3066 emit_operand(dst, src); | |
3067 } | |
3068 | |
3069 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) { | |
3070 assert(VM_Version::supports_avx(), ""); | |
3071 InstructionMark im(this); | |
3072 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
3073 emit_byte(0x54); | |
3074 emit_operand(dst, src); | |
3075 } | |
3076 | |
3077 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3078 assert(VM_Version::supports_avx(), ""); | |
3079 InstructionMark im(this); | |
3080 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3081 emit_byte(0x5E); | |
3082 emit_operand(dst, src); | |
3083 } | |
3084 | |
3085 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3086 assert(VM_Version::supports_avx(), ""); | |
3087 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3088 emit_byte(0x5E); | |
3089 emit_byte(0xC0 | encode); | |
3090 } | |
3091 | |
3092 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { | |
3093 assert(VM_Version::supports_avx(), ""); | |
3094 InstructionMark im(this); | |
3095 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3096 emit_byte(0x5E); | |
3097 emit_operand(dst, src); | |
3098 } | |
3099 | |
3100 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3101 assert(VM_Version::supports_avx(), ""); | |
3102 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3103 emit_byte(0x5E); | |
3104 emit_byte(0xC0 | encode); | |
3105 } | |
3106 | |
3107 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3108 assert(VM_Version::supports_avx(), ""); | |
3109 InstructionMark im(this); | |
3110 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3111 emit_byte(0x59); | |
3112 emit_operand(dst, src); | |
3113 } | |
3114 | |
3115 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3116 assert(VM_Version::supports_avx(), ""); | |
3117 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3118 emit_byte(0x59); | |
3119 emit_byte(0xC0 | encode); | |
3120 } | |
3121 | |
3122 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { | |
3123 InstructionMark im(this); | |
3124 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3125 emit_byte(0x59); | |
3126 emit_operand(dst, src); | |
3127 } | |
3128 | |
3129 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3130 assert(VM_Version::supports_avx(), ""); | |
3131 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3132 emit_byte(0x59); | |
3133 emit_byte(0xC0 | encode); | |
3134 } | |
3135 | |
3136 | |
3137 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { | |
3138 assert(VM_Version::supports_avx(), ""); | |
3139 InstructionMark im(this); | |
3140 vex_prefix(dst, nds, src, VEX_SIMD_F2); | |
3141 emit_byte(0x5C); | |
3142 emit_operand(dst, src); | |
3143 } | |
3144 | |
3145 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3146 assert(VM_Version::supports_avx(), ""); | |
3147 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2); | |
3148 emit_byte(0x5C); | |
3149 emit_byte(0xC0 | encode); | |
3150 } | |
3151 | |
3152 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { | |
3153 assert(VM_Version::supports_avx(), ""); | |
3154 InstructionMark im(this); | |
3155 vex_prefix(dst, nds, src, VEX_SIMD_F3); | |
3156 emit_byte(0x5C); | |
3157 emit_operand(dst, src); | |
3158 } | |
3159 | |
3160 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { | |
3161 assert(VM_Version::supports_avx(), ""); | |
3162 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3); | |
3163 emit_byte(0x5C); | |
3164 emit_byte(0xC0 | encode); | |
3165 } | |
3166 | |
3167 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) { | |
3168 assert(VM_Version::supports_avx(), ""); | |
3169 InstructionMark im(this); | |
3170 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector | |
3171 emit_byte(0x57); | |
3172 emit_operand(dst, src); | |
3173 } | 3054 } |
3174 | 3055 |
3175 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | 3056 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3176 assert(VM_Version::supports_avx(), ""); | 3057 assert(VM_Version::supports_avx(), ""); |
3177 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256); | 3058 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
3178 emit_byte(0x57); | |
3179 emit_byte(0xC0 | encode); | |
3180 } | |
3181 | |
3182 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) { | |
3183 assert(VM_Version::supports_avx(), ""); | |
3184 InstructionMark im(this); | |
3185 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector | |
3186 emit_byte(0x57); | |
3187 emit_operand(dst, src); | |
3188 } | 3059 } |
3189 | 3060 |
3190 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | 3061 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3191 assert(VM_Version::supports_avx(), ""); | 3062 assert(VM_Version::supports_avx(), ""); |
3192 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256); | 3063 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
3193 emit_byte(0x57); | 3064 } |
3065 | |
3066 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3067 assert(VM_Version::supports_avx(), ""); | |
3068 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); | |
3069 } | |
3070 | |
3071 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3072 assert(VM_Version::supports_avx(), ""); | |
3073 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); | |
3074 } | |
3075 | |
3076 | |
3077 // Integer vector arithmetic | |
3078 void Assembler::paddb(XMMRegister dst, XMMRegister src) { | |
3079 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3080 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); | |
3081 } | |
3082 | |
3083 void Assembler::paddw(XMMRegister dst, XMMRegister src) { | |
3084 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3085 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); | |
3086 } | |
3087 | |
3088 void Assembler::paddd(XMMRegister dst, XMMRegister src) { | |
3089 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3090 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); | |
3091 } | |
3092 | |
3093 void Assembler::paddq(XMMRegister dst, XMMRegister src) { | |
3094 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3095 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); | |
3096 } | |
3097 | |
3098 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3099 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3100 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); | |
3101 } | |
3102 | |
3103 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3104 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3105 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); | |
3106 } | |
3107 | |
3108 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3109 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3110 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); | |
3111 } | |
3112 | |
3113 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3114 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3115 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); | |
3116 } | |
3117 | |
3118 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3119 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3120 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); | |
3121 } | |
3122 | |
3123 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3124 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3125 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); | |
3126 } | |
3127 | |
3128 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3129 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3130 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); | |
3131 } | |
3132 | |
3133 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3134 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3135 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); | |
3136 } | |
3137 | |
3138 void Assembler::psubb(XMMRegister dst, XMMRegister src) { | |
3139 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3140 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); | |
3141 } | |
3142 | |
3143 void Assembler::psubw(XMMRegister dst, XMMRegister src) { | |
3144 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3145 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); | |
3146 } | |
3147 | |
3148 void Assembler::psubd(XMMRegister dst, XMMRegister src) { | |
3149 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3150 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); | |
3151 } | |
3152 | |
3153 void Assembler::psubq(XMMRegister dst, XMMRegister src) { | |
3154 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3155 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); | |
3156 } | |
3157 | |
3158 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3159 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3160 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); | |
3161 } | |
3162 | |
3163 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3164 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3165 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); | |
3166 } | |
3167 | |
3168 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3169 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3170 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); | |
3171 } | |
3172 | |
3173 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3174 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3175 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); | |
3176 } | |
3177 | |
3178 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3179 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3180 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); | |
3181 } | |
3182 | |
3183 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3184 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3185 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); | |
3186 } | |
3187 | |
3188 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3189 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3190 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); | |
3191 } | |
3192 | |
3193 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3194 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3195 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); | |
3196 } | |
3197 | |
3198 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { | |
3199 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3200 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); | |
3201 } | |
3202 | |
3203 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { | |
3204 assert(VM_Version::supports_sse4_1(), ""); | |
3205 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
3206 emit_byte(0x40); | |
3194 emit_byte(0xC0 | encode); | 3207 emit_byte(0xC0 | encode); |
3195 } | 3208 } |
3196 | 3209 |
3210 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3211 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3212 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); | |
3213 } | |
3214 | |
3215 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3216 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3217 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); | |
3218 emit_byte(0x40); | |
3219 emit_byte(0xC0 | encode); | |
3220 } | |
3221 | |
3222 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3223 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3224 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); | |
3225 } | |
3226 | |
3227 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3228 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3229 InstructionMark im(this); | |
3230 int dst_enc = dst->encoding(); | |
3231 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
3232 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); | |
3233 emit_byte(0x40); | |
3234 emit_operand(dst, src); | |
3235 } | |
3236 | |
3237 // Shift packed integers left by specified number of bits. | |
3238 void Assembler::psllw(XMMRegister dst, int shift) { | |
3239 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3240 // XMM6 is for /6 encoding: 66 0F 71 /6 ib | |
3241 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | |
3242 emit_byte(0x71); | |
3243 emit_byte(0xC0 | encode); | |
3244 emit_byte(shift & 0xFF); | |
3245 } | |
3246 | |
3247 void Assembler::pslld(XMMRegister dst, int shift) { | |
3248 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3249 // XMM6 is for /6 encoding: 66 0F 72 /6 ib | |
3250 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | |
3251 emit_byte(0x72); | |
3252 emit_byte(0xC0 | encode); | |
3253 emit_byte(shift & 0xFF); | |
3254 } | |
3255 | |
3256 void Assembler::psllq(XMMRegister dst, int shift) { | |
3257 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3258 // XMM6 is for /6 encoding: 66 0F 73 /6 ib | |
3259 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); | |
3260 emit_byte(0x73); | |
3261 emit_byte(0xC0 | encode); | |
3262 emit_byte(shift & 0xFF); | |
3263 } | |
3264 | |
3265 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { | |
3266 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3267 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); | |
3268 } | |
3269 | |
3270 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { | |
3271 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3272 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); | |
3273 } | |
3274 | |
3275 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { | |
3276 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3277 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); | |
3278 } | |
3279 | |
3280 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3281 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3282 // XMM6 is for /6 encoding: 66 0F 71 /6 ib | |
3283 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); | |
3284 emit_byte(shift & 0xFF); | |
3285 } | |
3286 | |
3287 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3288 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3289 // XMM6 is for /6 encoding: 66 0F 72 /6 ib | |
3290 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); | |
3291 emit_byte(shift & 0xFF); | |
3292 } | |
3293 | |
3294 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3295 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3296 // XMM6 is for /6 encoding: 66 0F 73 /6 ib | |
3297 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); | |
3298 emit_byte(shift & 0xFF); | |
3299 } | |
3300 | |
3301 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3302 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3303 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); | |
3304 } | |
3305 | |
3306 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3307 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3308 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); | |
3309 } | |
3310 | |
3311 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3312 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3313 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); | |
3314 } | |
3315 | |
3316 // Shift packed integers logically right by specified number of bits. | |
3317 void Assembler::psrlw(XMMRegister dst, int shift) { | |
3318 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3319 // XMM2 is for /2 encoding: 66 0F 71 /2 ib | |
3320 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
3321 emit_byte(0x71); | |
3322 emit_byte(0xC0 | encode); | |
3323 emit_byte(shift & 0xFF); | |
3324 } | |
3325 | |
3326 void Assembler::psrld(XMMRegister dst, int shift) { | |
3327 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3328 // XMM2 is for /2 encoding: 66 0F 72 /2 ib | |
3329 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
3330 emit_byte(0x72); | |
3331 emit_byte(0xC0 | encode); | |
3332 emit_byte(shift & 0xFF); | |
3333 } | |
3334 | |
3335 void Assembler::psrlq(XMMRegister dst, int shift) { | |
3336 // Do not confuse it with psrldq SSE2 instruction which | |
3337 // shifts 128 bit value in xmm register by number of bytes. | |
3338 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3339 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |
3340 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); | |
3341 emit_byte(0x73); | |
3342 emit_byte(0xC0 | encode); | |
3343 emit_byte(shift & 0xFF); | |
3344 } | |
3345 | |
3346 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { | |
3347 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3348 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); | |
3349 } | |
3350 | |
3351 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { | |
3352 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3353 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); | |
3354 } | |
3355 | |
3356 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { | |
3357 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3358 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); | |
3359 } | |
3360 | |
3361 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3362 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3363 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |
3364 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); | |
3365 emit_byte(shift & 0xFF); | |
3366 } | |
3367 | |
3368 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3369 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3370 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |
3371 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); | |
3372 emit_byte(shift & 0xFF); | |
3373 } | |
3374 | |
3375 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3376 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3377 // XMM2 is for /2 encoding: 66 0F 73 /2 ib | |
3378 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); | |
3379 emit_byte(shift & 0xFF); | |
3380 } | |
3381 | |
3382 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3383 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3384 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); | |
3385 } | |
3386 | |
3387 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3388 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3389 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); | |
3390 } | |
3391 | |
3392 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3393 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3394 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); | |
3395 } | |
3396 | |
3397 // Shift packed integers arithmetically right by specified number of bits. | |
3398 void Assembler::psraw(XMMRegister dst, int shift) { | |
3399 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3400 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |
3401 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); | |
3402 emit_byte(0x71); | |
3403 emit_byte(0xC0 | encode); | |
3404 emit_byte(shift & 0xFF); | |
3405 } | |
3406 | |
3407 void Assembler::psrad(XMMRegister dst, int shift) { | |
3408 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3409 // XMM4 is for /4 encoding: 66 0F 72 /4 ib | |
3410 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); | |
3411 emit_byte(0x72); | |
3412 emit_byte(0xC0 | encode); | |
3413 emit_byte(shift & 0xFF); | |
3414 } | |
3415 | |
3416 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { | |
3417 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3418 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); | |
3419 } | |
3420 | |
3421 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { | |
3422 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3423 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); | |
3424 } | |
3425 | |
3426 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3427 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3428 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |
3429 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); | |
3430 emit_byte(shift & 0xFF); | |
3431 } | |
3432 | |
3433 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { | |
3434 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3435 // XMM4 is for /4 encoding: 66 0F 71 /4 ib | |
3436 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); | |
3437 emit_byte(shift & 0xFF); | |
3438 } | |
3439 | |
3440 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3441 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3442 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); | |
3443 } | |
3444 | |
3445 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { | |
3446 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3447 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); | |
3448 } | |
3449 | |
3450 | |
3451 // AND packed integers | |
3452 void Assembler::pand(XMMRegister dst, XMMRegister src) { | |
3453 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3454 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); | |
3455 } | |
3456 | |
3457 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3458 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3459 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); | |
3460 } | |
3461 | |
3462 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3463 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3464 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); | |
3465 } | |
3466 | |
3467 void Assembler::por(XMMRegister dst, XMMRegister src) { | |
3468 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3469 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); | |
3470 } | |
3471 | |
3472 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | |
3473 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3474 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); | |
3475 } | |
3476 | |
3477 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { | |
3478 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3479 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); | |
3480 } | |
3481 | |
3482 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
3483 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3484 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); | |
3485 } | |
3486 | |
3197 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { | 3487 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
3198 assert(VM_Version::supports_avx2() || (!vector256) && VM_Version::supports_avx(), ""); | 3488 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
3199 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256); | 3489 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
3200 emit_byte(0xEF); | 3490 } |
3201 emit_byte(0xC0 | encode); | 3491 |
3202 } | 3492 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
3493 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); | |
3494 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); | |
3495 } | |
3496 | |
3203 | 3497 |
3204 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { | 3498 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3205 assert(VM_Version::supports_avx(), ""); | 3499 assert(VM_Version::supports_avx(), ""); |
3206 bool vector256 = true; | 3500 bool vector256 = true; |
3207 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | 3501 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
3801 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | 4095 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); |
3802 } else { | 4096 } else { |
3803 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | 4097 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); |
3804 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | 4098 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); |
3805 } | 4099 } |
4100 } | |
4101 | |
4102 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { | |
4103 InstructionMark im(this); | |
4104 simd_prefix(dst, dst, src, pre); | |
4105 emit_byte(opcode); | |
4106 emit_operand(dst, src); | |
4107 } | |
4108 | |
4109 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { | |
4110 int encode = simd_prefix_and_encode(dst, dst, src, pre); | |
4111 emit_byte(opcode); | |
4112 emit_byte(0xC0 | encode); | |
4113 } | |
4114 | |
4115 // Versions with no second source register (non-destructive source). | |
4116 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { | |
4117 InstructionMark im(this); | |
4118 simd_prefix(dst, xnoreg, src, pre); | |
4119 emit_byte(opcode); | |
4120 emit_operand(dst, src); | |
4121 } | |
4122 | |
4123 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { | |
4124 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); | |
4125 emit_byte(opcode); | |
4126 emit_byte(0xC0 | encode); | |
4127 } | |
4128 | |
4129 // 3-operands AVX instructions | |
4130 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, | |
4131 Address src, VexSimdPrefix pre, bool vector256) { | |
4132 InstructionMark im(this); | |
4133 vex_prefix(dst, nds, src, pre, vector256); | |
4134 emit_byte(opcode); | |
4135 emit_operand(dst, src); | |
4136 } | |
4137 | |
4138 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, | |
4139 XMMRegister src, VexSimdPrefix pre, bool vector256) { | |
4140 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); | |
4141 emit_byte(opcode); | |
4142 emit_byte(0xC0 | encode); | |
3806 } | 4143 } |
3807 | 4144 |
3808 #ifndef _LP64 | 4145 #ifndef _LP64 |
3809 | 4146 |
3810 void Assembler::incl(Register dst) { | 4147 void Assembler::incl(Register dst) { |
7966 lea(rscratch1, src); | 8303 lea(rscratch1, src); |
7967 vaddss(dst, nds, Address(rscratch1, 0)); | 8304 vaddss(dst, nds, Address(rscratch1, 0)); |
7968 } | 8305 } |
7969 } | 8306 } |
7970 | 8307 |
7971 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | 8308 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
7972 if (reachable(src)) { | 8309 if (reachable(src)) { |
7973 vandpd(dst, nds, as_Address(src)); | 8310 vandpd(dst, nds, as_Address(src), vector256); |
7974 } else { | 8311 } else { |
7975 lea(rscratch1, src); | 8312 lea(rscratch1, src); |
7976 vandpd(dst, nds, Address(rscratch1, 0)); | 8313 vandpd(dst, nds, Address(rscratch1, 0), vector256); |
7977 } | 8314 } |
7978 } | 8315 } |
7979 | 8316 |
7980 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | 8317 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
7981 if (reachable(src)) { | 8318 if (reachable(src)) { |
7982 vandps(dst, nds, as_Address(src)); | 8319 vandps(dst, nds, as_Address(src), vector256); |
7983 } else { | 8320 } else { |
7984 lea(rscratch1, src); | 8321 lea(rscratch1, src); |
7985 vandps(dst, nds, Address(rscratch1, 0)); | 8322 vandps(dst, nds, Address(rscratch1, 0), vector256); |
7986 } | 8323 } |
7987 } | 8324 } |
7988 | 8325 |
7989 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | 8326 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { |
7990 if (reachable(src)) { | 8327 if (reachable(src)) { |
8038 lea(rscratch1, src); | 8375 lea(rscratch1, src); |
8039 vsubss(dst, nds, Address(rscratch1, 0)); | 8376 vsubss(dst, nds, Address(rscratch1, 0)); |
8040 } | 8377 } |
8041 } | 8378 } |
8042 | 8379 |
8043 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | 8380 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
8044 if (reachable(src)) { | 8381 if (reachable(src)) { |
8045 vxorpd(dst, nds, as_Address(src)); | 8382 vxorpd(dst, nds, as_Address(src), vector256); |
8046 } else { | 8383 } else { |
8047 lea(rscratch1, src); | 8384 lea(rscratch1, src); |
8048 vxorpd(dst, nds, Address(rscratch1, 0)); | 8385 vxorpd(dst, nds, Address(rscratch1, 0), vector256); |
8049 } | 8386 } |
8050 } | 8387 } |
8051 | 8388 |
8052 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | 8389 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { |
8053 if (reachable(src)) { | 8390 if (reachable(src)) { |
8054 vxorps(dst, nds, as_Address(src)); | 8391 vxorps(dst, nds, as_Address(src), vector256); |
8055 } else { | 8392 } else { |
8056 lea(rscratch1, src); | 8393 lea(rscratch1, src); |
8057 vxorps(dst, nds, Address(rscratch1, 0)); | 8394 vxorps(dst, nds, Address(rscratch1, 0), vector256); |
8058 } | 8395 } |
8059 } | 8396 } |
8060 | 8397 |
8061 | 8398 |
8062 ////////////////////////////////////////////////////////////////////////////////// | 8399 ////////////////////////////////////////////////////////////////////////////////// |