Mercurial > hg > graal-jvmci-8
comparison src/share/vm/utilities/globalDefinitions.hpp @ 14452:c6d7e7406136
8029101: PPC64 (part 211): ordering of Independent Reads of Independent Writes
Reviewed-by: dholmes, kvn
Contributed-by: martin.doerr@sap.com
author | goetz |
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date | Thu, 16 Jan 2014 14:25:51 +0100 |
parents | da862781b584 |
children | 8a9bb7821e28 62c54fcc0a35 |
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14451:b858620b0081 | 14452:c6d7e7406136 |
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394 * the platform specific globalDefinitions (above) | 394 * the platform specific globalDefinitions (above) |
395 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0 | 395 * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0 |
396 */ | 396 */ |
397 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED | 397 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED |
398 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 | 398 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 |
399 #endif | |
400 | |
401 // To assure the IRIW property on processors that are not multiple copy | |
402 // atomic, sync instructions must be issued between volatile reads to | |
403 // assure their ordering, instead of after volatile stores. | |
404 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" | |
405 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) | |
406 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC | |
407 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; | |
408 #else | |
409 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; | |
399 #endif | 410 #endif |
400 | 411 |
401 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. | 412 // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. |
402 // Note: this value must be a power of 2 | 413 // Note: this value must be a power of 2 |
403 | 414 |