Mercurial > hg > graal-jvmci-8

comparison src/cpu/x86/vm/assembler_x86.hpp @ 7199:cd3d6a6b95d9

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
8003240: x86: move MacroAssembler into separate file Reviewed-by: kvn
author twisti
date Fri, 30 Nov 2012 15:23:16 -0800
parents 6ab62ad83507
children f0c2369fda5a
comparison
equal deleted inserted replaced
7198:6ab62ad83507 7199:cd3d6a6b95d9
23 */ 23 */
24 24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27 27
28 #include "asm/register.hpp"
29
28 class BiasedLockingCounters; 30 class BiasedLockingCounters;
29 31
30 // Contains all the definitions needed for x86 assembly code generation. 32 // Contains all the definitions needed for x86 assembly code generation.
31 33
32 // Calling convention 34 // Calling convention
432 Address index() { return _index; } 434 Address index() { return _index; }
433 435
434 }; 436 };
435 437
436 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
439
440 #ifdef ASSERT
441 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
442 #endif
437 443
438 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 444 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
439 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 445 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
440 // is what you get. The Assembler is generating code into a CodeBuffer. 446 // is what you get. The Assembler is generating code into a CodeBuffer.
441 447
912 918
913 void cdql(); 919 void cdql();
914 920
915 void cdqq(); 921 void cdqq();
916 922
917 void cld() { emit_byte(0xfc); } 923 void cld();
918 924
919 void clflush(Address adr); 925 void clflush(Address adr);
920 926
921 void cmovl(Condition cc, Register dst, Register src); 927 void cmovl(Condition cc, Register dst, Register src);
922 void cmovl(Condition cc, Register dst, Address src); 928 void cmovl(Condition cc, Register dst, Address src);
959 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 965 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
960 void comiss(XMMRegister dst, Address src); 966 void comiss(XMMRegister dst, Address src);
961 void comiss(XMMRegister dst, XMMRegister src); 967 void comiss(XMMRegister dst, XMMRegister src);
962 968
963 // Identify processor type and features 969 // Identify processor type and features
964 void cpuid() { 970 void cpuid();
965 emit_byte(0x0F);
966 emit_byte(0xA2);
967 }
968 971
969 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 972 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
970 void cvtsd2ss(XMMRegister dst, XMMRegister src); 973 void cvtsd2ss(XMMRegister dst, XMMRegister src);
971 void cvtsd2ss(XMMRegister dst, Address src); 974 void cvtsd2ss(XMMRegister dst, Address src);
972 975
1207 1210
1208 void leal(Register dst, Address src); 1211 void leal(Register dst, Address src);
1209 1212
1210 void leaq(Register dst, Address src); 1213 void leaq(Register dst, Address src);
1211 1214
1212 void lfence() { 1215 void lfence();
1213 emit_byte(0x0F);
1214 emit_byte(0xAE);
1215 emit_byte(0xE8);
1216 }
1217 1216
1218 void lock(); 1217 void lock();
1219 1218
1220 void lzcntl(Register dst, Register src); 1219 void lzcntl(Register dst, Register src);
1221 1220
1519 1518
1520 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1519 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1521 void sqrtss(XMMRegister dst, Address src); 1520 void sqrtss(XMMRegister dst, Address src);
1522 void sqrtss(XMMRegister dst, XMMRegister src); 1521 void sqrtss(XMMRegister dst, XMMRegister src);
1523 1522
1524 void std() { emit_byte(0xfd); } 1523 void std();
1525 1524
1526 void stmxcsr( Address dst ); 1525 void stmxcsr( Address dst );
1527 1526
1528 void subl(Address dst, int32_t imm32); 1527 void subl(Address dst, int32_t imm32);
1529 void subl(Address dst, Register src); 1528 void subl(Address dst, Register src);
1576 1575
1577 void xchgq(Register reg, Address adr); 1576 void xchgq(Register reg, Address adr);
1578 void xchgq(Register dst, Register src); 1577 void xchgq(Register dst, Register src);
1579 1578
1580 // Get Value of Extended Control Register 1579 // Get Value of Extended Control Register
1581 void xgetbv() { 1580 void xgetbv();
1582 emit_byte(0x0F);
1583 emit_byte(0x01);
1584 emit_byte(0xD0);
1585 }
1586 1581
1587 void xorl(Register dst, int32_t imm32); 1582 void xorl(Register dst, int32_t imm32);
1588 void xorl(Register dst, Address src); 1583 void xorl(Register dst, Address src);
1589 void xorl(Register dst, Register src); 1584 void xorl(Register dst, Register src);
1590 1585
1777 void xorpd(XMMRegister dst, Address src); 1772 void xorpd(XMMRegister dst, Address src);
1778 void xorps(XMMRegister dst, Address src); 1773 void xorps(XMMRegister dst, Address src);
1779 1774
1780 }; 1775 };
1781 1776
1782
1783 // MacroAssembler extends Assembler by frequently used macros.
1784 //
1785 // Instructions for which a 'better' code sequence exists depending
1786 // on arguments should also go in here.
1787
1788 class MacroAssembler: public Assembler {
1789 friend class LIR_Assembler;
1790 friend class Runtime1; // as_Address()
1791
1792 protected:
1793
1794 Address as_Address(AddressLiteral adr);
1795 Address as_Address(ArrayAddress adr);
1796
1797 // Support for VM calls
1798 //
1799 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1800 // may customize this version by overriding it for its purposes (e.g., to save/restore
1801 // additional registers when doing a VM call).
1802 #ifdef CC_INTERP
1803 // c++ interpreter never wants to use interp_masm version of call_VM
1804 #define VIRTUAL
1805 #else
1806 #define VIRTUAL virtual
1807 #endif
1808
1809 VIRTUAL void call_VM_leaf_base(
1810 address entry_point, // the entry point
1811 int number_of_arguments // the number of arguments to pop after the call
1812 );
1813
1814 // This is the base routine called by the different versions of call_VM. The interpreter
1815 // may customize this version by overriding it for its purposes (e.g., to save/restore
1816 // additional registers when doing a VM call).
1817 //
1818 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1819 // returns the register which contains the thread upon return. If a thread register has been
1820 // specified, the return value will correspond to that register. If no last_java_sp is specified
1821 // (noreg) than rsp will be used instead.
1822 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1823 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1824 Register java_thread, // the thread if computed before ; use noreg otherwise
1825 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1826 address entry_point, // the entry point
1827 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1828 bool check_exceptions // whether to check for pending exceptions after return
1829 );
1830
1831 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1832 // The implementation is only non-empty for the InterpreterMacroAssembler,
1833 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1834 virtual void check_and_handle_popframe(Register java_thread);
1835 virtual void check_and_handle_earlyret(Register java_thread);
1836
1837 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1838
1839 // helpers for FPU flag access
1840 // tmp is a temporary register, if none is available use noreg
1841 void save_rax (Register tmp);
1842 void restore_rax(Register tmp);
1843
1844 public:
1845 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1846
1847 // Support for NULL-checks
1848 //
1849 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1850 // If the accessed location is M[reg + offset] and the offset is known, provide the
1851 // offset. No explicit code generation is needed if the offset is within a certain
1852 // range (0 <= offset <= page_size).
1853
1854 void null_check(Register reg, int offset = -1);
1855 static bool needs_explicit_null_check(intptr_t offset);
1856
1857 // Required platform-specific helpers for Label::patch_instructions.
1858 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1859 void pd_patch_instruction(address branch, address target);
1860 #ifndef PRODUCT
1861 static void pd_print_patched_instruction(address branch);
1862 #endif
1863
1864 // The following 4 methods return the offset of the appropriate move instruction
1865
1866 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1867 int load_unsigned_byte(Register dst, Address src);
1868 int load_unsigned_short(Register dst, Address src);
1869
1870 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1871 int load_signed_byte(Register dst, Address src);
1872 int load_signed_short(Register dst, Address src);
1873
1874 // Support for sign-extension (hi:lo = extend_sign(lo))
1875 void extend_sign(Register hi, Register lo);
1876
1877 // Load and store values by size and signed-ness
1878 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1879 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1880
1881 // Support for inc/dec with optimal instruction selection depending on value
1882
1883 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1884 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1885
1886 void decrementl(Address dst, int value = 1);
1887 void decrementl(Register reg, int value = 1);
1888
1889 void decrementq(Register reg, int value = 1);
1890 void decrementq(Address dst, int value = 1);
1891
1892 void incrementl(Address dst, int value = 1);
1893 void incrementl(Register reg, int value = 1);
1894
1895 void incrementq(Register reg, int value = 1);
1896 void incrementq(Address dst, int value = 1);
1897
1898
1899 // Support optimal SSE move instructions.
1900 void movflt(XMMRegister dst, XMMRegister src) {
1901 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1902 else { movss (dst, src); return; }
1903 }
1904 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1905 void movflt(XMMRegister dst, AddressLiteral src);
1906 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1907
1908 void movdbl(XMMRegister dst, XMMRegister src) {
1909 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1910 else { movsd (dst, src); return; }
1911 }
1912
1913 void movdbl(XMMRegister dst, AddressLiteral src);
1914
1915 void movdbl(XMMRegister dst, Address src) {
1916 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1917 else { movlpd(dst, src); return; }
1918 }
1919 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1920
1921 void incrementl(AddressLiteral dst);
1922 void incrementl(ArrayAddress dst);
1923
1924 // Alignment
1925 void align(int modulus);
1926
1927 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1928 void fat_nop();
1929
1930 // Stack frame creation/removal
1931 void enter();
1932 void leave();
1933
1934 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1935 // The pointer will be loaded into the thread register.
1936 void get_thread(Register thread);
1937
1938
1939 // Support for VM calls
1940 //
1941 // It is imperative that all calls into the VM are handled via the call_VM macros.
1942 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1943 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1944
1945
1946 void call_VM(Register oop_result,
1947 address entry_point,
1948 bool check_exceptions = true);
1949 void call_VM(Register oop_result,
1950 address entry_point,
1951 Register arg_1,
1952 bool check_exceptions = true);
1953 void call_VM(Register oop_result,
1954 address entry_point,
1955 Register arg_1, Register arg_2,
1956 bool check_exceptions = true);
1957 void call_VM(Register oop_result,
1958 address entry_point,
1959 Register arg_1, Register arg_2, Register arg_3,
1960 bool check_exceptions = true);
1961
1962 // Overloadings with last_Java_sp
1963 void call_VM(Register oop_result,
1964 Register last_java_sp,
1965 address entry_point,
1966 int number_of_arguments = 0,
1967 bool check_exceptions = true);
1968 void call_VM(Register oop_result,
1969 Register last_java_sp,
1970 address entry_point,
1971 Register arg_1, bool
1972 check_exceptions = true);
1973 void call_VM(Register oop_result,
1974 Register last_java_sp,
1975 address entry_point,
1976 Register arg_1, Register arg_2,
1977 bool check_exceptions = true);
1978 void call_VM(Register oop_result,
1979 Register last_java_sp,
1980 address entry_point,
1981 Register arg_1, Register arg_2, Register arg_3,
1982 bool check_exceptions = true);
1983
1984 void get_vm_result (Register oop_result, Register thread);
1985 void get_vm_result_2(Register metadata_result, Register thread);
1986
1987 // These always tightly bind to MacroAssembler::call_VM_base
1988 // bypassing the virtual implementation
1989 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1990 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1991 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1992 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1993 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1994
1995 void call_VM_leaf(address entry_point,
1996 int number_of_arguments = 0);
1997 void call_VM_leaf(address entry_point,
1998 Register arg_1);
1999 void call_VM_leaf(address entry_point,
2000 Register arg_1, Register arg_2);
2001 void call_VM_leaf(address entry_point,
2002 Register arg_1, Register arg_2, Register arg_3);
2003
2004 // These always tightly bind to MacroAssembler::call_VM_leaf_base
2005 // bypassing the virtual implementation
2006 void super_call_VM_leaf(address entry_point);
2007 void super_call_VM_leaf(address entry_point, Register arg_1);
2008 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
2009 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
2010 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
2011
2012 // last Java Frame (fills frame anchor)
2013 void set_last_Java_frame(Register thread,
2014 Register last_java_sp,
2015 Register last_java_fp,
2016 address last_java_pc);
2017
2018 // thread in the default location (r15_thread on 64bit)
2019 void set_last_Java_frame(Register last_java_sp,
2020 Register last_java_fp,
2021 address last_java_pc);
2022
2023 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
2024
2025 // thread in the default location (r15_thread on 64bit)
2026 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
2027
2028 // Stores
2029 void store_check(Register obj); // store check for obj - register is destroyed afterwards
2030 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
2031
2032 #ifndef SERIALGC
2033
2034 void g1_write_barrier_pre(Register obj,
2035 Register pre_val,
2036 Register thread,
2037 Register tmp,
2038 bool tosca_live,
2039 bool expand_call);
2040
2041 void g1_write_barrier_post(Register store_addr,
2042 Register new_val,
2043 Register thread,
2044 Register tmp,
2045 Register tmp2);
2046
2047 #endif // SERIALGC
2048
2049 // split store_check(Register obj) to enhance instruction interleaving
2050 void store_check_part_1(Register obj);
2051 void store_check_part_2(Register obj);
2052
2053 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
2054 void c2bool(Register x);
2055
2056 // C++ bool manipulation
2057
2058 void movbool(Register dst, Address src);
2059 void movbool(Address dst, bool boolconst);
2060 void movbool(Address dst, Register src);
2061 void testbool(Register dst);
2062
2063 // oop manipulations
2064 void load_klass(Register dst, Register src);
2065 void store_klass(Register dst, Register src);
2066
2067 void load_heap_oop(Register dst, Address src);
2068 void load_heap_oop_not_null(Register dst, Address src);
2069 void store_heap_oop(Address dst, Register src);
2070 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
2071
2072 // Used for storing NULL. All other oop constants should be
2073 // stored using routines that take a jobject.
2074 void store_heap_oop_null(Address dst);
2075
2076 void load_prototype_header(Register dst, Register src);
2077
2078 #ifdef _LP64
2079 void store_klass_gap(Register dst, Register src);
2080
2081 // This dummy is to prevent a call to store_heap_oop from
2082 // converting a zero (like NULL) into a Register by giving
2083 // the compiler two choices it can't resolve
2084
2085 void store_heap_oop(Address dst, void* dummy);
2086
2087 void encode_heap_oop(Register r);
2088 void decode_heap_oop(Register r);
2089 void encode_heap_oop_not_null(Register r);
2090 void decode_heap_oop_not_null(Register r);
2091 void encode_heap_oop_not_null(Register dst, Register src);
2092 void decode_heap_oop_not_null(Register dst, Register src);
2093
2094 void set_narrow_oop(Register dst, jobject obj);
2095 void set_narrow_oop(Address dst, jobject obj);
2096 void cmp_narrow_oop(Register dst, jobject obj);
2097 void cmp_narrow_oop(Address dst, jobject obj);
2098
2099 void encode_klass_not_null(Register r);
2100 void decode_klass_not_null(Register r);
2101 void encode_klass_not_null(Register dst, Register src);
2102 void decode_klass_not_null(Register dst, Register src);
2103 void set_narrow_klass(Register dst, Klass* k);
2104 void set_narrow_klass(Address dst, Klass* k);
2105 void cmp_narrow_klass(Register dst, Klass* k);
2106 void cmp_narrow_klass(Address dst, Klass* k);
2107
2108 // if heap base register is used - reinit it with the correct value
2109 void reinit_heapbase();
2110
2111 DEBUG_ONLY(void verify_heapbase(const char* msg);)
2112
2113 #endif // _LP64
2114
2115 // Int division/remainder for Java
2116 // (as idivl, but checks for special case as described in JVM spec.)
2117 // returns idivl instruction offset for implicit exception handling
2118 int corrected_idivl(Register reg);
2119
2120 // Long division/remainder for Java
2121 // (as idivq, but checks for special case as described in JVM spec.)
2122 // returns idivq instruction offset for implicit exception handling
2123 int corrected_idivq(Register reg);
2124
2125 void int3();
2126
2127 // Long operation macros for a 32bit cpu
2128 // Long negation for Java
2129 void lneg(Register hi, Register lo);
2130
2131 // Long multiplication for Java
2132 // (destroys contents of eax, ebx, ecx and edx)
2133 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
2134
2135 // Long shifts for Java
2136 // (semantics as described in JVM spec.)
2137 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
2138 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
2139
2140 // Long compare for Java
2141 // (semantics as described in JVM spec.)
2142 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
2143
2144
2145 // misc
2146
2147 // Sign extension
2148 void sign_extend_short(Register reg);
2149 void sign_extend_byte(Register reg);
2150
2151 // Division by power of 2, rounding towards 0
2152 void division_with_shift(Register reg, int shift_value);
2153
2154 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
2155 //
2156 // CF (corresponds to C0) if x < y
2157 // PF (corresponds to C2) if unordered
2158 // ZF (corresponds to C3) if x = y
2159 //
2160 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2161 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
2162 void fcmp(Register tmp);
2163 // Variant of the above which allows y to be further down the stack
2164 // and which only pops x and y if specified. If pop_right is
2165 // specified then pop_left must also be specified.
2166 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
2167
2168 // Floating-point comparison for Java
2169 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
2170 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2171 // (semantics as described in JVM spec.)
2172 void fcmp2int(Register dst, bool unordered_is_less);
2173 // Variant of the above which allows y to be further down the stack
2174 // and which only pops x and y if specified. If pop_right is
2175 // specified then pop_left must also be specified.
2176 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
2177
2178 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
2179 // tmp is a temporary register, if none is available use noreg
2180 void fremr(Register tmp);
2181
2182
2183 // same as fcmp2int, but using SSE2
2184 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2185 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2186
2187 // Inlined sin/cos generator for Java; must not use CPU instruction
2188 // directly on Intel as it does not have high enough precision
2189 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2190 // number of FPU stack slots in use; all but the topmost will
2191 // require saving if a slow case is necessary. Assumes argument is
2192 // on FP TOS; result is on FP TOS. No cpu registers are changed by
2193 // this code.
2194 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2195
2196 // branch to L if FPU flag C2 is set/not set
2197 // tmp is a temporary register, if none is available use noreg
2198 void jC2 (Register tmp, Label& L);
2199 void jnC2(Register tmp, Label& L);
2200
2201 // Pop ST (ffree & fincstp combined)
2202 void fpop();
2203
2204 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2205 void push_fTOS();
2206
2207 // pops double TOS element from CPU stack and pushes on FPU stack
2208 void pop_fTOS();
2209
2210 void empty_FPU_stack();
2211
2212 void push_IU_state();
2213 void pop_IU_state();
2214
2215 void push_FPU_state();
2216 void pop_FPU_state();
2217
2218 void push_CPU_state();
2219 void pop_CPU_state();
2220
2221 // Round up to a power of two
2222 void round_to(Register reg, int modulus);
2223
2224 // Callee saved registers handling
2225 void push_callee_saved_registers();
2226 void pop_callee_saved_registers();
2227
2228 // allocation
2229 void eden_allocate(
2230 Register obj, // result: pointer to object after successful allocation
2231 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2232 int con_size_in_bytes, // object size in bytes if known at compile time
2233 Register t1, // temp register
2234 Label& slow_case // continuation point if fast allocation fails
2235 );
2236 void tlab_allocate(
2237 Register obj, // result: pointer to object after successful allocation
2238 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2239 int con_size_in_bytes, // object size in bytes if known at compile time
2240 Register t1, // temp register
2241 Register t2, // temp register
2242 Label& slow_case // continuation point if fast allocation fails
2243 );
2244 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2245 void incr_allocated_bytes(Register thread,
2246 Register var_size_in_bytes, int con_size_in_bytes,
2247 Register t1 = noreg);
2248
2249 // interface method calling
2250 void lookup_interface_method(Register recv_klass,
2251 Register intf_klass,
2252 RegisterOrConstant itable_index,
2253 Register method_result,
2254 Register scan_temp,
2255 Label& no_such_interface);
2256
2257 // virtual method calling
2258 void lookup_virtual_method(Register recv_klass,
2259 RegisterOrConstant vtable_index,
2260 Register method_result);
2261
2262 // Test sub_klass against super_klass, with fast and slow paths.
2263
2264 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2265 // One of the three labels can be NULL, meaning take the fall-through.
2266 // If super_check_offset is -1, the value is loaded up from super_klass.
2267 // No registers are killed, except temp_reg.
2268 void check_klass_subtype_fast_path(Register sub_klass,
2269 Register super_klass,
2270 Register temp_reg,
2271 Label* L_success,
2272 Label* L_failure,
2273 Label* L_slow_path,
2274 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2275
2276 // The rest of the type check; must be wired to a corresponding fast path.
2277 // It does not repeat the fast path logic, so don't use it standalone.
2278 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2279 // Updates the sub's secondary super cache as necessary.
2280 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2281 void check_klass_subtype_slow_path(Register sub_klass,
2282 Register super_klass,
2283 Register temp_reg,
2284 Register temp2_reg,
2285 Label* L_success,
2286 Label* L_failure,
2287 bool set_cond_codes = false);
2288
2289 // Simplified, combined version, good for typical uses.
2290 // Falls through on failure.
2291 void check_klass_subtype(Register sub_klass,
2292 Register super_klass,
2293 Register temp_reg,
2294 Label& L_success);
2295
2296 // method handles (JSR 292)
2297 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2298
2299 //----
2300 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2301
2302 // Debugging
2303
2304 // only if +VerifyOops
2305 // TODO: Make these macros with file and line like sparc version!
2306 void verify_oop(Register reg, const char* s = "broken oop");
2307 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2308
2309 // TODO: verify method and klass metadata (compare against vptr?)
2310 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
2311 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
2312
2313 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
2314 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
2315
2316 // only if +VerifyFPU
2317 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2318
2319 // prints msg, dumps registers and stops execution
2320 void stop(const char* msg);
2321
2322 // prints msg and continues
2323 void warn(const char* msg);
2324
2325 // dumps registers and other state
2326 void print_state();
2327
2328 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2329 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2330 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
2331 static void print_state64(int64_t pc, int64_t regs[]);
2332
2333 void os_breakpoint();
2334
2335 void untested() { stop("untested"); }
2336
2337 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
2338
2339 void should_not_reach_here() { stop("should not reach here"); }
2340
2341 void print_CPU_state();
2342
2343 // Stack overflow checking
2344 void bang_stack_with_offset(int offset) {
2345 // stack grows down, caller passes positive offset
2346 assert(offset > 0, "must bang with negative offset");
2347 movl(Address(rsp, (-offset)), rax);
2348 }
2349
2350 // Writes to stack successive pages until offset reached to check for
2351 // stack overflow + shadow pages. Also, clobbers tmp
2352 void bang_stack_size(Register size, Register tmp);
2353
2354 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2355 Register tmp,
2356 int offset);
2357
2358 // Support for serializing memory accesses between threads
2359 void serialize_memory(Register thread, Register tmp);
2360
2361 void verify_tlab();
2362
2363 // Biased locking support
2364 // lock_reg and obj_reg must be loaded up with the appropriate values.
2365 // swap_reg must be rax, and is killed.
2366 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2367 // be killed; if not supplied, push/pop will be used internally to
2368 // allocate a temporary (inefficient, avoid if possible).
2369 // Optional slow case is for implementations (interpreter and C1) which branch to
2370 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2371 // Returns offset of first potentially-faulting instruction for null
2372 // check info (currently consumed only by C1). If
2373 // swap_reg_contains_mark is true then returns -1 as it is assumed
2374 // the calling code has already passed any potential faults.
2375 int biased_locking_enter(Register lock_reg, Register obj_reg,
2376 Register swap_reg, Register tmp_reg,
2377 bool swap_reg_contains_mark,
2378 Label& done, Label* slow_case = NULL,
2379 BiasedLockingCounters* counters = NULL);
2380 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2381
2382
2383 Condition negate_condition(Condition cond);
2384
2385 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2386 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2387 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2388 // here in MacroAssembler. The major exception to this rule is call
2389
2390 // Arithmetics
2391
2392
2393 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2394 void addptr(Address dst, Register src);
2395
2396 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2397 void addptr(Register dst, int32_t src);
2398 void addptr(Register dst, Register src);
2399 void addptr(Register dst, RegisterOrConstant src) {
2400 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2401 else addptr(dst, src.as_register());
2402 }
2403
2404 void andptr(Register dst, int32_t src);
2405 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2406
2407 void cmp8(AddressLiteral src1, int imm);
2408
2409 // renamed to drag out the casting of address to int32_t/intptr_t
2410 void cmp32(Register src1, int32_t imm);
2411
2412 void cmp32(AddressLiteral src1, int32_t imm);
2413 // compare reg - mem, or reg - &mem
2414 void cmp32(Register src1, AddressLiteral src2);
2415
2416 void cmp32(Register src1, Address src2);
2417
2418 #ifndef _LP64
2419 void cmpklass(Address dst, Metadata* obj);
2420 void cmpklass(Register dst, Metadata* obj);
2421 void cmpoop(Address dst, jobject obj);
2422 void cmpoop(Register dst, jobject obj);
2423 #endif // _LP64
2424
2425 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2426 void cmpptr(Address src1, AddressLiteral src2);
2427
2428 void cmpptr(Register src1, AddressLiteral src2);
2429
2430 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2431 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2432 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2433
2434 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2435 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2436
2437 // cmp64 to avoild hiding cmpq
2438 void cmp64(Register src1, AddressLiteral src);
2439
2440 void cmpxchgptr(Register reg, Address adr);
2441
2442 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2443
2444
2445 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2446
2447
2448 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2449
2450 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2451
2452 void shlptr(Register dst, int32_t shift);
2453 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2454
2455 void shrptr(Register dst, int32_t shift);
2456 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2457
2458 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2459 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2460
2461 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2462
2463 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2464 void subptr(Register dst, int32_t src);
2465 // Force generation of a 4 byte immediate value even if it fits into 8bit
2466 void subptr_imm32(Register dst, int32_t src);
2467 void subptr(Register dst, Register src);
2468 void subptr(Register dst, RegisterOrConstant src) {
2469 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2470 else subptr(dst, src.as_register());
2471 }
2472
2473 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2474 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2475
2476 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2477 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2478
2479 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2480
2481
2482
2483 // Helper functions for statistics gathering.
2484 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2485 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2486 // Unconditional atomic increment.
2487 void atomic_incl(AddressLiteral counter_addr);
2488
2489 void lea(Register dst, AddressLiteral adr);
2490 void lea(Address dst, AddressLiteral adr);
2491 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2492
2493 void leal32(Register dst, Address src) { leal(dst, src); }
2494
2495 // Import other testl() methods from the parent class or else
2496 // they will be hidden by the following overriding declaration.
2497 using Assembler::testl;
2498 void testl(Register dst, AddressLiteral src);
2499
2500 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2501 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2502 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2503
2504 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2505 void testptr(Register src1, Register src2);
2506
2507 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2508 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2509
2510 // Calls
2511
2512 void call(Label& L, relocInfo::relocType rtype);
2513 void call(Register entry);
2514
2515 // NOTE: this call tranfers to the effective address of entry NOT
2516 // the address contained by entry. This is because this is more natural
2517 // for jumps/calls.
2518 void call(AddressLiteral entry);
2519
2520 // Emit the CompiledIC call idiom
2521 void ic_call(address entry);
2522
2523 // Jumps
2524
2525 // NOTE: these jumps tranfer to the effective address of dst NOT
2526 // the address contained by dst. This is because this is more natural
2527 // for jumps/calls.
2528 void jump(AddressLiteral dst);
2529 void jump_cc(Condition cc, AddressLiteral dst);
2530
2531 // 32bit can do a case table jump in one instruction but we no longer allow the base
2532 // to be installed in the Address class. This jump will tranfers to the address
2533 // contained in the location described by entry (not the address of entry)
2534 void jump(ArrayAddress entry);
2535
2536 // Floating
2537
2538 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2539 void andpd(XMMRegister dst, AddressLiteral src);
2540
2541 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2542 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2543 void andps(XMMRegister dst, AddressLiteral src);
2544
2545 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2546 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2547 void comiss(XMMRegister dst, AddressLiteral src);
2548
2549 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2550 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2551 void comisd(XMMRegister dst, AddressLiteral src);
2552
2553 void fadd_s(Address src) { Assembler::fadd_s(src); }
2554 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2555
2556 void fldcw(Address src) { Assembler::fldcw(src); }
2557 void fldcw(AddressLiteral src);
2558
2559 void fld_s(int index) { Assembler::fld_s(index); }
2560 void fld_s(Address src) { Assembler::fld_s(src); }
2561 void fld_s(AddressLiteral src);
2562
2563 void fld_d(Address src) { Assembler::fld_d(src); }
2564 void fld_d(AddressLiteral src);
2565
2566 void fld_x(Address src) { Assembler::fld_x(src); }
2567 void fld_x(AddressLiteral src);
2568
2569 void fmul_s(Address src) { Assembler::fmul_s(src); }
2570 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2571
2572 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2573 void ldmxcsr(AddressLiteral src);
2574
2575 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
2576 // all corner cases and may result in NaN and require fallback to a
2577 // runtime call.
2578 void fast_pow();
2579 void fast_exp();
2580 void increase_precision();
2581 void restore_precision();
2582
2583 // computes exp(x). Fallback to runtime call included.
2584 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
2585 // computes pow(x,y). Fallback to runtime call included.
2586 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
2587
2588 private:
2589
2590 // call runtime as a fallback for trig functions and pow/exp.
2591 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
2592
2593 // computes 2^(Ylog2X); Ylog2X in ST(0)
2594 void pow_exp_core_encoding();
2595
2596 // computes pow(x,y) or exp(x). Fallback to runtime call included.
2597 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
2598
2599 // these are private because users should be doing movflt/movdbl
2600
2601 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2602 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2603 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2604 void movss(XMMRegister dst, AddressLiteral src);
2605
2606 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2607 void movlpd(XMMRegister dst, AddressLiteral src);
2608
2609 public:
2610
2611 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2612 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2613 void addsd(XMMRegister dst, AddressLiteral src);
2614
2615 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2616 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2617 void addss(XMMRegister dst, AddressLiteral src);
2618
2619 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2620 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2621 void divsd(XMMRegister dst, AddressLiteral src);
2622
2623 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2624 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2625 void divss(XMMRegister dst, AddressLiteral src);
2626
2627 // Move Unaligned Double Quadword
2628 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2629 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
2630 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2631 void movdqu(XMMRegister dst, AddressLiteral src);
2632
2633 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2634 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2635 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2636 void movsd(XMMRegister dst, AddressLiteral src);
2637
2638 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2639 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2640 void mulsd(XMMRegister dst, AddressLiteral src);
2641
2642 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2643 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2644 void mulss(XMMRegister dst, AddressLiteral src);
2645
2646 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2647 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2648 void sqrtsd(XMMRegister dst, AddressLiteral src);
2649
2650 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2651 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2652 void sqrtss(XMMRegister dst, AddressLiteral src);
2653
2654 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2655 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2656 void subsd(XMMRegister dst, AddressLiteral src);
2657
2658 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2659 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2660 void subss(XMMRegister dst, AddressLiteral src);
2661
2662 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2663 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2664 void ucomiss(XMMRegister dst, AddressLiteral src);
2665
2666 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2667 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2668 void ucomisd(XMMRegister dst, AddressLiteral src);
2669
2670 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2671 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2672 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2673 void xorpd(XMMRegister dst, AddressLiteral src);
2674
2675 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2676 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2677 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2678 void xorps(XMMRegister dst, AddressLiteral src);
2679
2680 // Shuffle Bytes
2681 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
2682 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
2683 void pshufb(XMMRegister dst, AddressLiteral src);
2684 // AVX 3-operands instructions
2685
2686 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2687 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
2688 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2689
2690 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2691 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2692 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2693
2694 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2695 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2696 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2697
2698 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2699 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2700 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2701
2702 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2703 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2704 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2705
2706 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2707 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
2708 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2709
2710 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2711 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
2712 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2713
2714 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2715 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
2716 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2717
2718 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2719 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
2720 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2721
2722 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2723 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
2724 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2725
2726 // AVX Vector instructions
2727
2728 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2729 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2730 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2731
2732 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2733 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2734 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2735
2736 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2737 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2738 Assembler::vpxor(dst, nds, src, vector256);
2739 else
2740 Assembler::vxorpd(dst, nds, src, vector256);
2741 }
2742 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2743 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2744 Assembler::vpxor(dst, nds, src, vector256);
2745 else
2746 Assembler::vxorpd(dst, nds, src, vector256);
2747 }
2748
2749 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
2750 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2751 if (UseAVX > 1) // vinserti128h is available only in AVX2
2752 Assembler::vinserti128h(dst, nds, src);
2753 else
2754 Assembler::vinsertf128h(dst, nds, src);
2755 }
2756
2757 // Data
2758
2759 void cmov32( Condition cc, Register dst, Address src);
2760 void cmov32( Condition cc, Register dst, Register src);
2761
2762 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2763
2764 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2765 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2766
2767 void movoop(Register dst, jobject obj);
2768 void movoop(Address dst, jobject obj);
2769
2770 void mov_metadata(Register dst, Metadata* obj);
2771 void mov_metadata(Address dst, Metadata* obj);
2772
2773 void movptr(ArrayAddress dst, Register src);
2774 // can this do an lea?
2775 void movptr(Register dst, ArrayAddress src);
2776
2777 void movptr(Register dst, Address src);
2778
2779 void movptr(Register dst, AddressLiteral src);
2780
2781 void movptr(Register dst, intptr_t src);
2782 void movptr(Register dst, Register src);
2783 void movptr(Address dst, intptr_t src);
2784
2785 void movptr(Address dst, Register src);
2786
2787 void movptr(Register dst, RegisterOrConstant src) {
2788 if (src.is_constant()) movptr(dst, src.as_constant());
2789 else movptr(dst, src.as_register());
2790 }
2791
2792 #ifdef _LP64
2793 // Generally the next two are only used for moving NULL
2794 // Although there are situations in initializing the mark word where
2795 // they could be used. They are dangerous.
2796
2797 // They only exist on LP64 so that int32_t and intptr_t are not the same
2798 // and we have ambiguous declarations.
2799
2800 void movptr(Address dst, int32_t imm32);
2801 void movptr(Register dst, int32_t imm32);
2802 #endif // _LP64
2803
2804 // to avoid hiding movl
2805 void mov32(AddressLiteral dst, Register src);
2806 void mov32(Register dst, AddressLiteral src);
2807
2808 // to avoid hiding movb
2809 void movbyte(ArrayAddress dst, int src);
2810
2811 // Import other mov() methods from the parent class or else
2812 // they will be hidden by the following overriding declaration.
2813 using Assembler::movdl;
2814 using Assembler::movq;
2815 void movdl(XMMRegister dst, AddressLiteral src);
2816 void movq(XMMRegister dst, AddressLiteral src);
2817
2818 // Can push value or effective address
2819 void pushptr(AddressLiteral src);
2820
2821 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2822 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2823
2824 void pushoop(jobject obj);
2825 void pushklass(Metadata* obj);
2826
2827 // sign extend as need a l to ptr sized element
2828 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2829 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2830
2831 // C2 compiled method's prolog code.
2832 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
2833
2834 // IndexOf strings.
2835 // Small strings are loaded through stack if they cross page boundary.
2836 void string_indexof(Register str1, Register str2,
2837 Register cnt1, Register cnt2,
2838 int int_cnt2, Register result,
2839 XMMRegister vec, Register tmp);
2840
2841 // IndexOf for constant substrings with size >= 8 elements
2842 // which don't need to be loaded through stack.
2843 void string_indexofC8(Register str1, Register str2,
2844 Register cnt1, Register cnt2,
2845 int int_cnt2, Register result,
2846 XMMRegister vec, Register tmp);
2847
2848 // Smallest code: we don't need to load through stack,
2849 // check string tail.
2850
2851 // Compare strings.
2852 void string_compare(Register str1, Register str2,
2853 Register cnt1, Register cnt2, Register result,
2854 XMMRegister vec1);
2855
2856 // Compare char[] arrays.
2857 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2858 Register limit, Register result, Register chr,
2859 XMMRegister vec1, XMMRegister vec2);
2860
2861 // Fill primitive arrays
2862 void generate_fill(BasicType t, bool aligned,
2863 Register to, Register value, Register count,
2864 Register rtmp, XMMRegister xtmp);
2865
2866 #undef VIRTUAL
2867
2868 };
2869
2870 /**
2871 * class SkipIfEqual:
2872 *
2873 * Instantiating this class will result in assembly code being output that will
2874 * jump around any code emitted between the creation of the instance and it's
2875 * automatic destruction at the end of a scope block, depending on the value of
2876 * the flag passed to the constructor, which will be checked at run-time.
2877 */
2878 class SkipIfEqual {
2879 private:
2880 MacroAssembler* _masm;
2881 Label _label;
2882
2883 public:
2884 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2885 ~SkipIfEqual();
2886 };
2887
2888 #ifdef ASSERT
2889 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2890 #endif
2891
2892 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP 1777 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP