Mercurial > hg > graal-jvmci-8

comparison src/cpu/x86/vm/assembler_x86.hpp @ 7206:d2f8c38e543d

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Merge
author roland
date Fri, 07 Dec 2012 01:09:03 -0800
parents f0c2369fda5a
children 00af3a3a8df4
comparison
equal deleted inserted replaced
7191:816b7e5bf2ed 7206:d2f8c38e543d
23 */ 23 */
24 24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27 27
28 #include "asm/register.hpp"
29
28 class BiasedLockingCounters; 30 class BiasedLockingCounters;
29 31
30 // Contains all the definitions needed for x86 assembly code generation. 32 // Contains all the definitions needed for x86 assembly code generation.
31 33
32 // Calling convention 34 // Calling convention
704 protected: 706 protected:
705 #ifdef ASSERT 707 #ifdef ASSERT
706 void check_relocation(RelocationHolder const& rspec, int format); 708 void check_relocation(RelocationHolder const& rspec, int format);
707 #endif 709 #endif
708 710
709 inline void emit_long64(jlong x);
710
711 void emit_data(jint data, relocInfo::relocType rtype, int format); 711 void emit_data(jint data, relocInfo::relocType rtype, int format);
712 void emit_data(jint data, RelocationHolder const& rspec, int format); 712 void emit_data(jint data, RelocationHolder const& rspec, int format);
713 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 713 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
714 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 714 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
715 715
914 914
915 void cdql(); 915 void cdql();
916 916
917 void cdqq(); 917 void cdqq();
918 918
919 void cld() { emit_byte(0xfc); } 919 void cld();
920 920
921 void clflush(Address adr); 921 void clflush(Address adr);
922 922
923 void cmovl(Condition cc, Register dst, Register src); 923 void cmovl(Condition cc, Register dst, Register src);
924 void cmovl(Condition cc, Register dst, Address src); 924 void cmovl(Condition cc, Register dst, Address src);
961 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 961 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
962 void comiss(XMMRegister dst, Address src); 962 void comiss(XMMRegister dst, Address src);
963 void comiss(XMMRegister dst, XMMRegister src); 963 void comiss(XMMRegister dst, XMMRegister src);
964 964
965 // Identify processor type and features 965 // Identify processor type and features
966 void cpuid() { 966 void cpuid();
967 emit_byte(0x0F);
968 emit_byte(0xA2);
969 }
970 967
971 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 968 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
972 void cvtsd2ss(XMMRegister dst, XMMRegister src); 969 void cvtsd2ss(XMMRegister dst, XMMRegister src);
973 void cvtsd2ss(XMMRegister dst, Address src); 970 void cvtsd2ss(XMMRegister dst, Address src);
974 971
1209 1206
1210 void leal(Register dst, Address src); 1207 void leal(Register dst, Address src);
1211 1208
1212 void leaq(Register dst, Address src); 1209 void leaq(Register dst, Address src);
1213 1210
1214 void lfence() { 1211 void lfence();
1215 emit_byte(0x0F);
1216 emit_byte(0xAE);
1217 emit_byte(0xE8);
1218 }
1219 1212
1220 void lock(); 1213 void lock();
1221 1214
1222 void lzcntl(Register dst, Register src); 1215 void lzcntl(Register dst, Register src);
1223 1216
1521 1514
1522 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1515 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1523 void sqrtss(XMMRegister dst, Address src); 1516 void sqrtss(XMMRegister dst, Address src);
1524 void sqrtss(XMMRegister dst, XMMRegister src); 1517 void sqrtss(XMMRegister dst, XMMRegister src);
1525 1518
1526 void std() { emit_byte(0xfd); } 1519 void std();
1527 1520
1528 void stmxcsr( Address dst ); 1521 void stmxcsr( Address dst );
1529 1522
1530 void subl(Address dst, int32_t imm32); 1523 void subl(Address dst, int32_t imm32);
1531 void subl(Address dst, Register src); 1524 void subl(Address dst, Register src);
1578 1571
1579 void xchgq(Register reg, Address adr); 1572 void xchgq(Register reg, Address adr);
1580 void xchgq(Register dst, Register src); 1573 void xchgq(Register dst, Register src);
1581 1574
1582 // Get Value of Extended Control Register 1575 // Get Value of Extended Control Register
1583 void xgetbv() { 1576 void xgetbv();
1584 emit_byte(0x0F);
1585 emit_byte(0x01);
1586 emit_byte(0xD0);
1587 }
1588 1577
1589 void xorl(Register dst, int32_t imm32); 1578 void xorl(Register dst, int32_t imm32);
1590 void xorl(Register dst, Address src); 1579 void xorl(Register dst, Address src);
1591 void xorl(Register dst, Register src); 1580 void xorl(Register dst, Register src);
1592 1581
1779 void xorpd(XMMRegister dst, Address src); 1768 void xorpd(XMMRegister dst, Address src);
1780 void xorps(XMMRegister dst, Address src); 1769 void xorps(XMMRegister dst, Address src);
1781 1770
1782 }; 1771 };
1783 1772
1784
1785 // MacroAssembler extends Assembler by frequently used macros.
1786 //
1787 // Instructions for which a 'better' code sequence exists depending
1788 // on arguments should also go in here.
1789
1790 class MacroAssembler: public Assembler {
1791 friend class LIR_Assembler;
1792 friend class Runtime1; // as_Address()
1793
1794 protected:
1795
1796 Address as_Address(AddressLiteral adr);
1797 Address as_Address(ArrayAddress adr);
1798
1799 // Support for VM calls
1800 //
1801 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1802 // may customize this version by overriding it for its purposes (e.g., to save/restore
1803 // additional registers when doing a VM call).
1804 #ifdef CC_INTERP
1805 // c++ interpreter never wants to use interp_masm version of call_VM
1806 #define VIRTUAL
1807 #else
1808 #define VIRTUAL virtual
1809 #endif
1810
1811 VIRTUAL void call_VM_leaf_base(
1812 address entry_point, // the entry point
1813 int number_of_arguments // the number of arguments to pop after the call
1814 );
1815
1816 // This is the base routine called by the different versions of call_VM. The interpreter
1817 // may customize this version by overriding it for its purposes (e.g., to save/restore
1818 // additional registers when doing a VM call).
1819 //
1820 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1821 // returns the register which contains the thread upon return. If a thread register has been
1822 // specified, the return value will correspond to that register. If no last_java_sp is specified
1823 // (noreg) than rsp will be used instead.
1824 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1825 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1826 Register java_thread, // the thread if computed before ; use noreg otherwise
1827 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1828 address entry_point, // the entry point
1829 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1830 bool check_exceptions // whether to check for pending exceptions after return
1831 );
1832
1833 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1834 // The implementation is only non-empty for the InterpreterMacroAssembler,
1835 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1836 virtual void check_and_handle_popframe(Register java_thread);
1837 virtual void check_and_handle_earlyret(Register java_thread);
1838
1839 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1840
1841 // helpers for FPU flag access
1842 // tmp is a temporary register, if none is available use noreg
1843 void save_rax (Register tmp);
1844 void restore_rax(Register tmp);
1845
1846 public:
1847 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1848
1849 // Support for NULL-checks
1850 //
1851 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1852 // If the accessed location is M[reg + offset] and the offset is known, provide the
1853 // offset. No explicit code generation is needed if the offset is within a certain
1854 // range (0 <= offset <= page_size).
1855
1856 void null_check(Register reg, int offset = -1);
1857 static bool needs_explicit_null_check(intptr_t offset);
1858
1859 // Required platform-specific helpers for Label::patch_instructions.
1860 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1861 void pd_patch_instruction(address branch, address target);
1862 #ifndef PRODUCT
1863 static void pd_print_patched_instruction(address branch);
1864 #endif
1865
1866 // The following 4 methods return the offset of the appropriate move instruction
1867
1868 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1869 int load_unsigned_byte(Register dst, Address src);
1870 int load_unsigned_short(Register dst, Address src);
1871
1872 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1873 int load_signed_byte(Register dst, Address src);
1874 int load_signed_short(Register dst, Address src);
1875
1876 // Support for sign-extension (hi:lo = extend_sign(lo))
1877 void extend_sign(Register hi, Register lo);
1878
1879 // Load and store values by size and signed-ness
1880 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1881 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1882
1883 // Support for inc/dec with optimal instruction selection depending on value
1884
1885 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1886 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1887
1888 void decrementl(Address dst, int value = 1);
1889 void decrementl(Register reg, int value = 1);
1890
1891 void decrementq(Register reg, int value = 1);
1892 void decrementq(Address dst, int value = 1);
1893
1894 void incrementl(Address dst, int value = 1);
1895 void incrementl(Register reg, int value = 1);
1896
1897 void incrementq(Register reg, int value = 1);
1898 void incrementq(Address dst, int value = 1);
1899
1900
1901 // Support optimal SSE move instructions.
1902 void movflt(XMMRegister dst, XMMRegister src) {
1903 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1904 else { movss (dst, src); return; }
1905 }
1906 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1907 void movflt(XMMRegister dst, AddressLiteral src);
1908 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1909
1910 void movdbl(XMMRegister dst, XMMRegister src) {
1911 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1912 else { movsd (dst, src); return; }
1913 }
1914
1915 void movdbl(XMMRegister dst, AddressLiteral src);
1916
1917 void movdbl(XMMRegister dst, Address src) {
1918 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1919 else { movlpd(dst, src); return; }
1920 }
1921 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1922
1923 void incrementl(AddressLiteral dst);
1924 void incrementl(ArrayAddress dst);
1925
1926 // Alignment
1927 void align(int modulus);
1928
1929 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1930 void fat_nop();
1931
1932 // Stack frame creation/removal
1933 void enter();
1934 void leave();
1935
1936 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1937 // The pointer will be loaded into the thread register.
1938 void get_thread(Register thread);
1939
1940
1941 // Support for VM calls
1942 //
1943 // It is imperative that all calls into the VM are handled via the call_VM macros.
1944 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1945 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1946
1947
1948 void call_VM(Register oop_result,
1949 address entry_point,
1950 bool check_exceptions = true);
1951 void call_VM(Register oop_result,
1952 address entry_point,
1953 Register arg_1,
1954 bool check_exceptions = true);
1955 void call_VM(Register oop_result,
1956 address entry_point,
1957 Register arg_1, Register arg_2,
1958 bool check_exceptions = true);
1959 void call_VM(Register oop_result,
1960 address entry_point,
1961 Register arg_1, Register arg_2, Register arg_3,
1962 bool check_exceptions = true);
1963
1964 // Overloadings with last_Java_sp
1965 void call_VM(Register oop_result,
1966 Register last_java_sp,
1967 address entry_point,
1968 int number_of_arguments = 0,
1969 bool check_exceptions = true);
1970 void call_VM(Register oop_result,
1971 Register last_java_sp,
1972 address entry_point,
1973 Register arg_1, bool
1974 check_exceptions = true);
1975 void call_VM(Register oop_result,
1976 Register last_java_sp,
1977 address entry_point,
1978 Register arg_1, Register arg_2,
1979 bool check_exceptions = true);
1980 void call_VM(Register oop_result,
1981 Register last_java_sp,
1982 address entry_point,
1983 Register arg_1, Register arg_2, Register arg_3,
1984 bool check_exceptions = true);
1985
1986 void get_vm_result (Register oop_result, Register thread);
1987 void get_vm_result_2(Register metadata_result, Register thread);
1988
1989 // These always tightly bind to MacroAssembler::call_VM_base
1990 // bypassing the virtual implementation
1991 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1992 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1993 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1994 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1995 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
1996
1997 void call_VM_leaf(address entry_point,
1998 int number_of_arguments = 0);
1999 void call_VM_leaf(address entry_point,
2000 Register arg_1);
2001 void call_VM_leaf(address entry_point,
2002 Register arg_1, Register arg_2);
2003 void call_VM_leaf(address entry_point,
2004 Register arg_1, Register arg_2, Register arg_3);
2005
2006 // These always tightly bind to MacroAssembler::call_VM_leaf_base
2007 // bypassing the virtual implementation
2008 void super_call_VM_leaf(address entry_point);
2009 void super_call_VM_leaf(address entry_point, Register arg_1);
2010 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
2011 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
2012 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
2013
2014 // last Java Frame (fills frame anchor)
2015 void set_last_Java_frame(Register thread,
2016 Register last_java_sp,
2017 Register last_java_fp,
2018 address last_java_pc);
2019
2020 // thread in the default location (r15_thread on 64bit)
2021 void set_last_Java_frame(Register last_java_sp,
2022 Register last_java_fp,
2023 address last_java_pc);
2024
2025 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
2026
2027 // thread in the default location (r15_thread on 64bit)
2028 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
2029
2030 // Stores
2031 void store_check(Register obj); // store check for obj - register is destroyed afterwards
2032 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
2033
2034 #ifndef SERIALGC
2035
2036 void g1_write_barrier_pre(Register obj,
2037 Register pre_val,
2038 Register thread,
2039 Register tmp,
2040 bool tosca_live,
2041 bool expand_call);
2042
2043 void g1_write_barrier_post(Register store_addr,
2044 Register new_val,
2045 Register thread,
2046 Register tmp,
2047 Register tmp2);
2048
2049 #endif // SERIALGC
2050
2051 // split store_check(Register obj) to enhance instruction interleaving
2052 void store_check_part_1(Register obj);
2053 void store_check_part_2(Register obj);
2054
2055 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
2056 void c2bool(Register x);
2057
2058 // C++ bool manipulation
2059
2060 void movbool(Register dst, Address src);
2061 void movbool(Address dst, bool boolconst);
2062 void movbool(Address dst, Register src);
2063 void testbool(Register dst);
2064
2065 // oop manipulations
2066 void load_klass(Register dst, Register src);
2067 void store_klass(Register dst, Register src);
2068
2069 void load_heap_oop(Register dst, Address src);
2070 void load_heap_oop_not_null(Register dst, Address src);
2071 void store_heap_oop(Address dst, Register src);
2072 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
2073
2074 // Used for storing NULL. All other oop constants should be
2075 // stored using routines that take a jobject.
2076 void store_heap_oop_null(Address dst);
2077
2078 void load_prototype_header(Register dst, Register src);
2079
2080 #ifdef _LP64
2081 void store_klass_gap(Register dst, Register src);
2082
2083 // This dummy is to prevent a call to store_heap_oop from
2084 // converting a zero (like NULL) into a Register by giving
2085 // the compiler two choices it can't resolve
2086
2087 void store_heap_oop(Address dst, void* dummy);
2088
2089 void encode_heap_oop(Register r);
2090 void decode_heap_oop(Register r);
2091 void encode_heap_oop_not_null(Register r);
2092 void decode_heap_oop_not_null(Register r);
2093 void encode_heap_oop_not_null(Register dst, Register src);
2094 void decode_heap_oop_not_null(Register dst, Register src);
2095
2096 void set_narrow_oop(Register dst, jobject obj);
2097 void set_narrow_oop(Address dst, jobject obj);
2098 void cmp_narrow_oop(Register dst, jobject obj);
2099 void cmp_narrow_oop(Address dst, jobject obj);
2100
2101 void encode_klass_not_null(Register r);
2102 void decode_klass_not_null(Register r);
2103 void encode_klass_not_null(Register dst, Register src);
2104 void decode_klass_not_null(Register dst, Register src);
2105 void set_narrow_klass(Register dst, Klass* k);
2106 void set_narrow_klass(Address dst, Klass* k);
2107 void cmp_narrow_klass(Register dst, Klass* k);
2108 void cmp_narrow_klass(Address dst, Klass* k);
2109
2110 // if heap base register is used - reinit it with the correct value
2111 void reinit_heapbase();
2112
2113 DEBUG_ONLY(void verify_heapbase(const char* msg);)
2114
2115 #endif // _LP64
2116
2117 // Int division/remainder for Java
2118 // (as idivl, but checks for special case as described in JVM spec.)
2119 // returns idivl instruction offset for implicit exception handling
2120 int corrected_idivl(Register reg);
2121
2122 // Long division/remainder for Java
2123 // (as idivq, but checks for special case as described in JVM spec.)
2124 // returns idivq instruction offset for implicit exception handling
2125 int corrected_idivq(Register reg);
2126
2127 void int3();
2128
2129 // Long operation macros for a 32bit cpu
2130 // Long negation for Java
2131 void lneg(Register hi, Register lo);
2132
2133 // Long multiplication for Java
2134 // (destroys contents of eax, ebx, ecx and edx)
2135 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
2136
2137 // Long shifts for Java
2138 // (semantics as described in JVM spec.)
2139 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
2140 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
2141
2142 // Long compare for Java
2143 // (semantics as described in JVM spec.)
2144 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
2145
2146
2147 // misc
2148
2149 // Sign extension
2150 void sign_extend_short(Register reg);
2151 void sign_extend_byte(Register reg);
2152
2153 // Division by power of 2, rounding towards 0
2154 void division_with_shift(Register reg, int shift_value);
2155
2156 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
2157 //
2158 // CF (corresponds to C0) if x < y
2159 // PF (corresponds to C2) if unordered
2160 // ZF (corresponds to C3) if x = y
2161 //
2162 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2163 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
2164 void fcmp(Register tmp);
2165 // Variant of the above which allows y to be further down the stack
2166 // and which only pops x and y if specified. If pop_right is
2167 // specified then pop_left must also be specified.
2168 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
2169
2170 // Floating-point comparison for Java
2171 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
2172 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
2173 // (semantics as described in JVM spec.)
2174 void fcmp2int(Register dst, bool unordered_is_less);
2175 // Variant of the above which allows y to be further down the stack
2176 // and which only pops x and y if specified. If pop_right is
2177 // specified then pop_left must also be specified.
2178 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
2179
2180 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
2181 // tmp is a temporary register, if none is available use noreg
2182 void fremr(Register tmp);
2183
2184
2185 // same as fcmp2int, but using SSE2
2186 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2187 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
2188
2189 // Inlined sin/cos generator for Java; must not use CPU instruction
2190 // directly on Intel as it does not have high enough precision
2191 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
2192 // number of FPU stack slots in use; all but the topmost will
2193 // require saving if a slow case is necessary. Assumes argument is
2194 // on FP TOS; result is on FP TOS. No cpu registers are changed by
2195 // this code.
2196 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
2197
2198 // branch to L if FPU flag C2 is set/not set
2199 // tmp is a temporary register, if none is available use noreg
2200 void jC2 (Register tmp, Label& L);
2201 void jnC2(Register tmp, Label& L);
2202
2203 // Pop ST (ffree & fincstp combined)
2204 void fpop();
2205
2206 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2207 void push_fTOS();
2208
2209 // pops double TOS element from CPU stack and pushes on FPU stack
2210 void pop_fTOS();
2211
2212 void empty_FPU_stack();
2213
2214 void push_IU_state();
2215 void pop_IU_state();
2216
2217 void push_FPU_state();
2218 void pop_FPU_state();
2219
2220 void push_CPU_state();
2221 void pop_CPU_state();
2222
2223 // Round up to a power of two
2224 void round_to(Register reg, int modulus);
2225
2226 // Callee saved registers handling
2227 void push_callee_saved_registers();
2228 void pop_callee_saved_registers();
2229
2230 // allocation
2231 void eden_allocate(
2232 Register obj, // result: pointer to object after successful allocation
2233 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2234 int con_size_in_bytes, // object size in bytes if known at compile time
2235 Register t1, // temp register
2236 Label& slow_case // continuation point if fast allocation fails
2237 );
2238 void tlab_allocate(
2239 Register obj, // result: pointer to object after successful allocation
2240 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2241 int con_size_in_bytes, // object size in bytes if known at compile time
2242 Register t1, // temp register
2243 Register t2, // temp register
2244 Label& slow_case // continuation point if fast allocation fails
2245 );
2246 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
2247 void incr_allocated_bytes(Register thread,
2248 Register var_size_in_bytes, int con_size_in_bytes,
2249 Register t1 = noreg);
2250
2251 // interface method calling
2252 void lookup_interface_method(Register recv_klass,
2253 Register intf_klass,
2254 RegisterOrConstant itable_index,
2255 Register method_result,
2256 Register scan_temp,
2257 Label& no_such_interface);
2258
2259 // virtual method calling
2260 void lookup_virtual_method(Register recv_klass,
2261 RegisterOrConstant vtable_index,
2262 Register method_result);
2263
2264 // Test sub_klass against super_klass, with fast and slow paths.
2265
2266 // The fast path produces a tri-state answer: yes / no / maybe-slow.
2267 // One of the three labels can be NULL, meaning take the fall-through.
2268 // If super_check_offset is -1, the value is loaded up from super_klass.
2269 // No registers are killed, except temp_reg.
2270 void check_klass_subtype_fast_path(Register sub_klass,
2271 Register super_klass,
2272 Register temp_reg,
2273 Label* L_success,
2274 Label* L_failure,
2275 Label* L_slow_path,
2276 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
2277
2278 // The rest of the type check; must be wired to a corresponding fast path.
2279 // It does not repeat the fast path logic, so don't use it standalone.
2280 // The temp_reg and temp2_reg can be noreg, if no temps are available.
2281 // Updates the sub's secondary super cache as necessary.
2282 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
2283 void check_klass_subtype_slow_path(Register sub_klass,
2284 Register super_klass,
2285 Register temp_reg,
2286 Register temp2_reg,
2287 Label* L_success,
2288 Label* L_failure,
2289 bool set_cond_codes = false);
2290
2291 // Simplified, combined version, good for typical uses.
2292 // Falls through on failure.
2293 void check_klass_subtype(Register sub_klass,
2294 Register super_klass,
2295 Register temp_reg,
2296 Label& L_success);
2297
2298 // method handles (JSR 292)
2299 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
2300
2301 //----
2302 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
2303
2304 // Debugging
2305
2306 // only if +VerifyOops
2307 // TODO: Make these macros with file and line like sparc version!
2308 void verify_oop(Register reg, const char* s = "broken oop");
2309 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
2310
2311 // TODO: verify method and klass metadata (compare against vptr?)
2312 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
2313 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
2314
2315 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
2316 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
2317
2318 // only if +VerifyFPU
2319 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2320
2321 // prints msg, dumps registers and stops execution
2322 void stop(const char* msg);
2323
2324 // prints msg and continues
2325 void warn(const char* msg);
2326
2327 // dumps registers and other state
2328 void print_state();
2329
2330 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
2331 static void debug64(char* msg, int64_t pc, int64_t regs[]);
2332 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
2333 static void print_state64(int64_t pc, int64_t regs[]);
2334
2335 void os_breakpoint();
2336
2337 void untested() { stop("untested"); }
2338
2339 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
2340
2341 void should_not_reach_here() { stop("should not reach here"); }
2342
2343 void print_CPU_state();
2344
2345 // Stack overflow checking
2346 void bang_stack_with_offset(int offset) {
2347 // stack grows down, caller passes positive offset
2348 assert(offset > 0, "must bang with negative offset");
2349 movl(Address(rsp, (-offset)), rax);
2350 }
2351
2352 // Writes to stack successive pages until offset reached to check for
2353 // stack overflow + shadow pages. Also, clobbers tmp
2354 void bang_stack_size(Register size, Register tmp);
2355
2356 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2357 Register tmp,
2358 int offset);
2359
2360 // Support for serializing memory accesses between threads
2361 void serialize_memory(Register thread, Register tmp);
2362
2363 void verify_tlab();
2364
2365 // Biased locking support
2366 // lock_reg and obj_reg must be loaded up with the appropriate values.
2367 // swap_reg must be rax, and is killed.
2368 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
2369 // be killed; if not supplied, push/pop will be used internally to
2370 // allocate a temporary (inefficient, avoid if possible).
2371 // Optional slow case is for implementations (interpreter and C1) which branch to
2372 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
2373 // Returns offset of first potentially-faulting instruction for null
2374 // check info (currently consumed only by C1). If
2375 // swap_reg_contains_mark is true then returns -1 as it is assumed
2376 // the calling code has already passed any potential faults.
2377 int biased_locking_enter(Register lock_reg, Register obj_reg,
2378 Register swap_reg, Register tmp_reg,
2379 bool swap_reg_contains_mark,
2380 Label& done, Label* slow_case = NULL,
2381 BiasedLockingCounters* counters = NULL);
2382 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
2383
2384
2385 Condition negate_condition(Condition cond);
2386
2387 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
2388 // operands. In general the names are modified to avoid hiding the instruction in Assembler
2389 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
2390 // here in MacroAssembler. The major exception to this rule is call
2391
2392 // Arithmetics
2393
2394
2395 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2396 void addptr(Address dst, Register src);
2397
2398 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2399 void addptr(Register dst, int32_t src);
2400 void addptr(Register dst, Register src);
2401 void addptr(Register dst, RegisterOrConstant src) {
2402 if (src.is_constant()) addptr(dst, (int) src.as_constant());
2403 else addptr(dst, src.as_register());
2404 }
2405
2406 void andptr(Register dst, int32_t src);
2407 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2408
2409 void cmp8(AddressLiteral src1, int imm);
2410
2411 // renamed to drag out the casting of address to int32_t/intptr_t
2412 void cmp32(Register src1, int32_t imm);
2413
2414 void cmp32(AddressLiteral src1, int32_t imm);
2415 // compare reg - mem, or reg - &mem
2416 void cmp32(Register src1, AddressLiteral src2);
2417
2418 void cmp32(Register src1, Address src2);
2419
2420 #ifndef _LP64
2421 void cmpklass(Address dst, Metadata* obj);
2422 void cmpklass(Register dst, Metadata* obj);
2423 void cmpoop(Address dst, jobject obj);
2424 void cmpoop(Register dst, jobject obj);
2425 #endif // _LP64
2426
2427 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2428 void cmpptr(Address src1, AddressLiteral src2);
2429
2430 void cmpptr(Register src1, AddressLiteral src2);
2431
2432 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2433 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2434 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2435
2436 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2437 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2438
2439 // cmp64 to avoild hiding cmpq
2440 void cmp64(Register src1, AddressLiteral src);
2441
2442 void cmpxchgptr(Register reg, Address adr);
2443
2444 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2445
2446
2447 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2448
2449
2450 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2451
2452 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2453
2454 void shlptr(Register dst, int32_t shift);
2455 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2456
2457 void shrptr(Register dst, int32_t shift);
2458 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2459
2460 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2461 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2462
2463 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2464
2465 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2466 void subptr(Register dst, int32_t src);
2467 // Force generation of a 4 byte immediate value even if it fits into 8bit
2468 void subptr_imm32(Register dst, int32_t src);
2469 void subptr(Register dst, Register src);
2470 void subptr(Register dst, RegisterOrConstant src) {
2471 if (src.is_constant()) subptr(dst, (int) src.as_constant());
2472 else subptr(dst, src.as_register());
2473 }
2474
2475 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2476 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2477
2478 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2479 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2480
2481 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2482
2483
2484
2485 // Helper functions for statistics gathering.
2486 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2487 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2488 // Unconditional atomic increment.
2489 void atomic_incl(AddressLiteral counter_addr);
2490
2491 void lea(Register dst, AddressLiteral adr);
2492 void lea(Address dst, AddressLiteral adr);
2493 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2494
2495 void leal32(Register dst, Address src) { leal(dst, src); }
2496
2497 // Import other testl() methods from the parent class or else
2498 // they will be hidden by the following overriding declaration.
2499 using Assembler::testl;
2500 void testl(Register dst, AddressLiteral src);
2501
2502 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2503 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2504 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2505
2506 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2507 void testptr(Register src1, Register src2);
2508
2509 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2510 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2511
2512 // Calls
2513
2514 void call(Label& L, relocInfo::relocType rtype);
2515 void call(Register entry);
2516
2517 // NOTE: this call tranfers to the effective address of entry NOT
2518 // the address contained by entry. This is because this is more natural
2519 // for jumps/calls.
2520 void call(AddressLiteral entry);
2521
2522 // Emit the CompiledIC call idiom
2523 void ic_call(address entry);
2524
2525 // Jumps
2526
2527 // NOTE: these jumps tranfer to the effective address of dst NOT
2528 // the address contained by dst. This is because this is more natural
2529 // for jumps/calls.
2530 void jump(AddressLiteral dst);
2531 void jump_cc(Condition cc, AddressLiteral dst);
2532
2533 // 32bit can do a case table jump in one instruction but we no longer allow the base
2534 // to be installed in the Address class. This jump will tranfers to the address
2535 // contained in the location described by entry (not the address of entry)
2536 void jump(ArrayAddress entry);
2537
2538 // Floating
2539
2540 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2541 void andpd(XMMRegister dst, AddressLiteral src);
2542
2543 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
2544 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
2545 void andps(XMMRegister dst, AddressLiteral src);
2546
2547 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
2548 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2549 void comiss(XMMRegister dst, AddressLiteral src);
2550
2551 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
2552 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2553 void comisd(XMMRegister dst, AddressLiteral src);
2554
2555 void fadd_s(Address src) { Assembler::fadd_s(src); }
2556 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2557
2558 void fldcw(Address src) { Assembler::fldcw(src); }
2559 void fldcw(AddressLiteral src);
2560
2561 void fld_s(int index) { Assembler::fld_s(index); }
2562 void fld_s(Address src) { Assembler::fld_s(src); }
2563 void fld_s(AddressLiteral src);
2564
2565 void fld_d(Address src) { Assembler::fld_d(src); }
2566 void fld_d(AddressLiteral src);
2567
2568 void fld_x(Address src) { Assembler::fld_x(src); }
2569 void fld_x(AddressLiteral src);
2570
2571 void fmul_s(Address src) { Assembler::fmul_s(src); }
2572 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2573
2574 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2575 void ldmxcsr(AddressLiteral src);
2576
2577 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
2578 // all corner cases and may result in NaN and require fallback to a
2579 // runtime call.
2580 void fast_pow();
2581 void fast_exp();
2582 void increase_precision();
2583 void restore_precision();
2584
2585 // computes exp(x). Fallback to runtime call included.
2586 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
2587 // computes pow(x,y). Fallback to runtime call included.
2588 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
2589
2590 private:
2591
2592 // call runtime as a fallback for trig functions and pow/exp.
2593 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
2594
2595 // computes 2^(Ylog2X); Ylog2X in ST(0)
2596 void pow_exp_core_encoding();
2597
2598 // computes pow(x,y) or exp(x). Fallback to runtime call included.
2599 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
2600
2601 // these are private because users should be doing movflt/movdbl
2602
2603 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2604 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2605 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2606 void movss(XMMRegister dst, AddressLiteral src);
2607
2608 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2609 void movlpd(XMMRegister dst, AddressLiteral src);
2610
2611 public:
2612
2613 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2614 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2615 void addsd(XMMRegister dst, AddressLiteral src);
2616
2617 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2618 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2619 void addss(XMMRegister dst, AddressLiteral src);
2620
2621 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2622 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2623 void divsd(XMMRegister dst, AddressLiteral src);
2624
2625 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2626 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2627 void divss(XMMRegister dst, AddressLiteral src);
2628
2629 // Move Unaligned Double Quadword
2630 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2631 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
2632 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
2633 void movdqu(XMMRegister dst, AddressLiteral src);
2634
2635 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2636 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2637 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2638 void movsd(XMMRegister dst, AddressLiteral src);
2639
2640 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2641 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2642 void mulsd(XMMRegister dst, AddressLiteral src);
2643
2644 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2645 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2646 void mulss(XMMRegister dst, AddressLiteral src);
2647
2648 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2649 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2650 void sqrtsd(XMMRegister dst, AddressLiteral src);
2651
2652 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2653 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2654 void sqrtss(XMMRegister dst, AddressLiteral src);
2655
2656 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2657 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2658 void subsd(XMMRegister dst, AddressLiteral src);
2659
2660 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2661 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2662 void subss(XMMRegister dst, AddressLiteral src);
2663
2664 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2665 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2666 void ucomiss(XMMRegister dst, AddressLiteral src);
2667
2668 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2669 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2670 void ucomisd(XMMRegister dst, AddressLiteral src);
2671
2672 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2673 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2674 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2675 void xorpd(XMMRegister dst, AddressLiteral src);
2676
2677 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2678 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2679 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2680 void xorps(XMMRegister dst, AddressLiteral src);
2681
2682 // Shuffle Bytes
2683 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
2684 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
2685 void pshufb(XMMRegister dst, AddressLiteral src);
2686 // AVX 3-operands instructions
2687
2688 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
2689 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
2690 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2691
2692 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2693 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2694 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2695
2696 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2697 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2698 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2699
2700 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2701 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2702 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2703
2704 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2705 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2706 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2707
2708 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
2709 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
2710 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2711
2712 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
2713 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
2714 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2715
2716 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
2717 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
2718 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2719
2720 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
2721 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
2722 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2723
2724 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
2725 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
2726 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2727
2728 // AVX Vector instructions
2729
2730 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2731 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2732 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2733
2734 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2735 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2736 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2737
2738 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2739 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2740 Assembler::vpxor(dst, nds, src, vector256);
2741 else
2742 Assembler::vxorpd(dst, nds, src, vector256);
2743 }
2744 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2745 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2746 Assembler::vpxor(dst, nds, src, vector256);
2747 else
2748 Assembler::vxorpd(dst, nds, src, vector256);
2749 }
2750
2751 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
2752 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2753 if (UseAVX > 1) // vinserti128h is available only in AVX2
2754 Assembler::vinserti128h(dst, nds, src);
2755 else
2756 Assembler::vinsertf128h(dst, nds, src);
2757 }
2758
2759 // Data
2760
2761 void cmov32( Condition cc, Register dst, Address src);
2762 void cmov32( Condition cc, Register dst, Register src);
2763
2764 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2765
2766 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2767 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2768
2769 void movoop(Register dst, jobject obj);
2770 void movoop(Address dst, jobject obj);
2771
2772 void mov_metadata(Register dst, Metadata* obj);
2773 void mov_metadata(Address dst, Metadata* obj);
2774
2775 void movptr(ArrayAddress dst, Register src);
2776 // can this do an lea?
2777 void movptr(Register dst, ArrayAddress src);
2778
2779 void movptr(Register dst, Address src);
2780
2781 void movptr(Register dst, AddressLiteral src);
2782
2783 void movptr(Register dst, intptr_t src);
2784 void movptr(Register dst, Register src);
2785 void movptr(Address dst, intptr_t src);
2786
2787 void movptr(Address dst, Register src);
2788
2789 void movptr(Register dst, RegisterOrConstant src) {
2790 if (src.is_constant()) movptr(dst, src.as_constant());
2791 else movptr(dst, src.as_register());
2792 }
2793
2794 #ifdef _LP64
2795 // Generally the next two are only used for moving NULL
2796 // Although there are situations in initializing the mark word where
2797 // they could be used. They are dangerous.
2798
2799 // They only exist on LP64 so that int32_t and intptr_t are not the same
2800 // and we have ambiguous declarations.
2801
2802 void movptr(Address dst, int32_t imm32);
2803 void movptr(Register dst, int32_t imm32);
2804 #endif // _LP64
2805
2806 // to avoid hiding movl
2807 void mov32(AddressLiteral dst, Register src);
2808 void mov32(Register dst, AddressLiteral src);
2809
2810 // to avoid hiding movb
2811 void movbyte(ArrayAddress dst, int src);
2812
2813 // Import other mov() methods from the parent class or else
2814 // they will be hidden by the following overriding declaration.
2815 using Assembler::movdl;
2816 using Assembler::movq;
2817 void movdl(XMMRegister dst, AddressLiteral src);
2818 void movq(XMMRegister dst, AddressLiteral src);
2819
2820 // Can push value or effective address
2821 void pushptr(AddressLiteral src);
2822
2823 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2824 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2825
2826 void pushoop(jobject obj);
2827 void pushklass(Metadata* obj);
2828
2829 // sign extend as need a l to ptr sized element
2830 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2831 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2832
2833 // C2 compiled method's prolog code.
2834 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
2835
2836 // IndexOf strings.
2837 // Small strings are loaded through stack if they cross page boundary.
2838 void string_indexof(Register str1, Register str2,
2839 Register cnt1, Register cnt2,
2840 int int_cnt2, Register result,
2841 XMMRegister vec, Register tmp);
2842
2843 // IndexOf for constant substrings with size >= 8 elements
2844 // which don't need to be loaded through stack.
2845 void string_indexofC8(Register str1, Register str2,
2846 Register cnt1, Register cnt2,
2847 int int_cnt2, Register result,
2848 XMMRegister vec, Register tmp);
2849
2850 // Smallest code: we don't need to load through stack,
2851 // check string tail.
2852
2853 // Compare strings.
2854 void string_compare(Register str1, Register str2,
2855 Register cnt1, Register cnt2, Register result,
2856 XMMRegister vec1);
2857
2858 // Compare char[] arrays.
2859 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2860 Register limit, Register result, Register chr,
2861 XMMRegister vec1, XMMRegister vec2);
2862
2863 // Fill primitive arrays
2864 void generate_fill(BasicType t, bool aligned,
2865 Register to, Register value, Register count,
2866 Register rtmp, XMMRegister xtmp);
2867
2868 #undef VIRTUAL
2869
2870 };
2871
2872 /**
2873 * class SkipIfEqual:
2874 *
2875 * Instantiating this class will result in assembly code being output that will
2876 * jump around any code emitted between the creation of the instance and it's
2877 * automatic destruction at the end of a scope block, depending on the value of
2878 * the flag passed to the constructor, which will be checked at run-time.
2879 */
2880 class SkipIfEqual {
2881 private:
2882 MacroAssembler* _masm;
2883 Label _label;
2884
2885 public:
2886 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2887 ~SkipIfEqual();
2888 };
2889
2890 #ifdef ASSERT
2891 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2892 #endif
2893
2894 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP 1773 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP