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comparison src/cpu/sparc/vm/vm_version_sparc.cpp @ 20421:d635fd1ac81c

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8056124: Hotspot should use PICL interface to get cacheline size on SPARC Summary: Using libpicl to get L1 data and L2 cache line sizes Reviewed-by: kvn, roland, morris
author iveresov
date Mon, 08 Sep 2014 18:11:37 -0700
parents b20a35eae442
children 7848fc12602b f79d8e8caecb
comparison
equal deleted inserted replaced
20419:2219e830b668 20421:d635fd1ac81c
35 # include "os_solaris.inline.hpp" 35 # include "os_solaris.inline.hpp"
36 #endif 36 #endif
37 37
38 int VM_Version::_features = VM_Version::unknown_m; 38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = ""; 39 const char* VM_Version::_features_str = "";
40 unsigned int VM_Version::_L2_cache_line_size = 0;
40 41
41 void VM_Version::initialize() { 42 void VM_Version::initialize() {
42 _features = determine_features(); 43 _features = determine_features();
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 44 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 45 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
195 warning("CBCOND instruction is not available on this CPU"); 196 warning("CBCOND instruction is not available on this CPU");
196 FLAG_SET_DEFAULT(UseCBCond, false); 197 FLAG_SET_DEFAULT(UseCBCond, false);
197 } 198 }
198 199
199 assert(BlockZeroingLowLimit > 0, "invalid value"); 200 assert(BlockZeroingLowLimit > 0, "invalid value");
200 if (has_block_zeroing()) { 201 if (has_block_zeroing() && cache_line_size > 0) {
201 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 202 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
202 FLAG_SET_DEFAULT(UseBlockZeroing, true); 203 FLAG_SET_DEFAULT(UseBlockZeroing, true);
203 } 204 }
204 } else if (UseBlockZeroing) { 205 } else if (UseBlockZeroing) {
205 warning("BIS zeroing instructions are not available on this CPU"); 206 warning("BIS zeroing instructions are not available on this CPU");
206 FLAG_SET_DEFAULT(UseBlockZeroing, false); 207 FLAG_SET_DEFAULT(UseBlockZeroing, false);
207 } 208 }
208 209
209 assert(BlockCopyLowLimit > 0, "invalid value"); 210 assert(BlockCopyLowLimit > 0, "invalid value");
210 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache 211 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
211 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 212 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
212 FLAG_SET_DEFAULT(UseBlockCopy, true); 213 FLAG_SET_DEFAULT(UseBlockCopy, true);
213 } 214 }
214 } else if (UseBlockCopy) { 215 } else if (UseBlockCopy) {
215 warning("BIS instructions are not available or expensive on this CPU"); 216 warning("BIS instructions are not available or expensive on this CPU");
360 (cache_line_size > ContendedPaddingWidth)) 361 (cache_line_size > ContendedPaddingWidth))
361 ContendedPaddingWidth = cache_line_size; 362 ContendedPaddingWidth = cache_line_size;
362 363
363 #ifndef PRODUCT 364 #ifndef PRODUCT
364 if (PrintMiscellaneous && Verbose) { 365 if (PrintMiscellaneous && Verbose) {
366 tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
365 tty->print("Allocation"); 367 tty->print("Allocation");
366 if (AllocatePrefetchStyle <= 0) { 368 if (AllocatePrefetchStyle <= 0) {
367 tty->print_cr(": no prefetching"); 369 tty->print_cr(": no prefetching");
368 } else { 370 } else {
369 tty->print(" prefetching: "); 371 tty->print(" prefetching: ");