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comparison src/os_cpu/linux_x86/vm/orderAccess_linux_x86.inline.hpp @ 3308:da880ba4edf9

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7031385: incorrect register allocation in release_store_fence on linux x86 Summary: Since gcc 4.5 the inline assembly trying to use r register for an atomic 8-bit exchange and it leads to compilation error Reviewed-by: dsamersoff, dholmes Contributed-by: dbhole@redhat.com
author dsamersoff
date Tue, 03 May 2011 18:43:18 +0400
parents 4fc084dac61e
children 63e54c37ac64
comparison
equal deleted inserted replaced
3306:405c634f4aaa 3308:da880ba4edf9
91 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; } 91 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; }
92 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; } 92 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; }
93 93
94 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { 94 inline void OrderAccess::store_fence(jbyte* p, jbyte v) {
95 __asm__ volatile ( "xchgb (%2),%0" 95 __asm__ volatile ( "xchgb (%2),%0"
96 : "=r" (v) 96 : "=q" (v)
97 : "0" (v), "r" (p) 97 : "0" (v), "r" (p)
98 : "memory"); 98 : "memory");
99 } 99 }
100 inline void OrderAccess::store_fence(jshort* p, jshort v) { 100 inline void OrderAccess::store_fence(jshort* p, jshort v) {
101 __asm__ volatile ( "xchgw (%2),%0" 101 __asm__ volatile ( "xchgw (%2),%0"
153 } 153 }
154 154
155 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile. 155 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile.
156 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { 156 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) {
157 __asm__ volatile ( "xchgb (%2),%0" 157 __asm__ volatile ( "xchgb (%2),%0"
158 : "=r" (v) 158 : "=q" (v)
159 : "0" (v), "r" (p) 159 : "0" (v), "r" (p)
160 : "memory"); 160 : "memory");
161 } 161 }
162 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { 162 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) {
163 __asm__ volatile ( "xchgw (%2),%0" 163 __asm__ volatile ( "xchgw (%2),%0"