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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 1513:df736661d0c8

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Merge
author jrose
date Tue, 11 May 2010 15:19:19 -0700
parents befdf73d6b82 c640000b7cc1
children fb1a39993f69 61b2245abf36
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1496:e8e83be27dd7 1513:df736661d0c8
1 /* 1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. 2 * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
1378 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1378 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1379 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1379 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1380 1380
1381 // pp 181 1381 // pp 181
1382 1382
1383 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } 1383 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1384 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1384 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1385 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1385 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1386 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1386 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1387 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } 1387 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1388 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1388 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1389 void andn( Register s1, RegisterOrConstant s2, Register d);
1389 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1390 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1390 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1391 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1391 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } 1392 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1392 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1393 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1393 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1394 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1394 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1395 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1395 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } 1396 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1396 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1397 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1397 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1398 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1398 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1399 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1399 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } 1400 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1400 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1401 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1401 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1402 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1402 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1403 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1403 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } 1404 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1404 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1405 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1405 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1406 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
2024 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 2025 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
2025 inline void ld_ptr(Register s1, ByteSize simm13a, Register d); 2026 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
2026 inline void st_ptr(Register d, Register s1, ByteSize simm13a); 2027 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
2027 #endif 2028 #endif
2028 2029
2029 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's 2030 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
2030 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's 2031 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
2031 inline void ld_long(Register s1, Register s2, Register d); 2032 inline void ld_long(Register s1, Register s2, Register d);
2032 inline void ld_long(Register s1, int simm13a, Register d); 2033 inline void ld_long(Register s1, int simm13a, Register d);
2033 inline void ld_long(Register s1, RegisterOrConstant s2, Register d); 2034 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
2034 inline void ld_long(const Address& a, Register d, int offset = 0); 2035 inline void ld_long(const Address& a, Register d, int offset = 0);
2035 inline void st_long(Register d, Register s1, Register s2); 2036 inline void st_long(Register d, Register s1, Register s2);
2036 inline void st_long(Register d, Register s1, int simm13a); 2037 inline void st_long(Register d, Register s1, int simm13a);
2037 inline void st_long(Register d, Register s1, RegisterOrConstant s2); 2038 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
2038 inline void st_long(Register d, const Address& a, int offset = 0); 2039 inline void st_long(Register d, const Address& a, int offset = 0);
2039 2040
2040 // Helpers for address formation. 2041 // Helpers for address formation.
2041 // They update the dest in place, whether it is a register or constant. 2042 // - They emit only a move if s2 is a constant zero.
2042 // They emit no code at all if src is a constant zero. 2043 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
2043 // If dest is a constant and src is a register, the temp argument 2044 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
2044 // is required, and becomes the result. 2045 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2045 // If dest is a register and src is a non-simm13 constant, 2046 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2046 // the temp argument is required, and is used to materialize the constant. 2047 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
2047 void regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src, 2048
2048 Register temp = noreg ); 2049 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
2049 void regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src, 2050 if (is_simm13(src.constant_or_zero()))
2050 Register temp = noreg ); 2051 return src; // register or short constant
2051 2052 guarantee(temp != noreg, "constant offset overflow");
2052 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant roc, Register Rtemp) { 2053 set(src.as_constant(), temp);
2053 guarantee(Rtemp != noreg, "constant offset overflow"); 2054 return temp;
2054 if (is_simm13(roc.constant_or_zero()))
2055 return roc; // register or short constant
2056 set(roc.as_constant(), Rtemp);
2057 return RegisterOrConstant(Rtemp);
2058 } 2055 }
2059 2056
2060 // -------------------------------------------------- 2057 // --------------------------------------------------
2061 2058
2062 public: 2059 public:
2300 Register Rout_high, Register Rout_low, Register Rtemp ); 2297 Register Rout_high, Register Rout_low, Register Rtemp );
2301 2298
2302 #ifdef _LP64 2299 #ifdef _LP64
2303 void lcmp( Register Ra, Register Rb, Register Rresult); 2300 void lcmp( Register Ra, Register Rb, Register Rresult);
2304 #endif 2301 #endif
2302
2303 // Loading values by size and signed-ness
2304 void load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed);
2305 2305
2306 void float_cmp( bool is_float, int unordered_result, 2306 void float_cmp( bool is_float, int unordered_result,
2307 FloatRegister Fa, FloatRegister Fb, 2307 FloatRegister Fa, FloatRegister Fb,
2308 Register Rresult); 2308 Register Rresult);
2309 2309
2419 2419
2420 // method handles (JSR 292) 2420 // method handles (JSR 292)
2421 void check_method_handle_type(Register mtype_reg, Register mh_reg, 2421 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2422 Register temp_reg, 2422 Register temp_reg,
2423 Label& wrong_method_type); 2423 Label& wrong_method_type);
2424 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); 2424 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
2425 Register temp_reg);
2426 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true);
2425 // offset relative to Gargs of argument at tos[arg_slot]. 2427 // offset relative to Gargs of argument at tos[arg_slot].
2426 // (arg_slot == 0 means the last argument, not the first). 2428 // (arg_slot == 0 means the last argument, not the first).
2427 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, 2429 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
2428 int extra_slot_offset = 0); 2430 int extra_slot_offset = 0);
2429 2431 // Address of Gargs and argument_offset.
2432 Address argument_address(RegisterOrConstant arg_slot,
2433 int extra_slot_offset = 0);
2430 2434
2431 // Stack overflow checking 2435 // Stack overflow checking
2432 2436
2433 // Note: this clobbers G3_scratch 2437 // Note: this clobbers G3_scratch
2434 void bang_stack_with_offset(int offset) { 2438 void bang_stack_with_offset(int offset) {