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comparison src/cpu/x86/vm/nativeInst_x86.hpp @ 5840:f565e8d4d200

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parsing and patching of variable sized NativeCallReg instructions now works properly
author Doug Simon <doug.simon@oracle.com>
date Mon, 16 Jul 2012 15:19:25 +0200
parents b5dc2403c1e7
children a413bcd552a4
comparison
equal deleted inserted replaced
5839:58a607307306 5840:f565e8d4d200
184 184
185 class NativeCallReg: public NativeInstruction { 185 class NativeCallReg: public NativeInstruction {
186 public: 186 public:
187 enum Intel_specific_constants { 187 enum Intel_specific_constants {
188 instruction_code = 0xFF, 188 instruction_code = 0xFF,
189 instruction_size = 2, 189 instruction_offset = 0,
190 instruction_offset = 0, 190 return_address_offset_norex = 2,
191 return_address_offset = 2 191 return_address_offset_rex = 3
192 }; 192 };
193 193
194 address instruction_address() const { return addr_at(instruction_offset); } 194 int next_instruction_offset() const {
195 address next_instruction_address() const { return addr_at(return_address_offset); } 195 if (ubyte_at(0) == NativeCallReg::instruction_code) {
196 196 return return_address_offset_norex;
197 197 } else {
198 static bool is_call_reg_at(address instr) { 198 return return_address_offset_rex;
199 return ((*instr) & 0xFF) == NativeCallReg::instruction_code; 199 }
200 }
201
202 static bool is_call_reg_before(address return_address) {
203 return is_call_reg_at(return_address - NativeCallReg::return_address_offset);
204 } 200 }
205 }; 201 };
206 202
207 // An interface for accessing/manipulating native mov reg, imm32 instructions. 203 // An interface for accessing/manipulating native mov reg, imm32 instructions.
208 // (used to manipulate inlined 32bit data dll calls, etc.) 204 // (used to manipulate inlined 32bit data dll calls, etc.)
553 }; 549 };
554 }; 550 };
555 551
556 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } 552 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
557 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } 553 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
558 inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code; } 554 inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code ||
555 (ubyte_at(1) == NativeCallReg::instruction_code &&
556 (ubyte_at(0) == Assembler::REX || ubyte_at(0) == Assembler::REX_B)); }
559 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || 557 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
560 ubyte_at(0) == NativeReturnX::instruction_code; } 558 ubyte_at(0) == NativeReturnX::instruction_code; }
561 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || 559 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
562 ubyte_at(0) == 0xEB; /* short jump */ } 560 ubyte_at(0) == 0xEB; /* short jump */ }
563 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || 561 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||