Mercurial > hg > graal-jvmci-8
diff src/cpu/sparc/vm/vm_version_sparc.cpp @ 17910:03214612e77e
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
Summary: Fix the arbitrary alignment issue in SPARC AES crypto stub routines.
Reviewed-by: kvn, iveresov
Contributed-by: shrinivas.joshi@oracle.com
author | kvn |
---|---|
date | Wed, 30 Apr 2014 14:14:01 -0700 |
parents | 04d32e7fad07 |
children | 78bbf4d43a14 |
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--- a/src/cpu/sparc/vm/vm_version_sparc.cpp Thu May 01 15:02:46 2014 -0700 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Wed Apr 30 14:14:01 2014 -0700 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -266,9 +266,9 @@ if (!has_vis1()) // Drop to 0 if no VIS1 support UseVIS = 0; - // T2 and above should have support for AES instructions + // SPARC T4 and above should have support for AES instructions if (has_aes()) { - if (UseVIS > 0) { // AES intrinsics use FXOR instruction which is VIS1 + if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 if (FLAG_IS_DEFAULT(UseAES)) { FLAG_SET_DEFAULT(UseAES, true); } @@ -282,7 +282,7 @@ } } else { if (UseAES || UseAESIntrinsics) { - warning("SPARC AES intrinsics require VIS1 instruction support. Intrinsics will be disabled."); + warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); if (UseAES) { FLAG_SET_DEFAULT(UseAES, false); }