Mercurial > hg > graal-jvmci-8

diff src/cpu/sparc/vm/vm_version_sparc.cpp @ 22963:f79d8e8caecb

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8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect Summary: Chcek both l2-dcache-line-size and l2-cache-line-size properties to determine the size of the line Reviewed-by: kvn
author iveresov
date Fri, 10 Apr 2015 15:27:05 -0700
parents d635fd1ac81c
children dd9cc155639c d2dd79a4fd69
line wrap: on
line diff
--- a/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Apr 10 15:24:50 2015 -0700
+++ b/src/cpu/sparc/vm/vm_version_sparc.cpp	Fri Apr 10 15:27:05 2015 -0700
@@ -37,7 +37,7 @@
 
 int VM_Version::_features = VM_Version::unknown_m;
 const char* VM_Version::_features_str = "";
-unsigned int VM_Version::_L2_cache_line_size = 0;
+unsigned int VM_Version::_L2_data_cache_line_size = 0;
 
 void VM_Version::initialize() {
   _features = determine_features();
@@ -363,7 +363,7 @@
 
 #ifndef PRODUCT
   if (PrintMiscellaneous && Verbose) {
-    tty->print_cr("L2 cache line size: %u", L2_cache_line_size());
+    tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
     tty->print("Allocation");
     if (AllocatePrefetchStyle <= 0) {
       tty->print_cr(": no prefetching");