Mercurial > hg > graal-jvmci-8
view graal/com.oracle.graal.ptx/src/com/oracle/graal/ptx/PTX.java @ 7804:447f9ba1962b
Experimental PTX backend. Contribution by Christian Thalinger.
author | Thomas Wuerthinger <thomas.wuerthinger@oracle.com> |
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date | Mon, 18 Feb 2013 14:47:54 -0800 |
parents | |
children | 3ec29630cfb4 |
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/* * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. */ package com.oracle.graal.ptx; import static com.oracle.graal.api.code.MemoryBarriers.*; import static com.oracle.graal.api.code.Register.RegisterFlag.*; import java.nio.*; import com.oracle.graal.api.code.*; import com.oracle.graal.api.code.Register.*; /** * Represents the PTX architecture. */ public class PTX extends Architecture { // @formatter:off /* * Register State Space * * Registers (.reg state space) are fast storage locations. The number of * registers is limited, and will vary from platform to platform. When the * limit is exceeded, register variables will be spilled to memory, causing * changes in performance. For each architecture, there is a recommended * maximum number of registers to use (see the "CUDA Programming Guide" for * details). */ // General purpose registers public static final Register r0 = new Register(0, 0, 8, "r0", CPU, RegisterFlag.Byte); public static final Register r1 = new Register(1, 1, 8, "r1", CPU, RegisterFlag.Byte); public static final Register r2 = new Register(2, 2, 8, "r2", CPU, RegisterFlag.Byte); public static final Register r3 = new Register(3, 3, 8, "r3", CPU, RegisterFlag.Byte); public static final Register r4 = new Register(4, 4, 8, "r4", CPU, RegisterFlag.Byte); public static final Register r5 = new Register(5, 5, 8, "r5", CPU, RegisterFlag.Byte); public static final Register r6 = new Register(6, 6, 8, "r6", CPU, RegisterFlag.Byte); public static final Register r7 = new Register(7, 7, 8, "r7", CPU, RegisterFlag.Byte); public static final Register r8 = new Register(8, 8, 8, "r8", CPU, RegisterFlag.Byte); public static final Register r9 = new Register(9, 9, 8, "r9", CPU, RegisterFlag.Byte); public static final Register r10 = new Register(10, 10, 8, "r10", CPU, RegisterFlag.Byte); public static final Register r11 = new Register(11, 11, 8, "r11", CPU, RegisterFlag.Byte); public static final Register r12 = new Register(12, 12, 8, "r12", CPU, RegisterFlag.Byte); public static final Register r13 = new Register(13, 13, 8, "r13", CPU, RegisterFlag.Byte); public static final Register r14 = new Register(14, 14, 8, "r14", CPU, RegisterFlag.Byte); public static final Register r15 = new Register(15, 15, 8, "r15", CPU, RegisterFlag.Byte); public static final Register[] gprRegisters = { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 }; // Floating point registers public static final Register f0 = new Register(16, 0, 8, "f0", FPU); public static final Register f1 = new Register(17, 1, 8, "f1", FPU); public static final Register f2 = new Register(18, 2, 8, "f2", FPU); public static final Register f3 = new Register(19, 3, 8, "f3", FPU); public static final Register f4 = new Register(20, 4, 8, "f4", FPU); public static final Register f5 = new Register(21, 5, 8, "f5", FPU); public static final Register f6 = new Register(22, 6, 8, "f6", FPU); public static final Register f7 = new Register(23, 7, 8, "f7", FPU); public static final Register f8 = new Register(24, 8, 8, "f8", FPU); public static final Register f9 = new Register(25, 9, 8, "f9", FPU); public static final Register f10 = new Register(26, 10, 8, "f10", FPU); public static final Register f11 = new Register(27, 11, 8, "f11", FPU); public static final Register f12 = new Register(28, 12, 8, "f12", FPU); public static final Register f13 = new Register(29, 13, 8, "f13", FPU); public static final Register f14 = new Register(30, 14, 8, "f14", FPU); public static final Register f15 = new Register(31, 15, 8, "f15", FPU); public static final Register[] fpuRegisters = { f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15 }; public static final Register[] allRegisters = { // GPR r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, // FPU f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15 }; public PTX() { super("PTX", 8, ByteOrder.LITTLE_ENDIAN, allRegisters, LOAD_STORE | STORE_STORE, 0, r15.encoding + 1, 8); } // @formatter:on }