Mercurial > hg > graal-jvmci-8
view graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64SignExtendOp.java @ 21673:5024c80224c7
moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
author | Doug Simon <doug.simon@oracle.com> |
---|---|
date | Tue, 02 Jun 2015 22:11:52 +0200 |
parents | 48c1ebd24120 |
children | 6df25b1418be |
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/* * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. */ package com.oracle.graal.lir.amd64; import com.oracle.jvmci.amd64.*; import com.oracle.jvmci.meta.AllocatableValue; import com.oracle.jvmci.meta.LIRKind; import static com.oracle.jvmci.code.ValueUtil.*; import static com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize.*; import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*; import com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize; import com.oracle.graal.asm.amd64.*; import com.oracle.graal.lir.*; import com.oracle.graal.lir.asm.*; @Opcode("CDQ") public class AMD64SignExtendOp extends AMD64LIRInstruction { public static final LIRInstructionClass<AMD64SignExtendOp> TYPE = LIRInstructionClass.create(AMD64SignExtendOp.class); private final OperandSize size; @Def({REG}) protected AllocatableValue highResult; @Def({REG}) protected AllocatableValue lowResult; @Use({REG}) protected AllocatableValue input; public AMD64SignExtendOp(OperandSize size, LIRKind resultKind, AllocatableValue input) { super(TYPE); this.size = size; this.highResult = AMD64.rdx.asValue(resultKind); this.lowResult = AMD64.rax.asValue(resultKind); this.input = input; } public AllocatableValue getHighResult() { return highResult; } public AllocatableValue getLowResult() { return lowResult; } @Override public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { if (size == DWORD) { masm.cdql(); } else { assert size == QWORD; masm.cdqq(); } } @Override public void verify() { assert asRegister(highResult).equals(AMD64.rdx); assert asRegister(lowResult).equals(AMD64.rax); assert asRegister(input).equals(AMD64.rax); } }