# HG changeset patch
# User Stefan Anzinger <stefan.anzinger@oracle.com>
# Date 1438933617 -7200
# Node ID b1c2b695554b1001ad0209fcc62833e56359688e
# Parent  708a95bb443cc0fa7ac2b11da293eb3d1f2aee49
[SPARC] Backout change 44ee46c753b1

diff -r 708a95bb443c -r b1c2b695554b src/cpu/sparc/vm/sparc.ad
--- a/src/cpu/sparc/vm/sparc.ad	Thu Aug 06 15:50:18 2015 +0200
+++ b/src/cpu/sparc/vm/sparc.ad	Fri Aug 07 09:46:57 2015 +0200
@@ -6355,18 +6355,17 @@
   ins_pipe(iload_mem);
 %}
 
-// Use PREFETCHA instruction to prefetch for allocation.
+// Use BIS instruction to prefetch for allocation.
 // Could fault, need space at the end of TLAB.
 instruct prefetchAlloc_bis( iRegP dst ) %{
   predicate(AllocatePrefetchInstr == 1);
   match( PrefetchAllocation dst );
   ins_cost(MEMORY_REF_COST);
   size(4);
-  // Using prefetcha insteadof stxa. Because stxa does write to the tlab 32 bytes with zero, which leads to an overzero of 
-  // TLAB which triggers assertion error in ThreadLocalAllocBuffer::clear_before_allocation
-  format %{ "PREFETCHA   [$dst] #ASI_BLK_INIT_QUAD_LDD_P, severalWritesAndPossiblyReads\t! // Prefetch allocation using PREFETCHA" %}
-  ins_encode %{
-    __ prefetcha($dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY,  Assembler::severalWritesAndPossiblyReads);
+
+  format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
+  ins_encode %{
+    __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
   %}
   ins_pipe(istore_mem_reg);
 %}