# HG changeset patch
# User Josef Eisl <josef.eisl@jku.at>
# Date 1431002847 -7200
# Node ID f172a195a8a9a899f2630ba5d0a872bf9be0c111
# Parent  43462ed89797520aae05334ed94c76deb71b76e9
mx gate: bootstrap with -G:+SSA_LIR.

diff -r 43462ed89797 -r f172a195a8a9 mx/mx_graal.py
--- a/mx/mx_graal.py	Thu May 21 11:54:22 2015 +0200
+++ b/mx/mx_graal.py	Thu May 07 14:47:27 2015 +0200
@@ -1686,6 +1686,12 @@
                 vm(['-XX:-TieredCompilation', '-G:RegisterPressure=' + registers, '-esa', '-version'])
 
     with VM('graal', 'product'):
+        with Task('BootstrapSSAWithRegisterPressure:product', tasks) as t:
+            if t:
+                registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14'
+                vm(['-XX:-TieredCompilation', '-G:+SSA_LIR', '-G:RegisterPressure=' + registers, '-esa', '-version'])
+
+    with VM('graal', 'product'):
         with Task('BootstrapWithImmutableCode:product', tasks) as t:
             if t: vm(['-XX:-TieredCompilation', '-G:+ImmutableCode', '-G:+VerifyPhases', '-esa', '-version'])