Mercurial > hg > graal-jvmci-8
changeset 21973:e23e6dc49a11
[SPARC] Make frem and drem SSA LIR ready
| author | Stefan Anzinger <stefan.anzinger@oracle.com> |
|---|---|
| date | Mon, 15 Jun 2015 14:25:29 +0200 |
| parents | bf2a8eb04fc8 |
| children | 7a0c8adc0a30 |
| files | graal/com.oracle.graal.compiler.sparc/src/com/oracle/graal/compiler/sparc/SPARCLIRGenerator.java |
| diffstat | 1 files changed, 22 insertions(+), 13 deletions(-) [+] |
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--- a/graal/com.oracle.graal.compiler.sparc/src/com/oracle/graal/compiler/sparc/SPARCLIRGenerator.java Mon Jun 15 13:49:38 2015 +0200 +++ b/graal/com.oracle.graal.compiler.sparc/src/com/oracle/graal/compiler/sparc/SPARCLIRGenerator.java Mon Jun 15 14:25:29 2015 +0200 @@ -634,7 +634,10 @@ @Override public Value emitRem(Value a, Value b, LIRFrameState state) { Variable result = newVariable(LIRKind.derive(a, b)); - Variable q = null; + Variable q1; // Intermediate values + Variable q2; + Variable q3; + Variable q4; switch (a.getKind().getStackKind()) { case Int: append(new RemOp(IREM, result, load(a), loadNonConst(b), state, this)); @@ -643,20 +646,26 @@ append(new RemOp(LREM, result, load(a), loadNonConst(b), state, this)); break; case Float: - q = newVariable(LIRKind.value(Kind.Float)); - append(new BinaryRegReg(FDIV, q, a, b, state)); - append(new Unary2Op(F2I, q, q)); - append(new Unary2Op(I2F, q, q)); - append(new BinaryRegReg(FMUL, q, q, b)); - append(new BinaryRegReg(FSUB, result, a, q)); + q1 = newVariable(LIRKind.value(Kind.Float)); + append(new BinaryRegReg(FDIV, q1, a, b, state)); + q2 = newVariable(LIRKind.value(Kind.Float)); + append(new Unary2Op(F2I, q2, q1)); + q3 = newVariable(LIRKind.value(Kind.Float)); + append(new Unary2Op(I2F, q3, q2)); + q4 = newVariable(LIRKind.value(Kind.Float)); + append(new BinaryRegReg(FMUL, q4, q3, b)); + append(new BinaryRegReg(FSUB, result, a, q4)); break; case Double: - q = newVariable(LIRKind.value(Kind.Double)); - append(new BinaryRegReg(DDIV, q, a, b, state)); - append(new Unary2Op(D2L, q, q)); - append(new Unary2Op(L2D, q, q)); - append(new BinaryRegReg(DMUL, q, q, b)); - append(new BinaryRegReg(DSUB, result, a, q)); + q1 = newVariable(LIRKind.value(Kind.Double)); + append(new BinaryRegReg(DDIV, q1, a, b, state)); + q2 = newVariable(LIRKind.value(Kind.Double)); + append(new Unary2Op(D2L, q2, q1)); + q3 = newVariable(LIRKind.value(Kind.Double)); + append(new Unary2Op(L2D, q3, q2)); + q4 = newVariable(LIRKind.value(Kind.Double)); + append(new BinaryRegReg(DMUL, q4, q3, b)); + append(new BinaryRegReg(DSUB, result, a, q4)); break; default: throw JVMCIError.shouldNotReachHere("missing: " + a.getKind());