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annotate graal/com.oracle.graal.lir.hsail/src/com/oracle/graal/lir/hsail/HSAILArithmetic.java @ 14044:0b3960586b48

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IGV: fix NPE
author Andreas Woess <andreas.woess@jku.at>
date Mon, 03 Mar 2014 12:04:16 +0100
parents 958c99d0790c
children 64dcb92ee75a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 /*
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2 * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 */
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23 package com.oracle.graal.lir.hsail;
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24
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25 import static com.oracle.graal.api.code.ValueUtil.*;
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26 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
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27
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28 import com.oracle.graal.api.meta.*;
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29 import com.oracle.graal.asm.hsail.*;
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30 import com.oracle.graal.graph.*;
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31 import com.oracle.graal.lir.*;
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32 import com.oracle.graal.lir.asm.CompilationResultBuilder;
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33
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34 /**
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35 * Defines arithmetic instruction nodes.
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36 */
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37 public enum HSAILArithmetic {
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38 ABS,
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39 CALL,
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40 CEIL,
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41 FDIV,
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42 FLOOR,
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43 FREM,
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44 DADD,
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45 DDIV,
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46 DMUL,
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47 DNEG,
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48 DREM,
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49 DSUB,
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50 FADD,
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51 FMUL,
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52 FNEG,
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53 FSUB,
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54 IADD,
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55 IAND,
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56 ICARRY,
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57 IDIV,
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58 IMAX,
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59 IMIN,
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60 IMUL,
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61 INEG,
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62 INOT,
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63 IOR,
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64 IREM,
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65 ISHL,
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66 ISHR,
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67 ISUB,
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68 IUADD,
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69 IUCARRY,
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70 IUDIV,
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71 IUMAX,
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72 IUMIN,
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73 IUMUL,
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74 IUREM,
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75 IUSHR,
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76 IUSUB,
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77 IXOR,
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78 LADD,
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79 LAND,
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80 LCARRY,
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81 LDIV,
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82 LMAX,
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83 LMIN,
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84 LMUL,
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85 LNEG,
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86 LNOT,
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87 LOR,
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88 LREM,
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89 LSHL,
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90 LSHR,
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91 LSUB,
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92 LUADD,
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93 LUCARRY,
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94 LUDIV,
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95 LUMAX,
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96 LUMIN,
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97 LUMUL,
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98 LUREM,
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99 LUSHR,
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100 LUSUB,
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101 LXOR,
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102 OADD,
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103 RINT,
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104 SQRT,
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105 UNDEF;
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106
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107 public static class ConvertOp extends HSAILLIRInstruction {
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108 private final String from;
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109 private final String to;
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110 @Def({REG}) protected AllocatableValue result;
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111 @Use({REG, STACK}) protected AllocatableValue x;
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112
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113 public ConvertOp(AllocatableValue result, AllocatableValue x, String to, String from) {
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114 this.from = from;
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115 this.to = to;
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116 this.result = result;
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117 this.x = x;
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118 }
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119
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120 @Override
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121 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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122 masm.emitConvert(result, x, to, from);
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123 }
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124 }
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125
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126 public static class Op1Stack extends HSAILLIRInstruction {
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127 @Opcode private final HSAILArithmetic opcode;
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128 @Def({REG, HINT}) protected Value result;
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129 @Use({REG, STACK, CONST}) protected Value x;
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130
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131 public Op1Stack(HSAILArithmetic opcode, Value result, Value x) {
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132 this.opcode = opcode;
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133 this.result = result;
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134 this.x = x;
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135 }
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136
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137 @Override
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138 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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139 emit(crb, masm, opcode, result, x, null);
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140 }
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141 }
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142
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143 public static class Op2Stack extends HSAILLIRInstruction {
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144 @Opcode private final HSAILArithmetic opcode;
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145 @Def({REG, HINT}) protected Value result;
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146 @Use({REG, CONST}) protected Value x;
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147 @Alive({REG, CONST}) protected Value y;
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148
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149 public Op2Stack(HSAILArithmetic opcode, Value result, Value x, Value y) {
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150 this.opcode = opcode;
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151 this.result = result;
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152 this.x = x;
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153 this.y = y;
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154 }
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155
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156 @Override
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157 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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158 emit(crb, masm, opcode, result, x, y, null);
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159 }
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160
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161 @Override
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162 public void verify() {
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163 super.verify();
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164 verifyKind(opcode, result, x, y);
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165 }
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166 }
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167
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168 public static class Op1Reg extends HSAILLIRInstruction {
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169 @Opcode private final HSAILArithmetic opcode;
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170 @Def({REG, HINT}) protected Value result;
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171 @Use({REG}) protected Value x;
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172
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173 public Op1Reg(HSAILArithmetic opcode, Value result, Value x) {
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174 this.opcode = opcode;
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175 this.result = result;
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176 this.x = x;
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177 }
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178
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179 @Override
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180 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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181 emit(crb, masm, opcode, result, x, null);
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182 }
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183 }
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184
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185 public static class Op2Reg extends HSAILLIRInstruction {
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186 @Opcode private final HSAILArithmetic opcode;
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187 @Def({REG, HINT}) protected Value result;
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188 @Use({REG, STACK, CONST}) protected Value x;
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189 @Alive({REG, CONST}) protected Value y;
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190
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191 public Op2Reg(HSAILArithmetic opcode, Value result, Value x, Value y) {
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192 this.opcode = opcode;
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193 this.result = result;
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194 this.x = x;
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195 this.y = y;
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196 }
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197
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198 @Override
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199 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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200 emit(crb, masm, opcode, result, x, y, null);
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201 }
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202
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203 @Override
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204 public void verify() {
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205 super.verify();
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206 verifyKind(opcode, result, x, y);
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207 }
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208 }
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209
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210 public static class Op2RegCommutative extends HSAILLIRInstruction {
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211 @Opcode private final HSAILArithmetic opcode;
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212 @Def({REG, HINT}) protected Value result;
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213 @Use({REG, STACK, CONST}) protected Value x;
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214 @Use({REG, CONST}) protected Value y;
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215
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216 public Op2RegCommutative(HSAILArithmetic opcode, Value result, Value x, Value y) {
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217 this.opcode = opcode;
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218 this.result = result;
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219 this.x = x;
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220 this.y = y;
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221 }
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222
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223 @Override
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224 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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225 throw GraalInternalError.shouldNotReachHere();
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226 }
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227
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228 @Override
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229 protected void verify() {
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230 super.verify();
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231 verifyKind(opcode, result, x, y);
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232 }
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233 }
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234
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235 public static class ShiftOp extends HSAILLIRInstruction {
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236 @Opcode private final HSAILArithmetic opcode;
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237 @Def({REG, HINT}) protected Value result;
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238 @Use({REG, STACK, CONST}) protected Value x;
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239 @Alive({REG, CONST}) protected Value y;
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240
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241 public ShiftOp(HSAILArithmetic opcode, Value result, Value x, Value y) {
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242 this.opcode = opcode;
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243 this.result = result;
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244 this.x = x;
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245 this.y = y;
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246 }
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247
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248 @Override
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249 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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250 emit(crb, masm, opcode, result, x, y, null);
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251 }
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252
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253 @Override
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254 public void verify() {
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255 super.verify();
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256 verifyKind(opcode, result, x, x);
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257 assert y.getKind().getStackKind() == Kind.Int;
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258 }
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259 }
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260
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261 public static class DivOp extends HSAILLIRInstruction {
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262 @Opcode private final HSAILArithmetic opcode;
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263 @Def protected Value result;
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264 @Use protected Value x;
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265 @Alive protected Value y;
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266 @State protected LIRFrameState state;
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267
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268 public DivOp(HSAILArithmetic opcode, Value result, Value x, Value y, LIRFrameState state) {
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269 this.opcode = opcode;
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270 this.result = result;
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271 this.x = x;
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272 this.y = y;
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273 this.state = state;
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274 }
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275
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276 @Override
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277 public void emitCode(CompilationResultBuilder crb, HSAILAssembler masm) {
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278 emit(crb, masm, opcode, result, y, state);
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279 }
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280
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281 @Override
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282 protected void verify() {
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283 super.verify();
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284 verifyKind(opcode, result, x, y);
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285 }
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286 }
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287
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288 @SuppressWarnings("unused")
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289 protected static void emit(CompilationResultBuilder crb, HSAILAssembler masm, HSAILArithmetic opcode, Value result) {
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290 switch (opcode) {
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291 default:
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292 throw GraalInternalError.shouldNotReachHere();
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293 }
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parents:
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294 }
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295
13308
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296 /**
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297 * Emits the HSAIL code for an arithmetic operation taking one input parameter.
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298 *
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299 * @param crb the CompilationResultBuilder
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300 * @param masm the HSAIL assembler
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301 * @param opcode the opcode of the arithmetic operation
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302 * @param dst the destination
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303 * @param src the source parameter
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304 * @param info structure that stores the LIRFrameState. Used for exception handling.
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305 */
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306
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307 public static void emit(CompilationResultBuilder crb, HSAILAssembler masm, HSAILArithmetic opcode, Value dst, Value src, LIRFrameState info) {
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308 int exceptionOffset = -1;
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parents:
diff changeset
309 if (isRegister(src)) {
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diff changeset
310 switch (opcode) {
13308
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diff changeset
311 case ABS:
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312 masm.emit("abs", dst, src);
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diff changeset
313 break;
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diff changeset
314 case CEIL:
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315 masm.emit("ceil", dst, src);
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316 break;
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diff changeset
317 case FLOOR:
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318 masm.emit("floor", dst, src);
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319 break;
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diff changeset
320 case RINT:
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321 masm.emit("rint", dst, src);
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diff changeset
322 break;
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323 case SQRT:
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324 masm.emit("sqrt", dst, src);
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325 break;
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326 case UNDEF:
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327 masm.undefined("undefined node");
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328 break;
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329 case CALL:
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330 masm.undefined("undefined node CALL");
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331 break;
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diff changeset
332 case INOT:
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333 case LNOT:
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diff changeset
334 masm.emitForceBitwise("not", dst, src);
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parents: 12582
diff changeset
335 break;
c73b857b1be9 Adds support to the HSAIL backend to generate code for bitwise right shift (>>), bitwise NOT (~), and arithmetic negation
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diff changeset
336 case INEG:
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337 case LNEG:
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338 case FNEG:
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339 case DNEG:
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diff changeset
340 masm.emit("neg", dst, src);
12582
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twisti
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341 break;
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342 default:
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parents:
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343 throw GraalInternalError.shouldNotReachHere();
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344 }
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345 } else {
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346 throw GraalInternalError.shouldNotReachHere();
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347 }
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diff changeset
348 if (info != null) {
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349 assert exceptionOffset != -1;
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350 crb.recordImplicitException(exceptionOffset, info);
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351 }
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parents:
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352 }
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parents:
diff changeset
353
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diff changeset
354 public static void emit(CompilationResultBuilder crb, HSAILAssembler masm, HSAILArithmetic opcode, Value dst, Value src1, Value src2, LIRFrameState info) {
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355 /**
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356 * First check if one of src1 or src2 is an AddressValue. If it is, convert the address to a
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357 * register using an lda instruction. We can just reuse the eventual dst register for this.
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diff changeset
358 */
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diff changeset
359 if (src1 instanceof HSAILAddressValue) {
395d34c10e26 HSAIL backend changes
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diff changeset
360 assert (!(src2 instanceof HSAILAddressValue));
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diff changeset
361 masm.emitLda(dst, ((HSAILAddressValue) src1).toAddress());
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diff changeset
362 emit(crb, masm, opcode, dst, dst, src2, info);
10769
395d34c10e26 HSAIL backend changes
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diff changeset
363 return;
395d34c10e26 HSAIL backend changes
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diff changeset
364 } else if (src2 instanceof HSAILAddressValue) {
395d34c10e26 HSAIL backend changes
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diff changeset
365 assert (!(src1 instanceof HSAILAddressValue));
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diff changeset
366 masm.emitLda(dst, ((HSAILAddressValue) src2).toAddress());
13227
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diff changeset
367 emit(crb, masm, opcode, dst, src1, dst, info);
10769
395d34c10e26 HSAIL backend changes
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diff changeset
368 return;
395d34c10e26 HSAIL backend changes
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diff changeset
369 }
10662
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parents:
diff changeset
370 int exceptionOffset = -1;
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
371 switch (opcode) {
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
372 case IADD:
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
373 case LADD:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
374 case DADD:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
375 case FADD:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
376 case OADD:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
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diff changeset
377 masm.emit("add", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
378 break;
10662
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parents:
diff changeset
379 case ISUB:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
380 case LSUB:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
381 case DSUB:
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parents:
diff changeset
382 case FSUB:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
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diff changeset
383 masm.emit("sub", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
384 break;
10662
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
385 case IMUL:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
386 case LMUL:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
387 case FMUL:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
388 case DMUL:
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parents:
diff changeset
389 case LUMUL:
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parents: 11355
diff changeset
390 masm.emit("mul", dst, src1, src2);
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twisti
parents: 11355
diff changeset
391 break;
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
392 case IDIV:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
393 case LDIV:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
394 case FDIV:
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Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
395 case DDIV:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
396 masm.emit("div", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
397 break;
10662
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
398 case IMAX:
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
399 case LMAX:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
400 masm.emit("max", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
401 break;
10662
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
402 case IMIN:
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
403 case LMIN:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
404 masm.emit("min", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
405 break;
10662
4ef92b67aeae added HSAIL backend and tests
Doug Simon <doug.simon@oracle.com>
parents:
diff changeset
406 case ISHL:
10769
395d34c10e26 HSAIL backend changes
Doug Simon <doug.simon@oracle.com>
parents: 10662
diff changeset
407 case LSHL:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
408 masm.emit("shl", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
409 break;
10769
395d34c10e26 HSAIL backend changes
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parents: 10662
diff changeset
410 case ISHR:
395d34c10e26 HSAIL backend changes
Doug Simon <doug.simon@oracle.com>
parents: 10662
diff changeset
411 case LSHR:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
412 masm.emit("shr", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
413 break;
10769
395d34c10e26 HSAIL backend changes
Doug Simon <doug.simon@oracle.com>
parents: 10662
diff changeset
414 case IUSHR:
395d34c10e26 HSAIL backend changes
Doug Simon <doug.simon@oracle.com>
parents: 10662
diff changeset
415 case LUSHR:
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
416 masm.emitForceUnsigned("shr", dst, src1, src2);
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
417 break;
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
418 case IAND:
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
419 case LAND:
12651
c73b857b1be9 Adds support to the HSAIL backend to generate code for bitwise right shift (>>), bitwise NOT (~), and arithmetic negation
Doug Simon <doug.simon@oracle.com>
parents: 12582
diff changeset
420 masm.emitForceBitwise("and", dst, src1, src2);
12582
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
421 break;
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
422 case IXOR:
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
twisti
parents: 11355
diff changeset
423 case LXOR:
12651
c73b857b1be9 Adds support to the HSAIL backend to generate code for bitwise right shift (>>), bitwise NOT (~), and arithmetic negation
Doug Simon <doug.simon@oracle.com>
parents: 12582
diff changeset
424 masm.emitForceBitwise("xor", dst, src1, src2);
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425 break;
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426 case IOR:
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427 case LOR:
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c73b857b1be9 Adds support to the HSAIL backend to generate code for bitwise right shift (>>), bitwise NOT (~), and arithmetic negation
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428 masm.emitForceBitwise("or", dst, src1, src2);
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429 break;
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430 case IREM:
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b96536453a74 HSAIL: added support for LREM
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431 case LREM:
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432 masm.emit("rem", dst, src1, src2);
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433 break;
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434 default:
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435 throw GraalInternalError.shouldNotReachHere();
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436 }
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437 if (info != null) {
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438 assert exceptionOffset != -1;
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1a66453f73db renamed TargetMethodAssembler to CompilationResultBuilder
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439 crb.recordImplicitException(exceptionOffset, info);
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440 }
4ef92b67aeae added HSAIL backend and tests
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441 }
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442
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443 private static void verifyKind(HSAILArithmetic opcode, Value result, Value x, Value y) {
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444 assert (opcode.name().startsWith("I") && result.getKind() == Kind.Int && x.getKind().getStackKind() == Kind.Int && y.getKind().getStackKind() == Kind.Int) ||
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445 (opcode.name().startsWith("L") && result.getKind() == Kind.Long && x.getKind() == Kind.Long && y.getKind() == Kind.Long) ||
a5a4a0bcd863 Adds support to the HSAIL backend for three of the bitwise logical operators, bitwise AND, bitwise OR and bitwise XOR.
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446 (opcode.name().startsWith("LU") && result.getKind() == Kind.Long && x.getKind() == Kind.Long && y.getKind() == Kind.Int) ||
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447 (opcode.name().startsWith("F") && result.getKind() == Kind.Float && x.getKind() == Kind.Float && y.getKind() == Kind.Float) ||
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448 (opcode.name().startsWith("D") && result.getKind() == Kind.Double && x.getKind() == Kind.Double && y.getKind() == Kind.Double) ||
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449 (opcode.name().startsWith("O") && result.getKind() == Kind.Object && x.getKind() == Kind.Object && (y.getKind() == Kind.Int || y.getKind() == Kind.Long));
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450 }
4ef92b67aeae added HSAIL backend and tests
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451 }