Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 989:148e5441d916
6863023: need non-perm oops in code cache for JSR 292
Summary: Make a special root-list for those few nmethods which might contain non-perm oops.
Reviewed-by: twisti, kvn, never, jmasa, ysr
author | jrose |
---|---|
date | Tue, 15 Sep 2009 21:53:47 -0700 |
parents | c96bf21b756f |
children | 323bd24c6520 |
rev | line source |
---|---|
0 | 1 /* |
579 | 2 * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 # include "incls/_precompiled.incl" | |
26 # include "incls/_c1_LIRAssembler_x86.cpp.incl" | |
27 | |
28 | |
29 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
30 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
31 // fast versions of NegF/NegD and AbsF/AbsD. | |
32 | |
33 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
36 // of 128-bits operands for SSE instructions. | |
37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); | |
38 // Store the value to a 128-bits operand. | |
39 operand[0] = lo; | |
40 operand[1] = hi; | |
41 return operand; | |
42 } | |
43 | |
44 // Buffer for 128-bits masks used by SSE instructions. | |
45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
46 | |
47 // Static initialization during VM startup. | |
48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
52 | |
53 | |
54 | |
55 NEEDS_CLEANUP // remove this definitions ? | |
56 const Register IC_Klass = rax; // where the IC klass is cached | |
57 const Register SYNC_header = rax; // synchronization header | |
58 const Register SHIFT_count = rcx; // where count for shift operations must be | |
59 | |
60 #define __ _masm-> | |
61 | |
62 | |
63 static void select_different_registers(Register preserve, | |
64 Register extra, | |
65 Register &tmp1, | |
66 Register &tmp2) { | |
67 if (tmp1 == preserve) { | |
68 assert_different_registers(tmp1, tmp2, extra); | |
69 tmp1 = extra; | |
70 } else if (tmp2 == preserve) { | |
71 assert_different_registers(tmp1, tmp2, extra); | |
72 tmp2 = extra; | |
73 } | |
74 assert_different_registers(preserve, tmp1, tmp2); | |
75 } | |
76 | |
77 | |
78 | |
79 static void select_different_registers(Register preserve, | |
80 Register extra, | |
81 Register &tmp1, | |
82 Register &tmp2, | |
83 Register &tmp3) { | |
84 if (tmp1 == preserve) { | |
85 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
86 tmp1 = extra; | |
87 } else if (tmp2 == preserve) { | |
88 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
89 tmp2 = extra; | |
90 } else if (tmp3 == preserve) { | |
91 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
92 tmp3 = extra; | |
93 } | |
94 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
95 } | |
96 | |
97 | |
98 | |
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
100 if (opr->is_constant()) { | |
101 LIR_Const* constant = opr->as_constant_ptr(); | |
102 switch (constant->type()) { | |
103 case T_INT: { | |
104 return true; | |
105 } | |
106 | |
107 default: | |
108 return false; | |
109 } | |
110 } | |
111 return false; | |
112 } | |
113 | |
114 | |
115 LIR_Opr LIR_Assembler::receiverOpr() { | |
304 | 116 return FrameMap::receiver_opr; |
0 | 117 } |
118 | |
119 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
120 return receiverOpr(); | |
121 } | |
122 | |
123 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
304 | 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
0 | 125 } |
126 | |
127 //--------------fpu register translations----------------------- | |
128 | |
129 | |
130 address LIR_Assembler::float_constant(float f) { | |
131 address const_addr = __ float_constant(f); | |
132 if (const_addr == NULL) { | |
133 bailout("const section overflow"); | |
134 return __ code()->consts()->start(); | |
135 } else { | |
136 return const_addr; | |
137 } | |
138 } | |
139 | |
140 | |
141 address LIR_Assembler::double_constant(double d) { | |
142 address const_addr = __ double_constant(d); | |
143 if (const_addr == NULL) { | |
144 bailout("const section overflow"); | |
145 return __ code()->consts()->start(); | |
146 } else { | |
147 return const_addr; | |
148 } | |
149 } | |
150 | |
151 | |
152 void LIR_Assembler::set_24bit_FPU() { | |
153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
154 } | |
155 | |
156 void LIR_Assembler::reset_FPU() { | |
157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
158 } | |
159 | |
160 void LIR_Assembler::fpop() { | |
161 __ fpop(); | |
162 } | |
163 | |
164 void LIR_Assembler::fxch(int i) { | |
165 __ fxch(i); | |
166 } | |
167 | |
168 void LIR_Assembler::fld(int i) { | |
169 __ fld_s(i); | |
170 } | |
171 | |
172 void LIR_Assembler::ffree(int i) { | |
173 __ ffree(i); | |
174 } | |
175 | |
176 void LIR_Assembler::breakpoint() { | |
177 __ int3(); | |
178 } | |
179 | |
180 void LIR_Assembler::push(LIR_Opr opr) { | |
181 if (opr->is_single_cpu()) { | |
182 __ push_reg(opr->as_register()); | |
183 } else if (opr->is_double_cpu()) { | |
304 | 184 NOT_LP64(__ push_reg(opr->as_register_hi())); |
0 | 185 __ push_reg(opr->as_register_lo()); |
186 } else if (opr->is_stack()) { | |
187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
188 } else if (opr->is_constant()) { | |
189 LIR_Const* const_opr = opr->as_constant_ptr(); | |
190 if (const_opr->type() == T_OBJECT) { | |
191 __ push_oop(const_opr->as_jobject()); | |
192 } else if (const_opr->type() == T_INT) { | |
193 __ push_jint(const_opr->as_jint()); | |
194 } else { | |
195 ShouldNotReachHere(); | |
196 } | |
197 | |
198 } else { | |
199 ShouldNotReachHere(); | |
200 } | |
201 } | |
202 | |
203 void LIR_Assembler::pop(LIR_Opr opr) { | |
204 if (opr->is_single_cpu()) { | |
304 | 205 __ pop_reg(opr->as_register()); |
0 | 206 } else { |
207 ShouldNotReachHere(); | |
208 } | |
209 } | |
210 | |
304 | 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
212 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
213 } | |
214 | |
0 | 215 //------------------------------------------- |
304 | 216 |
0 | 217 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
304 | 218 return as_Address(addr, rscratch1); |
219 } | |
220 | |
221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
0 | 222 if (addr->base()->is_illegal()) { |
223 assert(addr->index()->is_illegal(), "must be illegal too"); | |
304 | 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
225 if (! __ reachable(laddr)) { | |
226 __ movptr(tmp, laddr.addr()); | |
227 Address res(tmp, 0); | |
228 return res; | |
229 } else { | |
230 return __ as_Address(laddr); | |
231 } | |
0 | 232 } |
233 | |
304 | 234 Register base = addr->base()->as_pointer_register(); |
0 | 235 |
236 if (addr->index()->is_illegal()) { | |
237 return Address( base, addr->disp()); | |
304 | 238 } else if (addr->index()->is_cpu_register()) { |
239 Register index = addr->index()->as_pointer_register(); | |
0 | 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
241 } else if (addr->index()->is_constant()) { | |
304 | 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
243 assert(Assembler::is_simm32(addr_offset), "must be"); | |
0 | 244 |
245 return Address(base, addr_offset); | |
246 } else { | |
247 Unimplemented(); | |
248 return Address(); | |
249 } | |
250 } | |
251 | |
252 | |
253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
254 Address base = as_Address(addr); | |
255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
256 } | |
257 | |
258 | |
259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
260 return as_Address(addr); | |
261 } | |
262 | |
263 | |
264 void LIR_Assembler::osr_entry() { | |
265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
267 ValueStack* entry_state = osr_entry->state(); | |
268 int number_of_locks = entry_state->locks_size(); | |
269 | |
270 // we jump here if osr happens with the interpreter | |
271 // state set up to continue at the beginning of the | |
272 // loop that triggered osr - in particular, we have | |
273 // the following registers setup: | |
274 // | |
275 // rcx: osr buffer | |
276 // | |
277 | |
278 // build frame | |
279 ciMethod* m = compilation()->method(); | |
280 __ build_frame(initial_frame_size_in_bytes()); | |
281 | |
282 // OSR buffer is | |
283 // | |
284 // locals[nlocals-1..0] | |
285 // monitors[0..number_of_locks] | |
286 // | |
287 // locals is a direct copy of the interpreter frame so in the osr buffer | |
288 // so first slot in the local array is the last local from the interpreter | |
289 // and last slot is local[0] (receiver) from the interpreter | |
290 // | |
291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
293 // in the interpreter frame (the method lock if a sync method) | |
294 | |
295 // Initialize monitors in the compiled activation. | |
296 // rcx: pointer to osr buffer | |
297 // | |
298 // All other registers are dead at this point and the locals will be | |
299 // copied into place by code emitted in the IR. | |
300 | |
304 | 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
0 | 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
303 int monitor_offset = BytesPerWord * method()->max_locals() + | |
304 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); | |
305 for (int i = 0; i < number_of_locks; i++) { | |
306 int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); | |
307 #ifdef ASSERT | |
308 // verify the interpreter's monitor has a non-null object | |
309 { | |
310 Label L; | |
304 | 311 __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD); |
0 | 312 __ jcc(Assembler::notZero, L); |
313 __ stop("locked object is NULL"); | |
314 __ bind(L); | |
315 } | |
316 #endif | |
304 | 317 __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes())); |
318 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); | |
319 __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes())); | |
320 __ movptr(frame_map()->address_for_monitor_object(i), rbx); | |
0 | 321 } |
322 } | |
323 } | |
324 | |
325 | |
326 // inline cache check; done before the frame is built. | |
327 int LIR_Assembler::check_icache() { | |
328 Register receiver = FrameMap::receiver_opr->as_register(); | |
329 Register ic_klass = IC_Klass; | |
304 | 330 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
0 | 331 |
332 if (!VerifyOops) { | |
333 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment | |
304 | 334 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
0 | 335 __ nop(); |
336 } | |
337 } | |
338 int offset = __ offset(); | |
339 __ inline_cache_check(receiver, IC_Klass); | |
340 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); | |
341 if (VerifyOops) { | |
342 // force alignment after the cache check. | |
343 // It's been verified to be aligned if !VerifyOops | |
344 __ align(CodeEntryAlignment); | |
345 } | |
346 return offset; | |
347 } | |
348 | |
349 | |
350 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
351 jobject o = NULL; | |
352 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
353 __ movoop(reg, o); | |
354 patching_epilog(patch, lir_patch_normal, reg, info); | |
355 } | |
356 | |
357 | |
358 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { | |
359 if (exception->is_valid()) { | |
360 // preserve exception | |
361 // note: the monitor_exit runtime call is a leaf routine | |
362 // and cannot block => no GC can happen | |
363 // The slow case (MonitorAccessStub) uses the first two stack slots | |
364 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] | |
304 | 365 __ movptr (Address(rsp, 2*wordSize), exception); |
0 | 366 } |
367 | |
368 Register obj_reg = obj_opr->as_register(); | |
369 Register lock_reg = lock_opr->as_register(); | |
370 | |
371 // setup registers (lock_reg must be rax, for lock_object) | |
372 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); | |
373 Register hdr = lock_reg; | |
374 assert(new_hdr == SYNC_header, "wrong register"); | |
375 lock_reg = new_hdr; | |
376 // compute pointer to BasicLock | |
377 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
304 | 378 __ lea(lock_reg, lock_addr); |
0 | 379 // unlock object |
380 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); | |
381 // _slow_case_stubs->append(slow_case); | |
382 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
383 _slow_case_stubs->append(slow_case); | |
384 if (UseFastLocking) { | |
385 // try inlined fast unlocking first, revert to slow locking if it fails | |
386 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
387 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
388 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
389 } else { | |
390 // always do slow unlocking | |
391 // note: the slow unlocking code could be inlined here, however if we use | |
392 // slow unlocking, speed doesn't matter anyway and this solution is | |
393 // simpler and requires less duplicated code - additionally, the | |
394 // slow unlocking code is the same in either case which simplifies | |
395 // debugging | |
396 __ jmp(*slow_case->entry()); | |
397 } | |
398 // done | |
399 __ bind(*slow_case->continuation()); | |
400 | |
401 if (exception->is_valid()) { | |
402 // restore exception | |
304 | 403 __ movptr (exception, Address(rsp, 2 * wordSize)); |
0 | 404 } |
405 } | |
406 | |
407 // This specifies the rsp decrement needed to build the frame | |
408 int LIR_Assembler::initial_frame_size_in_bytes() { | |
409 // if rounding, must let FrameMap know! | |
304 | 410 |
411 // The frame_map records size in slots (32bit word) | |
412 | |
413 // subtract two words to account for return address and link | |
414 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
0 | 415 } |
416 | |
417 | |
418 void LIR_Assembler::emit_exception_handler() { | |
419 // if the last instruction is a call (typically to do a throw which | |
420 // is coming at the end after block reordering) the return address | |
421 // must still point into the code area in order to avoid assertion | |
422 // failures when searching for the corresponding bci => add a nop | |
423 // (was bug 5/14/1999 - gri) | |
424 | |
425 __ nop(); | |
426 | |
427 // generate code for exception handler | |
428 address handler_base = __ start_a_stub(exception_handler_size); | |
429 if (handler_base == NULL) { | |
430 // not enough space left for the handler | |
431 bailout("exception handler overflow"); | |
432 return; | |
433 } | |
434 #ifdef ASSERT | |
435 int offset = code_offset(); | |
436 #endif // ASSERT | |
437 | |
438 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); | |
439 | |
440 // if the method does not have an exception handler, then there is | |
441 // no reason to search for one | |
780
c96bf21b756f
6788527: Server vm intermittently fails with assertion "live value must not be garbage" with fastdebug bits
kvn
parents:
647
diff
changeset
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442 if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_exceptions()) { |
0 | 443 // the exception oop and pc are in rax, and rdx |
444 // no other registers need to be preserved, so invalidate them | |
445 __ invalidate_registers(false, true, true, false, true, true); | |
446 | |
447 // check that there is really an exception | |
448 __ verify_not_null_oop(rax); | |
449 | |
450 // search an exception handler (rax: exception oop, rdx: throwing pc) | |
451 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); | |
452 | |
453 // if the call returns here, then the exception handler for particular | |
454 // exception doesn't exist -> unwind activation and forward exception to caller | |
455 } | |
456 | |
457 // the exception oop is in rax, | |
458 // no other registers need to be preserved, so invalidate them | |
459 __ invalidate_registers(false, true, true, true, true, true); | |
460 | |
461 // check that there is really an exception | |
462 __ verify_not_null_oop(rax); | |
463 | |
464 // unlock the receiver/klass if necessary | |
465 // rax,: exception | |
466 ciMethod* method = compilation()->method(); | |
467 if (method->is_synchronized() && GenerateSynchronizationCode) { | |
468 monitorexit(FrameMap::rbx_oop_opr, FrameMap::rcx_opr, SYNC_header, 0, rax); | |
469 } | |
470 | |
471 // unwind activation and forward exception to caller | |
472 // rax,: exception | |
473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); | |
474 | |
475 assert(code_offset() - offset <= exception_handler_size, "overflow"); | |
476 | |
477 __ end_a_stub(); | |
478 } | |
479 | |
480 void LIR_Assembler::emit_deopt_handler() { | |
481 // if the last instruction is a call (typically to do a throw which | |
482 // is coming at the end after block reordering) the return address | |
483 // must still point into the code area in order to avoid assertion | |
484 // failures when searching for the corresponding bci => add a nop | |
485 // (was bug 5/14/1999 - gri) | |
486 | |
487 __ nop(); | |
488 | |
489 // generate code for exception handler | |
490 address handler_base = __ start_a_stub(deopt_handler_size); | |
491 if (handler_base == NULL) { | |
492 // not enough space left for the handler | |
493 bailout("deopt handler overflow"); | |
494 return; | |
495 } | |
496 #ifdef ASSERT | |
497 int offset = code_offset(); | |
498 #endif // ASSERT | |
499 | |
500 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); | |
501 | |
502 InternalAddress here(__ pc()); | |
503 __ pushptr(here.addr()); | |
504 | |
505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
506 | |
507 assert(code_offset() - offset <= deopt_handler_size, "overflow"); | |
508 | |
509 __ end_a_stub(); | |
510 | |
511 } | |
512 | |
513 | |
514 // This is the fast version of java.lang.String.compare; it has not | |
515 // OSR-entry and therefore, we generate a slow version for OSR's | |
516 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
304 | 517 __ movptr (rbx, rcx); // receiver is in rcx |
518 __ movptr (rax, arg1->as_register()); | |
0 | 519 |
520 // Get addresses of first characters from both Strings | |
304 | 521 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
522 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
523 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
0 | 524 |
525 | |
526 // rbx, may be NULL | |
527 add_debug_info_for_null_check_here(info); | |
304 | 528 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
529 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
530 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
0 | 531 |
532 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
533 if (VM_Version::supports_cmov()) { | |
304 | 534 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
535 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); | |
536 __ mov (rcx, rbx); | |
537 __ subptr (rbx, rax); // subtract lengths | |
538 __ push (rbx); // result | |
539 __ cmov (Assembler::lessEqual, rax, rcx); | |
0 | 540 } else { |
541 Label L; | |
304 | 542 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
543 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); | |
544 __ mov (rax, rbx); | |
545 __ subptr (rbx, rcx); | |
546 __ push (rbx); | |
547 __ jcc (Assembler::lessEqual, L); | |
548 __ mov (rax, rcx); | |
0 | 549 __ bind (L); |
550 } | |
551 // is minimum length 0? | |
552 Label noLoop, haveResult; | |
304 | 553 __ testptr (rax, rax); |
0 | 554 __ jcc (Assembler::zero, noLoop); |
555 | |
556 // compare first characters | |
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557 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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558 __ load_unsigned_short(rbx, Address(rsi, 0)); |
0 | 559 __ subl(rcx, rbx); |
560 __ jcc(Assembler::notZero, haveResult); | |
561 // starting loop | |
562 __ decrement(rax); // we already tested index: skip one | |
563 __ jcc(Assembler::zero, noLoop); | |
564 | |
565 // set rsi.edi to the end of the arrays (arrays have same length) | |
566 // negate the index | |
567 | |
304 | 568 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
569 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
570 __ negptr(rax); | |
0 | 571 |
572 // compare the strings in a loop | |
573 | |
574 Label loop; | |
575 __ align(wordSize); | |
576 __ bind(loop); | |
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577 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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578 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
0 | 579 __ subl(rcx, rbx); |
580 __ jcc(Assembler::notZero, haveResult); | |
581 __ increment(rax); | |
582 __ jcc(Assembler::notZero, loop); | |
583 | |
584 // strings are equal up to min length | |
585 | |
586 __ bind(noLoop); | |
304 | 587 __ pop(rax); |
0 | 588 return_op(LIR_OprFact::illegalOpr); |
589 | |
590 __ bind(haveResult); | |
591 // leave instruction is going to discard the TOS value | |
304 | 592 __ mov (rax, rcx); // result of call is in rax, |
0 | 593 } |
594 | |
595 | |
596 void LIR_Assembler::return_op(LIR_Opr result) { | |
597 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
598 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
599 assert(result->fpu() == 0, "result must already be on TOS"); | |
600 } | |
601 | |
602 // Pop the stack before the safepoint code | |
603 __ leave(); | |
604 | |
605 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
606 | |
607 // Note: we do not need to round double result; float result has the right precision | |
608 // the poll sets the condition code, but no data registers | |
609 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
610 relocInfo::poll_return_type); | |
304 | 611 |
612 // NOTE: the requires that the polling page be reachable else the reloc | |
613 // goes to the movq that loads the address and not the faulting instruction | |
614 // which breaks the signal handler code | |
615 | |
0 | 616 __ test32(rax, polling_page); |
617 | |
618 __ ret(0); | |
619 } | |
620 | |
621 | |
622 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
623 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
624 relocInfo::poll_type); | |
625 | |
626 if (info != NULL) { | |
627 add_debug_info_for_branch(info); | |
628 } else { | |
629 ShouldNotReachHere(); | |
630 } | |
631 | |
632 int offset = __ offset(); | |
304 | 633 |
634 // NOTE: the requires that the polling page be reachable else the reloc | |
635 // goes to the movq that loads the address and not the faulting instruction | |
636 // which breaks the signal handler code | |
637 | |
0 | 638 __ test32(rax, polling_page); |
639 return offset; | |
640 } | |
641 | |
642 | |
643 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
304 | 644 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
0 | 645 } |
646 | |
647 void LIR_Assembler::swap_reg(Register a, Register b) { | |
304 | 648 __ xchgptr(a, b); |
0 | 649 } |
650 | |
651 | |
652 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
653 assert(src->is_constant(), "should not call otherwise"); | |
654 assert(dest->is_register(), "should not call otherwise"); | |
655 LIR_Const* c = src->as_constant_ptr(); | |
656 | |
657 switch (c->type()) { | |
658 case T_INT: { | |
659 assert(patch_code == lir_patch_none, "no patching handled here"); | |
660 __ movl(dest->as_register(), c->as_jint()); | |
661 break; | |
662 } | |
663 | |
664 case T_LONG: { | |
665 assert(patch_code == lir_patch_none, "no patching handled here"); | |
304 | 666 #ifdef _LP64 |
667 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
668 #else | |
669 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
670 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
671 #endif // _LP64 | |
0 | 672 break; |
673 } | |
674 | |
675 case T_OBJECT: { | |
676 if (patch_code != lir_patch_none) { | |
677 jobject2reg_with_patching(dest->as_register(), info); | |
678 } else { | |
679 __ movoop(dest->as_register(), c->as_jobject()); | |
680 } | |
681 break; | |
682 } | |
683 | |
684 case T_FLOAT: { | |
685 if (dest->is_single_xmm()) { | |
686 if (c->is_zero_float()) { | |
687 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
688 } else { | |
689 __ movflt(dest->as_xmm_float_reg(), | |
690 InternalAddress(float_constant(c->as_jfloat()))); | |
691 } | |
692 } else { | |
693 assert(dest->is_single_fpu(), "must be"); | |
694 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
695 if (c->is_zero_float()) { | |
696 __ fldz(); | |
697 } else if (c->is_one_float()) { | |
698 __ fld1(); | |
699 } else { | |
700 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
701 } | |
702 } | |
703 break; | |
704 } | |
705 | |
706 case T_DOUBLE: { | |
707 if (dest->is_double_xmm()) { | |
708 if (c->is_zero_double()) { | |
709 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
710 } else { | |
711 __ movdbl(dest->as_xmm_double_reg(), | |
712 InternalAddress(double_constant(c->as_jdouble()))); | |
713 } | |
714 } else { | |
715 assert(dest->is_double_fpu(), "must be"); | |
716 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
717 if (c->is_zero_double()) { | |
718 __ fldz(); | |
719 } else if (c->is_one_double()) { | |
720 __ fld1(); | |
721 } else { | |
722 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
723 } | |
724 } | |
725 break; | |
726 } | |
727 | |
728 default: | |
729 ShouldNotReachHere(); | |
730 } | |
731 } | |
732 | |
733 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
734 assert(src->is_constant(), "should not call otherwise"); | |
735 assert(dest->is_stack(), "should not call otherwise"); | |
736 LIR_Const* c = src->as_constant_ptr(); | |
737 | |
738 switch (c->type()) { | |
739 case T_INT: // fall through | |
740 case T_FLOAT: | |
741 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); | |
742 break; | |
743 | |
744 case T_OBJECT: | |
745 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
746 break; | |
747 | |
748 case T_LONG: // fall through | |
749 case T_DOUBLE: | |
304 | 750 #ifdef _LP64 |
751 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
752 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
753 #else | |
754 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
755 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
756 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
757 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
758 #endif // _LP64 | |
0 | 759 break; |
760 | |
761 default: | |
762 ShouldNotReachHere(); | |
763 } | |
764 } | |
765 | |
766 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { | |
767 assert(src->is_constant(), "should not call otherwise"); | |
768 assert(dest->is_address(), "should not call otherwise"); | |
769 LIR_Const* c = src->as_constant_ptr(); | |
770 LIR_Address* addr = dest->as_address_ptr(); | |
771 | |
304 | 772 int null_check_here = code_offset(); |
0 | 773 switch (type) { |
774 case T_INT: // fall through | |
775 case T_FLOAT: | |
776 __ movl(as_Address(addr), c->as_jint_bits()); | |
777 break; | |
778 | |
779 case T_OBJECT: // fall through | |
780 case T_ARRAY: | |
781 if (c->as_jobject() == NULL) { | |
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782 __ movptr(as_Address(addr), NULL_WORD); |
0 | 783 } else { |
304 | 784 if (is_literal_address(addr)) { |
785 ShouldNotReachHere(); | |
786 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
787 } else { | |
788 __ movoop(as_Address(addr), c->as_jobject()); | |
789 } | |
0 | 790 } |
791 break; | |
792 | |
793 case T_LONG: // fall through | |
794 case T_DOUBLE: | |
304 | 795 #ifdef _LP64 |
796 if (is_literal_address(addr)) { | |
797 ShouldNotReachHere(); | |
798 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
799 } else { | |
800 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
801 null_check_here = code_offset(); | |
802 __ movptr(as_Address_lo(addr), r10); | |
803 } | |
804 #else | |
805 // Always reachable in 32bit so this doesn't produce useless move literal | |
806 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
807 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
808 #endif // _LP64 | |
0 | 809 break; |
810 | |
811 case T_BOOLEAN: // fall through | |
812 case T_BYTE: | |
813 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
814 break; | |
815 | |
816 case T_CHAR: // fall through | |
817 case T_SHORT: | |
818 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
819 break; | |
820 | |
821 default: | |
822 ShouldNotReachHere(); | |
823 }; | |
304 | 824 |
825 if (info != NULL) { | |
826 add_debug_info_for_null_check(null_check_here, info); | |
827 } | |
0 | 828 } |
829 | |
830 | |
831 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
832 assert(src->is_register(), "should not call otherwise"); | |
833 assert(dest->is_register(), "should not call otherwise"); | |
834 | |
835 // move between cpu-registers | |
836 if (dest->is_single_cpu()) { | |
304 | 837 #ifdef _LP64 |
838 if (src->type() == T_LONG) { | |
839 // Can do LONG -> OBJECT | |
840 move_regs(src->as_register_lo(), dest->as_register()); | |
841 return; | |
842 } | |
843 #endif | |
0 | 844 assert(src->is_single_cpu(), "must match"); |
845 if (src->type() == T_OBJECT) { | |
846 __ verify_oop(src->as_register()); | |
847 } | |
848 move_regs(src->as_register(), dest->as_register()); | |
849 | |
850 } else if (dest->is_double_cpu()) { | |
304 | 851 #ifdef _LP64 |
852 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
853 // Surprising to me but we can see move of a long to t_object | |
854 __ verify_oop(src->as_register()); | |
855 move_regs(src->as_register(), dest->as_register_lo()); | |
856 return; | |
857 } | |
858 #endif | |
0 | 859 assert(src->is_double_cpu(), "must match"); |
860 Register f_lo = src->as_register_lo(); | |
861 Register f_hi = src->as_register_hi(); | |
862 Register t_lo = dest->as_register_lo(); | |
863 Register t_hi = dest->as_register_hi(); | |
304 | 864 #ifdef _LP64 |
865 assert(f_hi == f_lo, "must be same"); | |
866 assert(t_hi == t_lo, "must be same"); | |
867 move_regs(f_lo, t_lo); | |
868 #else | |
0 | 869 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
870 | |
304 | 871 |
0 | 872 if (f_lo == t_hi && f_hi == t_lo) { |
873 swap_reg(f_lo, f_hi); | |
874 } else if (f_hi == t_lo) { | |
875 assert(f_lo != t_hi, "overwriting register"); | |
876 move_regs(f_hi, t_hi); | |
877 move_regs(f_lo, t_lo); | |
878 } else { | |
879 assert(f_hi != t_lo, "overwriting register"); | |
880 move_regs(f_lo, t_lo); | |
881 move_regs(f_hi, t_hi); | |
882 } | |
304 | 883 #endif // LP64 |
0 | 884 |
885 // special moves from fpu-register to xmm-register | |
886 // necessary for method results | |
887 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
888 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
889 __ fld_s(Address(rsp, 0)); | |
890 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
891 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
892 __ fld_d(Address(rsp, 0)); | |
893 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
894 __ fstp_s(Address(rsp, 0)); | |
895 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
896 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
897 __ fstp_d(Address(rsp, 0)); | |
898 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
899 | |
900 // move between xmm-registers | |
901 } else if (dest->is_single_xmm()) { | |
902 assert(src->is_single_xmm(), "must match"); | |
903 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
904 } else if (dest->is_double_xmm()) { | |
905 assert(src->is_double_xmm(), "must match"); | |
906 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
907 | |
908 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
909 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
910 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
911 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
912 } else { | |
913 ShouldNotReachHere(); | |
914 } | |
915 } | |
916 | |
917 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
918 assert(src->is_register(), "should not call otherwise"); | |
919 assert(dest->is_stack(), "should not call otherwise"); | |
920 | |
921 if (src->is_single_cpu()) { | |
922 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
923 if (type == T_OBJECT || type == T_ARRAY) { | |
924 __ verify_oop(src->as_register()); | |
304 | 925 __ movptr (dst, src->as_register()); |
926 } else { | |
927 __ movl (dst, src->as_register()); | |
0 | 928 } |
929 | |
930 } else if (src->is_double_cpu()) { | |
931 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
932 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 933 __ movptr (dstLO, src->as_register_lo()); |
934 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
0 | 935 |
936 } else if (src->is_single_xmm()) { | |
937 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
938 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
939 | |
940 } else if (src->is_double_xmm()) { | |
941 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
942 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
943 | |
944 } else if (src->is_single_fpu()) { | |
945 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
946 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
947 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
948 else __ fst_s (dst_addr); | |
949 | |
950 } else if (src->is_double_fpu()) { | |
951 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
952 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
953 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
954 else __ fst_d (dst_addr); | |
955 | |
956 } else { | |
957 ShouldNotReachHere(); | |
958 } | |
959 } | |
960 | |
961 | |
962 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { | |
963 LIR_Address* to_addr = dest->as_address_ptr(); | |
964 PatchingStub* patch = NULL; | |
965 | |
966 if (type == T_ARRAY || type == T_OBJECT) { | |
967 __ verify_oop(src->as_register()); | |
968 } | |
969 if (patch_code != lir_patch_none) { | |
970 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 971 Address toa = as_Address(to_addr); |
972 assert(toa.disp() != 0, "must have"); | |
0 | 973 } |
974 if (info != NULL) { | |
975 add_debug_info_for_null_check_here(info); | |
976 } | |
977 | |
978 switch (type) { | |
979 case T_FLOAT: { | |
980 if (src->is_single_xmm()) { | |
981 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
982 } else { | |
983 assert(src->is_single_fpu(), "must be"); | |
984 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
985 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
986 else __ fst_s (as_Address(to_addr)); | |
987 } | |
988 break; | |
989 } | |
990 | |
991 case T_DOUBLE: { | |
992 if (src->is_double_xmm()) { | |
993 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
994 } else { | |
995 assert(src->is_double_fpu(), "must be"); | |
996 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
997 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
998 else __ fst_d (as_Address(to_addr)); | |
999 } | |
1000 break; | |
1001 } | |
1002 | |
1003 case T_ADDRESS: // fall through | |
1004 case T_ARRAY: // fall through | |
1005 case T_OBJECT: // fall through | |
304 | 1006 #ifdef _LP64 |
1007 __ movptr(as_Address(to_addr), src->as_register()); | |
1008 break; | |
1009 #endif // _LP64 | |
0 | 1010 case T_INT: |
1011 __ movl(as_Address(to_addr), src->as_register()); | |
1012 break; | |
1013 | |
1014 case T_LONG: { | |
1015 Register from_lo = src->as_register_lo(); | |
1016 Register from_hi = src->as_register_hi(); | |
304 | 1017 #ifdef _LP64 |
1018 __ movptr(as_Address_lo(to_addr), from_lo); | |
1019 #else | |
0 | 1020 Register base = to_addr->base()->as_register(); |
1021 Register index = noreg; | |
1022 if (to_addr->index()->is_register()) { | |
1023 index = to_addr->index()->as_register(); | |
1024 } | |
1025 if (base == from_lo || index == from_lo) { | |
1026 assert(base != from_hi, "can't be"); | |
1027 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
1028 __ movl(as_Address_hi(to_addr), from_hi); | |
1029 if (patch != NULL) { | |
1030 patching_epilog(patch, lir_patch_high, base, info); | |
1031 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1032 patch_code = lir_patch_low; | |
1033 } | |
1034 __ movl(as_Address_lo(to_addr), from_lo); | |
1035 } else { | |
1036 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
1037 __ movl(as_Address_lo(to_addr), from_lo); | |
1038 if (patch != NULL) { | |
1039 patching_epilog(patch, lir_patch_low, base, info); | |
1040 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1041 patch_code = lir_patch_high; | |
1042 } | |
1043 __ movl(as_Address_hi(to_addr), from_hi); | |
1044 } | |
304 | 1045 #endif // _LP64 |
0 | 1046 break; |
1047 } | |
1048 | |
1049 case T_BYTE: // fall through | |
1050 case T_BOOLEAN: { | |
1051 Register src_reg = src->as_register(); | |
1052 Address dst_addr = as_Address(to_addr); | |
1053 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
1054 __ movb(dst_addr, src_reg); | |
1055 break; | |
1056 } | |
1057 | |
1058 case T_CHAR: // fall through | |
1059 case T_SHORT: | |
1060 __ movw(as_Address(to_addr), src->as_register()); | |
1061 break; | |
1062 | |
1063 default: | |
1064 ShouldNotReachHere(); | |
1065 } | |
1066 | |
1067 if (patch_code != lir_patch_none) { | |
1068 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
1069 } | |
1070 } | |
1071 | |
1072 | |
1073 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1074 assert(src->is_stack(), "should not call otherwise"); | |
1075 assert(dest->is_register(), "should not call otherwise"); | |
1076 | |
1077 if (dest->is_single_cpu()) { | |
1078 if (type == T_ARRAY || type == T_OBJECT) { | |
304 | 1079 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
0 | 1080 __ verify_oop(dest->as_register()); |
304 | 1081 } else { |
1082 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
0 | 1083 } |
1084 | |
1085 } else if (dest->is_double_cpu()) { | |
1086 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
1087 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 1088 __ movptr(dest->as_register_lo(), src_addr_LO); |
1089 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
0 | 1090 |
1091 } else if (dest->is_single_xmm()) { | |
1092 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1093 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
1094 | |
1095 } else if (dest->is_double_xmm()) { | |
1096 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1097 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
1098 | |
1099 } else if (dest->is_single_fpu()) { | |
1100 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1101 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1102 __ fld_s(src_addr); | |
1103 | |
1104 } else if (dest->is_double_fpu()) { | |
1105 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1106 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1107 __ fld_d(src_addr); | |
1108 | |
1109 } else { | |
1110 ShouldNotReachHere(); | |
1111 } | |
1112 } | |
1113 | |
1114 | |
1115 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1116 if (src->is_single_stack()) { | |
304 | 1117 if (type == T_OBJECT || type == T_ARRAY) { |
1118 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
1119 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1120 } else { | |
1121 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); | |
1122 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1123 } | |
0 | 1124 |
1125 } else if (src->is_double_stack()) { | |
304 | 1126 #ifdef _LP64 |
1127 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
1128 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
1129 #else | |
0 | 1130 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
304 | 1131 // push and pop the part at src + wordSize, adding wordSize for the previous push |
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1132 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1133 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
0 | 1134 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
304 | 1135 #endif // _LP64 |
0 | 1136 |
1137 } else { | |
1138 ShouldNotReachHere(); | |
1139 } | |
1140 } | |
1141 | |
1142 | |
1143 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { | |
1144 assert(src->is_address(), "should not call otherwise"); | |
1145 assert(dest->is_register(), "should not call otherwise"); | |
1146 | |
1147 LIR_Address* addr = src->as_address_ptr(); | |
1148 Address from_addr = as_Address(addr); | |
1149 | |
1150 switch (type) { | |
1151 case T_BOOLEAN: // fall through | |
1152 case T_BYTE: // fall through | |
1153 case T_CHAR: // fall through | |
1154 case T_SHORT: | |
1155 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
1156 // on pre P6 processors we may get partial register stalls | |
1157 // so blow away the value of to_rinfo before loading a | |
1158 // partial word into it. Do it here so that it precedes | |
1159 // the potential patch point below. | |
304 | 1160 __ xorptr(dest->as_register(), dest->as_register()); |
0 | 1161 } |
1162 break; | |
1163 } | |
1164 | |
1165 PatchingStub* patch = NULL; | |
1166 if (patch_code != lir_patch_none) { | |
1167 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 1168 assert(from_addr.disp() != 0, "must have"); |
0 | 1169 } |
1170 if (info != NULL) { | |
1171 add_debug_info_for_null_check_here(info); | |
1172 } | |
1173 | |
1174 switch (type) { | |
1175 case T_FLOAT: { | |
1176 if (dest->is_single_xmm()) { | |
1177 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
1178 } else { | |
1179 assert(dest->is_single_fpu(), "must be"); | |
1180 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1181 __ fld_s(from_addr); | |
1182 } | |
1183 break; | |
1184 } | |
1185 | |
1186 case T_DOUBLE: { | |
1187 if (dest->is_double_xmm()) { | |
1188 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
1189 } else { | |
1190 assert(dest->is_double_fpu(), "must be"); | |
1191 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1192 __ fld_d(from_addr); | |
1193 } | |
1194 break; | |
1195 } | |
1196 | |
1197 case T_ADDRESS: // fall through | |
1198 case T_OBJECT: // fall through | |
1199 case T_ARRAY: // fall through | |
304 | 1200 #ifdef _LP64 |
1201 __ movptr(dest->as_register(), from_addr); | |
1202 break; | |
1203 #endif // _L64 | |
0 | 1204 case T_INT: |
304 | 1205 // %%% could this be a movl? this is safer but longer instruction |
1206 __ movl2ptr(dest->as_register(), from_addr); | |
0 | 1207 break; |
1208 | |
1209 case T_LONG: { | |
1210 Register to_lo = dest->as_register_lo(); | |
1211 Register to_hi = dest->as_register_hi(); | |
304 | 1212 #ifdef _LP64 |
1213 __ movptr(to_lo, as_Address_lo(addr)); | |
1214 #else | |
0 | 1215 Register base = addr->base()->as_register(); |
1216 Register index = noreg; | |
1217 if (addr->index()->is_register()) { | |
1218 index = addr->index()->as_register(); | |
1219 } | |
1220 if ((base == to_lo && index == to_hi) || | |
1221 (base == to_hi && index == to_lo)) { | |
1222 // addresses with 2 registers are only formed as a result of | |
1223 // array access so this code will never have to deal with | |
1224 // patches or null checks. | |
1225 assert(info == NULL && patch == NULL, "must be"); | |
304 | 1226 __ lea(to_hi, as_Address(addr)); |
0 | 1227 __ movl(to_lo, Address(to_hi, 0)); |
1228 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
1229 } else if (base == to_lo || index == to_lo) { | |
1230 assert(base != to_hi, "can't be"); | |
1231 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
1232 __ movl(to_hi, as_Address_hi(addr)); | |
1233 if (patch != NULL) { | |
1234 patching_epilog(patch, lir_patch_high, base, info); | |
1235 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1236 patch_code = lir_patch_low; | |
1237 } | |
1238 __ movl(to_lo, as_Address_lo(addr)); | |
1239 } else { | |
1240 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
1241 __ movl(to_lo, as_Address_lo(addr)); | |
1242 if (patch != NULL) { | |
1243 patching_epilog(patch, lir_patch_low, base, info); | |
1244 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1245 patch_code = lir_patch_high; | |
1246 } | |
1247 __ movl(to_hi, as_Address_hi(addr)); | |
1248 } | |
304 | 1249 #endif // _LP64 |
0 | 1250 break; |
1251 } | |
1252 | |
1253 case T_BOOLEAN: // fall through | |
1254 case T_BYTE: { | |
1255 Register dest_reg = dest->as_register(); | |
1256 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1257 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1258 __ movsbl(dest_reg, from_addr); |
0 | 1259 } else { |
1260 __ movb(dest_reg, from_addr); | |
1261 __ shll(dest_reg, 24); | |
1262 __ sarl(dest_reg, 24); | |
1263 } | |
304 | 1264 // These are unsigned so the zero extension on 64bit is just what we need |
0 | 1265 break; |
1266 } | |
1267 | |
1268 case T_CHAR: { | |
1269 Register dest_reg = dest->as_register(); | |
1270 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1271 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1272 __ movzwl(dest_reg, from_addr); |
0 | 1273 } else { |
1274 __ movw(dest_reg, from_addr); | |
1275 } | |
304 | 1276 // This is unsigned so the zero extension on 64bit is just what we need |
1277 // __ movl2ptr(dest_reg, dest_reg); | |
0 | 1278 break; |
1279 } | |
1280 | |
1281 case T_SHORT: { | |
1282 Register dest_reg = dest->as_register(); | |
1283 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1284 __ movswl(dest_reg, from_addr); |
0 | 1285 } else { |
1286 __ movw(dest_reg, from_addr); | |
1287 __ shll(dest_reg, 16); | |
1288 __ sarl(dest_reg, 16); | |
1289 } | |
304 | 1290 // Might not be needed in 64bit but certainly doesn't hurt (except for code size) |
1291 __ movl2ptr(dest_reg, dest_reg); | |
0 | 1292 break; |
1293 } | |
1294 | |
1295 default: | |
1296 ShouldNotReachHere(); | |
1297 } | |
1298 | |
1299 if (patch != NULL) { | |
1300 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
1301 } | |
1302 | |
1303 if (type == T_ARRAY || type == T_OBJECT) { | |
1304 __ verify_oop(dest->as_register()); | |
1305 } | |
1306 } | |
1307 | |
1308 | |
1309 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1310 LIR_Address* addr = src->as_address_ptr(); | |
1311 Address from_addr = as_Address(addr); | |
1312 | |
1313 if (VM_Version::supports_sse()) { | |
1314 switch (ReadPrefetchInstr) { | |
1315 case 0: | |
1316 __ prefetchnta(from_addr); break; | |
1317 case 1: | |
1318 __ prefetcht0(from_addr); break; | |
1319 case 2: | |
1320 __ prefetcht2(from_addr); break; | |
1321 default: | |
1322 ShouldNotReachHere(); break; | |
1323 } | |
1324 } else if (VM_Version::supports_3dnow()) { | |
1325 __ prefetchr(from_addr); | |
1326 } | |
1327 } | |
1328 | |
1329 | |
1330 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1331 LIR_Address* addr = src->as_address_ptr(); | |
1332 Address from_addr = as_Address(addr); | |
1333 | |
1334 if (VM_Version::supports_sse()) { | |
1335 switch (AllocatePrefetchInstr) { | |
1336 case 0: | |
1337 __ prefetchnta(from_addr); break; | |
1338 case 1: | |
1339 __ prefetcht0(from_addr); break; | |
1340 case 2: | |
1341 __ prefetcht2(from_addr); break; | |
1342 case 3: | |
1343 __ prefetchw(from_addr); break; | |
1344 default: | |
1345 ShouldNotReachHere(); break; | |
1346 } | |
1347 } else if (VM_Version::supports_3dnow()) { | |
1348 __ prefetchw(from_addr); | |
1349 } | |
1350 } | |
1351 | |
1352 | |
1353 NEEDS_CLEANUP; // This could be static? | |
1354 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
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1355 int elem_size = type2aelembytes(type); |
0 | 1356 switch (elem_size) { |
1357 case 1: return Address::times_1; | |
1358 case 2: return Address::times_2; | |
1359 case 4: return Address::times_4; | |
1360 case 8: return Address::times_8; | |
1361 } | |
1362 ShouldNotReachHere(); | |
1363 return Address::no_scale; | |
1364 } | |
1365 | |
1366 | |
1367 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
1368 switch (op->code()) { | |
1369 case lir_idiv: | |
1370 case lir_irem: | |
1371 arithmetic_idiv(op->code(), | |
1372 op->in_opr1(), | |
1373 op->in_opr2(), | |
1374 op->in_opr3(), | |
1375 op->result_opr(), | |
1376 op->info()); | |
1377 break; | |
1378 default: ShouldNotReachHere(); break; | |
1379 } | |
1380 } | |
1381 | |
1382 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
1383 #ifdef ASSERT | |
1384 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
1385 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
1386 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
1387 #endif | |
1388 | |
1389 if (op->cond() == lir_cond_always) { | |
1390 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
1391 __ jmp (*(op->label())); | |
1392 } else { | |
1393 Assembler::Condition acond = Assembler::zero; | |
1394 if (op->code() == lir_cond_float_branch) { | |
1395 assert(op->ublock() != NULL, "must have unordered successor"); | |
1396 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
1397 switch(op->cond()) { | |
1398 case lir_cond_equal: acond = Assembler::equal; break; | |
1399 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1400 case lir_cond_less: acond = Assembler::below; break; | |
1401 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
1402 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
1403 case lir_cond_greater: acond = Assembler::above; break; | |
1404 default: ShouldNotReachHere(); | |
1405 } | |
1406 } else { | |
1407 switch (op->cond()) { | |
1408 case lir_cond_equal: acond = Assembler::equal; break; | |
1409 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1410 case lir_cond_less: acond = Assembler::less; break; | |
1411 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1412 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
1413 case lir_cond_greater: acond = Assembler::greater; break; | |
1414 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
1415 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
1416 default: ShouldNotReachHere(); | |
1417 } | |
1418 } | |
1419 __ jcc(acond,*(op->label())); | |
1420 } | |
1421 } | |
1422 | |
1423 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
1424 LIR_Opr src = op->in_opr(); | |
1425 LIR_Opr dest = op->result_opr(); | |
1426 | |
1427 switch (op->bytecode()) { | |
1428 case Bytecodes::_i2l: | |
304 | 1429 #ifdef _LP64 |
1430 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
1431 #else | |
0 | 1432 move_regs(src->as_register(), dest->as_register_lo()); |
1433 move_regs(src->as_register(), dest->as_register_hi()); | |
1434 __ sarl(dest->as_register_hi(), 31); | |
304 | 1435 #endif // LP64 |
0 | 1436 break; |
1437 | |
1438 case Bytecodes::_l2i: | |
1439 move_regs(src->as_register_lo(), dest->as_register()); | |
1440 break; | |
1441 | |
1442 case Bytecodes::_i2b: | |
1443 move_regs(src->as_register(), dest->as_register()); | |
1444 __ sign_extend_byte(dest->as_register()); | |
1445 break; | |
1446 | |
1447 case Bytecodes::_i2c: | |
1448 move_regs(src->as_register(), dest->as_register()); | |
1449 __ andl(dest->as_register(), 0xFFFF); | |
1450 break; | |
1451 | |
1452 case Bytecodes::_i2s: | |
1453 move_regs(src->as_register(), dest->as_register()); | |
1454 __ sign_extend_short(dest->as_register()); | |
1455 break; | |
1456 | |
1457 | |
1458 case Bytecodes::_f2d: | |
1459 case Bytecodes::_d2f: | |
1460 if (dest->is_single_xmm()) { | |
1461 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
1462 } else if (dest->is_double_xmm()) { | |
1463 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
1464 } else { | |
1465 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
1466 // do nothing (float result is rounded later through spilling) | |
1467 } | |
1468 break; | |
1469 | |
1470 case Bytecodes::_i2f: | |
1471 case Bytecodes::_i2d: | |
1472 if (dest->is_single_xmm()) { | |
304 | 1473 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
0 | 1474 } else if (dest->is_double_xmm()) { |
304 | 1475 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
0 | 1476 } else { |
1477 assert(dest->fpu() == 0, "result must be on TOS"); | |
1478 __ movl(Address(rsp, 0), src->as_register()); | |
1479 __ fild_s(Address(rsp, 0)); | |
1480 } | |
1481 break; | |
1482 | |
1483 case Bytecodes::_f2i: | |
1484 case Bytecodes::_d2i: | |
1485 if (src->is_single_xmm()) { | |
304 | 1486 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
0 | 1487 } else if (src->is_double_xmm()) { |
304 | 1488 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
0 | 1489 } else { |
1490 assert(src->fpu() == 0, "input must be on TOS"); | |
1491 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
1492 __ fist_s(Address(rsp, 0)); | |
1493 __ movl(dest->as_register(), Address(rsp, 0)); | |
1494 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
1495 } | |
1496 | |
1497 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
1498 assert(op->stub() != NULL, "stub required"); | |
1499 __ cmpl(dest->as_register(), 0x80000000); | |
1500 __ jcc(Assembler::equal, *op->stub()->entry()); | |
1501 __ bind(*op->stub()->continuation()); | |
1502 break; | |
1503 | |
1504 case Bytecodes::_l2f: | |
1505 case Bytecodes::_l2d: | |
1506 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
1507 assert(dest->fpu() == 0, "result must be on TOS"); | |
1508 | |
304 | 1509 __ movptr(Address(rsp, 0), src->as_register_lo()); |
1510 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
0 | 1511 __ fild_d(Address(rsp, 0)); |
1512 // float result is rounded later through spilling | |
1513 break; | |
1514 | |
1515 case Bytecodes::_f2l: | |
1516 case Bytecodes::_d2l: | |
1517 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
1518 assert(src->fpu() == 0, "input must be on TOS"); | |
304 | 1519 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
0 | 1520 |
1521 // instruction sequence too long to inline it here | |
1522 { | |
1523 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
1524 } | |
1525 break; | |
1526 | |
1527 default: ShouldNotReachHere(); | |
1528 } | |
1529 } | |
1530 | |
1531 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
1532 if (op->init_check()) { | |
1533 __ cmpl(Address(op->klass()->as_register(), | |
1534 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), | |
1535 instanceKlass::fully_initialized); | |
1536 add_debug_info_for_null_check_here(op->stub()->info()); | |
1537 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
1538 } | |
1539 __ allocate_object(op->obj()->as_register(), | |
1540 op->tmp1()->as_register(), | |
1541 op->tmp2()->as_register(), | |
1542 op->header_size(), | |
1543 op->object_size(), | |
1544 op->klass()->as_register(), | |
1545 *op->stub()->entry()); | |
1546 __ bind(*op->stub()->continuation()); | |
1547 } | |
1548 | |
1549 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
1550 if (UseSlowPath || | |
1551 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
1552 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
1553 __ jmp(*op->stub()->entry()); | |
1554 } else { | |
1555 Register len = op->len()->as_register(); | |
1556 Register tmp1 = op->tmp1()->as_register(); | |
1557 Register tmp2 = op->tmp2()->as_register(); | |
1558 Register tmp3 = op->tmp3()->as_register(); | |
1559 if (len == tmp1) { | |
1560 tmp1 = tmp3; | |
1561 } else if (len == tmp2) { | |
1562 tmp2 = tmp3; | |
1563 } else if (len == tmp3) { | |
1564 // everything is ok | |
1565 } else { | |
304 | 1566 __ mov(tmp3, len); |
0 | 1567 } |
1568 __ allocate_array(op->obj()->as_register(), | |
1569 len, | |
1570 tmp1, | |
1571 tmp2, | |
1572 arrayOopDesc::header_size(op->type()), | |
1573 array_element_size(op->type()), | |
1574 op->klass()->as_register(), | |
1575 *op->stub()->entry()); | |
1576 } | |
1577 __ bind(*op->stub()->continuation()); | |
1578 } | |
1579 | |
1580 | |
1581 | |
1582 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { | |
1583 LIR_Code code = op->code(); | |
1584 if (code == lir_store_check) { | |
1585 Register value = op->object()->as_register(); | |
1586 Register array = op->array()->as_register(); | |
1587 Register k_RInfo = op->tmp1()->as_register(); | |
1588 Register klass_RInfo = op->tmp2()->as_register(); | |
1589 Register Rtmp1 = op->tmp3()->as_register(); | |
1590 | |
1591 CodeStub* stub = op->stub(); | |
1592 Label done; | |
304 | 1593 __ cmpptr(value, (int32_t)NULL_WORD); |
0 | 1594 __ jcc(Assembler::equal, done); |
1595 add_debug_info_for_null_check_here(op->info_for_exception()); | |
304 | 1596 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
1597 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); | |
0 | 1598 |
1599 // get instance klass | |
304 | 1600 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
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1601 // perform the fast part of the checking logic |
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1602 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); |
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1603 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
304 | 1604 __ push(klass_RInfo); |
1605 __ push(k_RInfo); | |
0 | 1606 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1607 __ pop(klass_RInfo); |
1608 __ pop(k_RInfo); | |
1609 // result is a boolean | |
0 | 1610 __ cmpl(k_RInfo, 0); |
1611 __ jcc(Assembler::equal, *stub->entry()); | |
1612 __ bind(done); | |
1613 } else if (op->code() == lir_checkcast) { | |
1614 // we always need a stub for the failure case. | |
1615 CodeStub* stub = op->stub(); | |
1616 Register obj = op->object()->as_register(); | |
1617 Register k_RInfo = op->tmp1()->as_register(); | |
1618 Register klass_RInfo = op->tmp2()->as_register(); | |
1619 Register dst = op->result_opr()->as_register(); | |
1620 ciKlass* k = op->klass(); | |
1621 Register Rtmp1 = noreg; | |
1622 | |
1623 Label done; | |
1624 if (obj == k_RInfo) { | |
1625 k_RInfo = dst; | |
1626 } else if (obj == klass_RInfo) { | |
1627 klass_RInfo = dst; | |
1628 } | |
1629 if (k->is_loaded()) { | |
1630 select_different_registers(obj, dst, k_RInfo, klass_RInfo); | |
1631 } else { | |
1632 Rtmp1 = op->tmp3()->as_register(); | |
1633 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
1634 } | |
1635 | |
1636 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
1637 if (!k->is_loaded()) { | |
1638 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
1639 } else { | |
304 | 1640 #ifdef _LP64 |
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1641 __ movoop(k_RInfo, k->constant_encoding()); |
304 | 1642 #else |
0 | 1643 k_RInfo = noreg; |
304 | 1644 #endif // _LP64 |
0 | 1645 } |
1646 assert(obj != k_RInfo, "must be different"); | |
304 | 1647 __ cmpptr(obj, (int32_t)NULL_WORD); |
0 | 1648 if (op->profiled_method() != NULL) { |
1649 ciMethod* method = op->profiled_method(); | |
1650 int bci = op->profiled_bci(); | |
1651 | |
1652 Label profile_done; | |
1653 __ jcc(Assembler::notEqual, profile_done); | |
1654 // Object is null; update methodDataOop | |
1655 ciMethodData* md = method->method_data(); | |
1656 if (md == NULL) { | |
1657 bailout("out of memory building methodDataOop"); | |
1658 return; | |
1659 } | |
1660 ciProfileData* data = md->bci_to_data(bci); | |
1661 assert(data != NULL, "need data for checkcast"); | |
1662 assert(data->is_BitData(), "need BitData for checkcast"); | |
1663 Register mdo = klass_RInfo; | |
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1664 __ movoop(mdo, md->constant_encoding()); |
0 | 1665 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
1666 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
1667 __ orl(data_addr, header_bits); | |
1668 __ jmp(done); | |
1669 __ bind(profile_done); | |
1670 } else { | |
1671 __ jcc(Assembler::equal, done); | |
1672 } | |
1673 __ verify_oop(obj); | |
1674 | |
1675 if (op->fast_check()) { | |
1676 // get object classo | |
1677 // not a safepoint as obj null check happens earlier | |
1678 if (k->is_loaded()) { | |
304 | 1679 #ifdef _LP64 |
1680 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
1681 #else | |
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1682 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
304 | 1683 #endif // _LP64 |
0 | 1684 } else { |
304 | 1685 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
0 | 1686 |
1687 } | |
1688 __ jcc(Assembler::notEqual, *stub->entry()); | |
1689 __ bind(done); | |
1690 } else { | |
1691 // get object class | |
1692 // not a safepoint as obj null check happens earlier | |
304 | 1693 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
0 | 1694 if (k->is_loaded()) { |
1695 // See if we get an immediate positive hit | |
304 | 1696 #ifdef _LP64 |
1697 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
1698 #else | |
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1699 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
304 | 1700 #endif // _LP64 |
0 | 1701 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { |
1702 __ jcc(Assembler::notEqual, *stub->entry()); | |
1703 } else { | |
1704 // See if we get an immediate positive hit | |
1705 __ jcc(Assembler::equal, done); | |
1706 // check for self | |
304 | 1707 #ifdef _LP64 |
1708 __ cmpptr(klass_RInfo, k_RInfo); | |
1709 #else | |
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1710 __ cmpoop(klass_RInfo, k->constant_encoding()); |
304 | 1711 #endif // _LP64 |
0 | 1712 __ jcc(Assembler::equal, done); |
1713 | |
304 | 1714 __ push(klass_RInfo); |
1715 #ifdef _LP64 | |
1716 __ push(k_RInfo); | |
1717 #else | |
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1718 __ pushoop(k->constant_encoding()); |
304 | 1719 #endif // _LP64 |
0 | 1720 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1721 __ pop(klass_RInfo); |
1722 __ pop(klass_RInfo); | |
1723 // result is a boolean | |
0 | 1724 __ cmpl(klass_RInfo, 0); |
1725 __ jcc(Assembler::equal, *stub->entry()); | |
1726 } | |
1727 __ bind(done); | |
1728 } else { | |
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1729 // perform the fast part of the checking logic |
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1730 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, &done, stub->entry(), NULL); |
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1731 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
304 | 1732 __ push(klass_RInfo); |
1733 __ push(k_RInfo); | |
0 | 1734 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1735 __ pop(klass_RInfo); |
1736 __ pop(k_RInfo); | |
1737 // result is a boolean | |
0 | 1738 __ cmpl(k_RInfo, 0); |
1739 __ jcc(Assembler::equal, *stub->entry()); | |
1740 __ bind(done); | |
1741 } | |
1742 | |
1743 } | |
1744 if (dst != obj) { | |
304 | 1745 __ mov(dst, obj); |
0 | 1746 } |
1747 } else if (code == lir_instanceof) { | |
1748 Register obj = op->object()->as_register(); | |
1749 Register k_RInfo = op->tmp1()->as_register(); | |
1750 Register klass_RInfo = op->tmp2()->as_register(); | |
1751 Register dst = op->result_opr()->as_register(); | |
1752 ciKlass* k = op->klass(); | |
1753 | |
1754 Label done; | |
1755 Label zero; | |
1756 Label one; | |
1757 if (obj == k_RInfo) { | |
1758 k_RInfo = klass_RInfo; | |
1759 klass_RInfo = obj; | |
1760 } | |
1761 // patching may screw with our temporaries on sparc, | |
1762 // so let's do it before loading the class | |
1763 if (!k->is_loaded()) { | |
1764 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
304 | 1765 } else { |
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1766 LP64_ONLY(__ movoop(k_RInfo, k->constant_encoding())); |
0 | 1767 } |
1768 assert(obj != k_RInfo, "must be different"); | |
1769 | |
1770 __ verify_oop(obj); | |
1771 if (op->fast_check()) { | |
304 | 1772 __ cmpptr(obj, (int32_t)NULL_WORD); |
0 | 1773 __ jcc(Assembler::equal, zero); |
1774 // get object class | |
1775 // not a safepoint as obj null check happens earlier | |
304 | 1776 if (LP64_ONLY(false &&) k->is_loaded()) { |
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1777 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding())); |
0 | 1778 k_RInfo = noreg; |
1779 } else { | |
304 | 1780 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
0 | 1781 |
1782 } | |
1783 __ jcc(Assembler::equal, one); | |
1784 } else { | |
1785 // get object class | |
1786 // not a safepoint as obj null check happens earlier | |
304 | 1787 __ cmpptr(obj, (int32_t)NULL_WORD); |
0 | 1788 __ jcc(Assembler::equal, zero); |
304 | 1789 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); |
1790 | |
1791 #ifndef _LP64 | |
0 | 1792 if (k->is_loaded()) { |
1793 // See if we get an immediate positive hit | |
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1794 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
0 | 1795 __ jcc(Assembler::equal, one); |
1796 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { | |
1797 // check for self | |
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1798 __ cmpoop(klass_RInfo, k->constant_encoding()); |
0 | 1799 __ jcc(Assembler::equal, one); |
304 | 1800 __ push(klass_RInfo); |
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1801 __ pushoop(k->constant_encoding()); |
0 | 1802 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1803 __ pop(klass_RInfo); |
1804 __ pop(dst); | |
0 | 1805 __ jmp(done); |
1806 } | |
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1807 } |
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1808 else // next block is unconditional if LP64: |
304 | 1809 #endif // LP64 |
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1810 { |
0 | 1811 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); |
1812 | |
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1813 // perform the fast part of the checking logic |
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1814 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, dst, &one, &zero, NULL); |
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1815 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
304 | 1816 __ push(klass_RInfo); |
1817 __ push(k_RInfo); | |
0 | 1818 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1819 __ pop(klass_RInfo); |
1820 __ pop(dst); | |
0 | 1821 __ jmp(done); |
1822 } | |
1823 } | |
1824 __ bind(zero); | |
304 | 1825 __ xorptr(dst, dst); |
0 | 1826 __ jmp(done); |
1827 __ bind(one); | |
304 | 1828 __ movptr(dst, 1); |
0 | 1829 __ bind(done); |
1830 } else { | |
1831 ShouldNotReachHere(); | |
1832 } | |
1833 | |
1834 } | |
1835 | |
1836 | |
1837 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
304 | 1838 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
0 | 1839 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
1840 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
1841 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
1842 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
1843 Register addr = op->addr()->as_register(); | |
1844 if (os::is_MP()) { | |
1845 __ lock(); | |
1846 } | |
304 | 1847 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
1848 | |
1849 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
1850 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
1851 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
0 | 1852 Register newval = op->new_value()->as_register(); |
1853 Register cmpval = op->cmp_value()->as_register(); | |
1854 assert(cmpval == rax, "wrong register"); | |
1855 assert(newval != NULL, "new val must be register"); | |
1856 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
1857 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
1858 assert(newval != addr, "new value and addr must be in different registers"); | |
1859 if (os::is_MP()) { | |
1860 __ lock(); | |
1861 } | |
304 | 1862 if ( op->code() == lir_cas_obj) { |
1863 __ cmpxchgptr(newval, Address(addr, 0)); | |
1864 } else if (op->code() == lir_cas_int) { | |
1865 __ cmpxchgl(newval, Address(addr, 0)); | |
1866 } else { | |
1867 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); | |
1868 } | |
1869 #ifdef _LP64 | |
1870 } else if (op->code() == lir_cas_long) { | |
1871 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
1872 Register newval = op->new_value()->as_register_lo(); | |
1873 Register cmpval = op->cmp_value()->as_register_lo(); | |
1874 assert(cmpval == rax, "wrong register"); | |
1875 assert(newval != NULL, "new val must be register"); | |
1876 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
1877 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
1878 assert(newval != addr, "new value and addr must be in different registers"); | |
1879 if (os::is_MP()) { | |
1880 __ lock(); | |
1881 } | |
1882 __ cmpxchgq(newval, Address(addr, 0)); | |
1883 #endif // _LP64 | |
0 | 1884 } else { |
1885 Unimplemented(); | |
1886 } | |
1887 } | |
1888 | |
1889 | |
1890 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { | |
1891 Assembler::Condition acond, ncond; | |
1892 switch (condition) { | |
1893 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
1894 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
1895 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
1896 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
1897 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
1898 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
1899 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
1900 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
1901 default: ShouldNotReachHere(); | |
1902 } | |
1903 | |
1904 if (opr1->is_cpu_register()) { | |
1905 reg2reg(opr1, result); | |
1906 } else if (opr1->is_stack()) { | |
1907 stack2reg(opr1, result, result->type()); | |
1908 } else if (opr1->is_constant()) { | |
1909 const2reg(opr1, result, lir_patch_none, NULL); | |
1910 } else { | |
1911 ShouldNotReachHere(); | |
1912 } | |
1913 | |
1914 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
1915 // optimized version that does not require a branch | |
1916 if (opr2->is_single_cpu()) { | |
1917 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
304 | 1918 __ cmov(ncond, result->as_register(), opr2->as_register()); |
0 | 1919 } else if (opr2->is_double_cpu()) { |
1920 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
1921 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
304 | 1922 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
1923 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
0 | 1924 } else if (opr2->is_single_stack()) { |
1925 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
1926 } else if (opr2->is_double_stack()) { | |
304 | 1927 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
1928 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
0 | 1929 } else { |
1930 ShouldNotReachHere(); | |
1931 } | |
1932 | |
1933 } else { | |
1934 Label skip; | |
1935 __ jcc (acond, skip); | |
1936 if (opr2->is_cpu_register()) { | |
1937 reg2reg(opr2, result); | |
1938 } else if (opr2->is_stack()) { | |
1939 stack2reg(opr2, result, result->type()); | |
1940 } else if (opr2->is_constant()) { | |
1941 const2reg(opr2, result, lir_patch_none, NULL); | |
1942 } else { | |
1943 ShouldNotReachHere(); | |
1944 } | |
1945 __ bind(skip); | |
1946 } | |
1947 } | |
1948 | |
1949 | |
1950 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
1951 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
1952 | |
1953 if (left->is_single_cpu()) { | |
1954 assert(left == dest, "left and dest must be equal"); | |
1955 Register lreg = left->as_register(); | |
1956 | |
1957 if (right->is_single_cpu()) { | |
1958 // cpu register - cpu register | |
1959 Register rreg = right->as_register(); | |
1960 switch (code) { | |
1961 case lir_add: __ addl (lreg, rreg); break; | |
1962 case lir_sub: __ subl (lreg, rreg); break; | |
1963 case lir_mul: __ imull(lreg, rreg); break; | |
1964 default: ShouldNotReachHere(); | |
1965 } | |
1966 | |
1967 } else if (right->is_stack()) { | |
1968 // cpu register - stack | |
1969 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
1970 switch (code) { | |
1971 case lir_add: __ addl(lreg, raddr); break; | |
1972 case lir_sub: __ subl(lreg, raddr); break; | |
1973 default: ShouldNotReachHere(); | |
1974 } | |
1975 | |
1976 } else if (right->is_constant()) { | |
1977 // cpu register - constant | |
1978 jint c = right->as_constant_ptr()->as_jint(); | |
1979 switch (code) { | |
1980 case lir_add: { | |
1981 __ increment(lreg, c); | |
1982 break; | |
1983 } | |
1984 case lir_sub: { | |
1985 __ decrement(lreg, c); | |
1986 break; | |
1987 } | |
1988 default: ShouldNotReachHere(); | |
1989 } | |
1990 | |
1991 } else { | |
1992 ShouldNotReachHere(); | |
1993 } | |
1994 | |
1995 } else if (left->is_double_cpu()) { | |
1996 assert(left == dest, "left and dest must be equal"); | |
1997 Register lreg_lo = left->as_register_lo(); | |
1998 Register lreg_hi = left->as_register_hi(); | |
1999 | |
2000 if (right->is_double_cpu()) { | |
2001 // cpu register - cpu register | |
2002 Register rreg_lo = right->as_register_lo(); | |
2003 Register rreg_hi = right->as_register_hi(); | |
304 | 2004 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
2005 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
0 | 2006 switch (code) { |
2007 case lir_add: | |
304 | 2008 __ addptr(lreg_lo, rreg_lo); |
2009 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
0 | 2010 break; |
2011 case lir_sub: | |
304 | 2012 __ subptr(lreg_lo, rreg_lo); |
2013 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
0 | 2014 break; |
2015 case lir_mul: | |
304 | 2016 #ifdef _LP64 |
2017 __ imulq(lreg_lo, rreg_lo); | |
2018 #else | |
0 | 2019 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
2020 __ imull(lreg_hi, rreg_lo); | |
2021 __ imull(rreg_hi, lreg_lo); | |
2022 __ addl (rreg_hi, lreg_hi); | |
2023 __ mull (rreg_lo); | |
2024 __ addl (lreg_hi, rreg_hi); | |
304 | 2025 #endif // _LP64 |
0 | 2026 break; |
2027 default: | |
2028 ShouldNotReachHere(); | |
2029 } | |
2030 | |
2031 } else if (right->is_constant()) { | |
2032 // cpu register - constant | |
304 | 2033 #ifdef _LP64 |
2034 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
2035 __ movptr(r10, (intptr_t) c); | |
2036 switch (code) { | |
2037 case lir_add: | |
2038 __ addptr(lreg_lo, r10); | |
2039 break; | |
2040 case lir_sub: | |
2041 __ subptr(lreg_lo, r10); | |
2042 break; | |
2043 default: | |
2044 ShouldNotReachHere(); | |
2045 } | |
2046 #else | |
0 | 2047 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
2048 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
2049 switch (code) { | |
2050 case lir_add: | |
304 | 2051 __ addptr(lreg_lo, c_lo); |
0 | 2052 __ adcl(lreg_hi, c_hi); |
2053 break; | |
2054 case lir_sub: | |
304 | 2055 __ subptr(lreg_lo, c_lo); |
0 | 2056 __ sbbl(lreg_hi, c_hi); |
2057 break; | |
2058 default: | |
2059 ShouldNotReachHere(); | |
2060 } | |
304 | 2061 #endif // _LP64 |
0 | 2062 |
2063 } else { | |
2064 ShouldNotReachHere(); | |
2065 } | |
2066 | |
2067 } else if (left->is_single_xmm()) { | |
2068 assert(left == dest, "left and dest must be equal"); | |
2069 XMMRegister lreg = left->as_xmm_float_reg(); | |
2070 | |
2071 if (right->is_single_xmm()) { | |
2072 XMMRegister rreg = right->as_xmm_float_reg(); | |
2073 switch (code) { | |
2074 case lir_add: __ addss(lreg, rreg); break; | |
2075 case lir_sub: __ subss(lreg, rreg); break; | |
2076 case lir_mul_strictfp: // fall through | |
2077 case lir_mul: __ mulss(lreg, rreg); break; | |
2078 case lir_div_strictfp: // fall through | |
2079 case lir_div: __ divss(lreg, rreg); break; | |
2080 default: ShouldNotReachHere(); | |
2081 } | |
2082 } else { | |
2083 Address raddr; | |
2084 if (right->is_single_stack()) { | |
2085 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2086 } else if (right->is_constant()) { | |
2087 // hack for now | |
2088 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
2089 } else { | |
2090 ShouldNotReachHere(); | |
2091 } | |
2092 switch (code) { | |
2093 case lir_add: __ addss(lreg, raddr); break; | |
2094 case lir_sub: __ subss(lreg, raddr); break; | |
2095 case lir_mul_strictfp: // fall through | |
2096 case lir_mul: __ mulss(lreg, raddr); break; | |
2097 case lir_div_strictfp: // fall through | |
2098 case lir_div: __ divss(lreg, raddr); break; | |
2099 default: ShouldNotReachHere(); | |
2100 } | |
2101 } | |
2102 | |
2103 } else if (left->is_double_xmm()) { | |
2104 assert(left == dest, "left and dest must be equal"); | |
2105 | |
2106 XMMRegister lreg = left->as_xmm_double_reg(); | |
2107 if (right->is_double_xmm()) { | |
2108 XMMRegister rreg = right->as_xmm_double_reg(); | |
2109 switch (code) { | |
2110 case lir_add: __ addsd(lreg, rreg); break; | |
2111 case lir_sub: __ subsd(lreg, rreg); break; | |
2112 case lir_mul_strictfp: // fall through | |
2113 case lir_mul: __ mulsd(lreg, rreg); break; | |
2114 case lir_div_strictfp: // fall through | |
2115 case lir_div: __ divsd(lreg, rreg); break; | |
2116 default: ShouldNotReachHere(); | |
2117 } | |
2118 } else { | |
2119 Address raddr; | |
2120 if (right->is_double_stack()) { | |
2121 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2122 } else if (right->is_constant()) { | |
2123 // hack for now | |
2124 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2125 } else { | |
2126 ShouldNotReachHere(); | |
2127 } | |
2128 switch (code) { | |
2129 case lir_add: __ addsd(lreg, raddr); break; | |
2130 case lir_sub: __ subsd(lreg, raddr); break; | |
2131 case lir_mul_strictfp: // fall through | |
2132 case lir_mul: __ mulsd(lreg, raddr); break; | |
2133 case lir_div_strictfp: // fall through | |
2134 case lir_div: __ divsd(lreg, raddr); break; | |
2135 default: ShouldNotReachHere(); | |
2136 } | |
2137 } | |
2138 | |
2139 } else if (left->is_single_fpu()) { | |
2140 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
2141 | |
2142 if (right->is_single_fpu()) { | |
2143 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
2144 | |
2145 } else { | |
2146 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
2147 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
2148 | |
2149 Address raddr; | |
2150 if (right->is_single_stack()) { | |
2151 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2152 } else if (right->is_constant()) { | |
2153 address const_addr = float_constant(right->as_jfloat()); | |
2154 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
2155 // hack for now | |
2156 raddr = __ as_Address(InternalAddress(const_addr)); | |
2157 } else { | |
2158 ShouldNotReachHere(); | |
2159 } | |
2160 | |
2161 switch (code) { | |
2162 case lir_add: __ fadd_s(raddr); break; | |
2163 case lir_sub: __ fsub_s(raddr); break; | |
2164 case lir_mul_strictfp: // fall through | |
2165 case lir_mul: __ fmul_s(raddr); break; | |
2166 case lir_div_strictfp: // fall through | |
2167 case lir_div: __ fdiv_s(raddr); break; | |
2168 default: ShouldNotReachHere(); | |
2169 } | |
2170 } | |
2171 | |
2172 } else if (left->is_double_fpu()) { | |
2173 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
2174 | |
2175 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2176 // Double values require special handling for strictfp mul/div on x86 | |
2177 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
2178 __ fmulp(left->fpu_regnrLo() + 1); | |
2179 } | |
2180 | |
2181 if (right->is_double_fpu()) { | |
2182 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
2183 | |
2184 } else { | |
2185 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
2186 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
2187 | |
2188 Address raddr; | |
2189 if (right->is_double_stack()) { | |
2190 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2191 } else if (right->is_constant()) { | |
2192 // hack for now | |
2193 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2194 } else { | |
2195 ShouldNotReachHere(); | |
2196 } | |
2197 | |
2198 switch (code) { | |
2199 case lir_add: __ fadd_d(raddr); break; | |
2200 case lir_sub: __ fsub_d(raddr); break; | |
2201 case lir_mul_strictfp: // fall through | |
2202 case lir_mul: __ fmul_d(raddr); break; | |
2203 case lir_div_strictfp: // fall through | |
2204 case lir_div: __ fdiv_d(raddr); break; | |
2205 default: ShouldNotReachHere(); | |
2206 } | |
2207 } | |
2208 | |
2209 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2210 // Double values require special handling for strictfp mul/div on x86 | |
2211 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
2212 __ fmulp(dest->fpu_regnrLo() + 1); | |
2213 } | |
2214 | |
2215 } else if (left->is_single_stack() || left->is_address()) { | |
2216 assert(left == dest, "left and dest must be equal"); | |
2217 | |
2218 Address laddr; | |
2219 if (left->is_single_stack()) { | |
2220 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
2221 } else if (left->is_address()) { | |
2222 laddr = as_Address(left->as_address_ptr()); | |
2223 } else { | |
2224 ShouldNotReachHere(); | |
2225 } | |
2226 | |
2227 if (right->is_single_cpu()) { | |
2228 Register rreg = right->as_register(); | |
2229 switch (code) { | |
2230 case lir_add: __ addl(laddr, rreg); break; | |
2231 case lir_sub: __ subl(laddr, rreg); break; | |
2232 default: ShouldNotReachHere(); | |
2233 } | |
2234 } else if (right->is_constant()) { | |
2235 jint c = right->as_constant_ptr()->as_jint(); | |
2236 switch (code) { | |
2237 case lir_add: { | |
304 | 2238 __ incrementl(laddr, c); |
0 | 2239 break; |
2240 } | |
2241 case lir_sub: { | |
304 | 2242 __ decrementl(laddr, c); |
0 | 2243 break; |
2244 } | |
2245 default: ShouldNotReachHere(); | |
2246 } | |
2247 } else { | |
2248 ShouldNotReachHere(); | |
2249 } | |
2250 | |
2251 } else { | |
2252 ShouldNotReachHere(); | |
2253 } | |
2254 } | |
2255 | |
2256 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
2257 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
2258 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
2259 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
2260 | |
2261 bool left_is_tos = (left_index == 0); | |
2262 bool dest_is_tos = (dest_index == 0); | |
2263 int non_tos_index = (left_is_tos ? right_index : left_index); | |
2264 | |
2265 switch (code) { | |
2266 case lir_add: | |
2267 if (pop_fpu_stack) __ faddp(non_tos_index); | |
2268 else if (dest_is_tos) __ fadd (non_tos_index); | |
2269 else __ fadda(non_tos_index); | |
2270 break; | |
2271 | |
2272 case lir_sub: | |
2273 if (left_is_tos) { | |
2274 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
2275 else if (dest_is_tos) __ fsub (non_tos_index); | |
2276 else __ fsubra(non_tos_index); | |
2277 } else { | |
2278 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
2279 else if (dest_is_tos) __ fsubr (non_tos_index); | |
2280 else __ fsuba (non_tos_index); | |
2281 } | |
2282 break; | |
2283 | |
2284 case lir_mul_strictfp: // fall through | |
2285 case lir_mul: | |
2286 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
2287 else if (dest_is_tos) __ fmul (non_tos_index); | |
2288 else __ fmula(non_tos_index); | |
2289 break; | |
2290 | |
2291 case lir_div_strictfp: // fall through | |
2292 case lir_div: | |
2293 if (left_is_tos) { | |
2294 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
2295 else if (dest_is_tos) __ fdiv (non_tos_index); | |
2296 else __ fdivra(non_tos_index); | |
2297 } else { | |
2298 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
2299 else if (dest_is_tos) __ fdivr (non_tos_index); | |
2300 else __ fdiva (non_tos_index); | |
2301 } | |
2302 break; | |
2303 | |
2304 case lir_rem: | |
2305 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
2306 __ fremr(noreg); | |
2307 break; | |
2308 | |
2309 default: | |
2310 ShouldNotReachHere(); | |
2311 } | |
2312 } | |
2313 | |
2314 | |
2315 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
2316 if (value->is_double_xmm()) { | |
2317 switch(code) { | |
2318 case lir_abs : | |
2319 { | |
2320 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
2321 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
2322 } | |
2323 __ andpd(dest->as_xmm_double_reg(), | |
2324 ExternalAddress((address)double_signmask_pool)); | |
2325 } | |
2326 break; | |
2327 | |
2328 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
2329 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
2330 default : ShouldNotReachHere(); | |
2331 } | |
2332 | |
2333 } else if (value->is_double_fpu()) { | |
2334 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
2335 switch(code) { | |
2336 case lir_log : __ flog() ; break; | |
2337 case lir_log10 : __ flog10() ; break; | |
2338 case lir_abs : __ fabs() ; break; | |
2339 case lir_sqrt : __ fsqrt(); break; | |
2340 case lir_sin : | |
2341 // Should consider not saving rbx, if not necessary | |
2342 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
2343 break; | |
2344 case lir_cos : | |
2345 // Should consider not saving rbx, if not necessary | |
2346 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
2347 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
2348 break; | |
2349 case lir_tan : | |
2350 // Should consider not saving rbx, if not necessary | |
2351 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
2352 break; | |
2353 default : ShouldNotReachHere(); | |
2354 } | |
2355 } else { | |
2356 Unimplemented(); | |
2357 } | |
2358 } | |
2359 | |
2360 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
2361 // assert(left->destroys_register(), "check"); | |
2362 if (left->is_single_cpu()) { | |
2363 Register reg = left->as_register(); | |
2364 if (right->is_constant()) { | |
2365 int val = right->as_constant_ptr()->as_jint(); | |
2366 switch (code) { | |
2367 case lir_logic_and: __ andl (reg, val); break; | |
2368 case lir_logic_or: __ orl (reg, val); break; | |
2369 case lir_logic_xor: __ xorl (reg, val); break; | |
2370 default: ShouldNotReachHere(); | |
2371 } | |
2372 } else if (right->is_stack()) { | |
2373 // added support for stack operands | |
2374 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2375 switch (code) { | |
2376 case lir_logic_and: __ andl (reg, raddr); break; | |
2377 case lir_logic_or: __ orl (reg, raddr); break; | |
2378 case lir_logic_xor: __ xorl (reg, raddr); break; | |
2379 default: ShouldNotReachHere(); | |
2380 } | |
2381 } else { | |
2382 Register rright = right->as_register(); | |
2383 switch (code) { | |
304 | 2384 case lir_logic_and: __ andptr (reg, rright); break; |
2385 case lir_logic_or : __ orptr (reg, rright); break; | |
2386 case lir_logic_xor: __ xorptr (reg, rright); break; | |
0 | 2387 default: ShouldNotReachHere(); |
2388 } | |
2389 } | |
2390 move_regs(reg, dst->as_register()); | |
2391 } else { | |
2392 Register l_lo = left->as_register_lo(); | |
2393 Register l_hi = left->as_register_hi(); | |
2394 if (right->is_constant()) { | |
304 | 2395 #ifdef _LP64 |
2396 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
2397 switch (code) { | |
2398 case lir_logic_and: | |
2399 __ andq(l_lo, rscratch1); | |
2400 break; | |
2401 case lir_logic_or: | |
2402 __ orq(l_lo, rscratch1); | |
2403 break; | |
2404 case lir_logic_xor: | |
2405 __ xorq(l_lo, rscratch1); | |
2406 break; | |
2407 default: ShouldNotReachHere(); | |
2408 } | |
2409 #else | |
0 | 2410 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
2411 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
2412 switch (code) { | |
2413 case lir_logic_and: | |
2414 __ andl(l_lo, r_lo); | |
2415 __ andl(l_hi, r_hi); | |
2416 break; | |
2417 case lir_logic_or: | |
2418 __ orl(l_lo, r_lo); | |
2419 __ orl(l_hi, r_hi); | |
2420 break; | |
2421 case lir_logic_xor: | |
2422 __ xorl(l_lo, r_lo); | |
2423 __ xorl(l_hi, r_hi); | |
2424 break; | |
2425 default: ShouldNotReachHere(); | |
2426 } | |
304 | 2427 #endif // _LP64 |
0 | 2428 } else { |
2429 Register r_lo = right->as_register_lo(); | |
2430 Register r_hi = right->as_register_hi(); | |
2431 assert(l_lo != r_hi, "overwriting registers"); | |
2432 switch (code) { | |
2433 case lir_logic_and: | |
304 | 2434 __ andptr(l_lo, r_lo); |
2435 NOT_LP64(__ andptr(l_hi, r_hi);) | |
0 | 2436 break; |
2437 case lir_logic_or: | |
304 | 2438 __ orptr(l_lo, r_lo); |
2439 NOT_LP64(__ orptr(l_hi, r_hi);) | |
0 | 2440 break; |
2441 case lir_logic_xor: | |
304 | 2442 __ xorptr(l_lo, r_lo); |
2443 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
0 | 2444 break; |
2445 default: ShouldNotReachHere(); | |
2446 } | |
2447 } | |
2448 | |
2449 Register dst_lo = dst->as_register_lo(); | |
2450 Register dst_hi = dst->as_register_hi(); | |
2451 | |
304 | 2452 #ifdef _LP64 |
2453 move_regs(l_lo, dst_lo); | |
2454 #else | |
0 | 2455 if (dst_lo == l_hi) { |
2456 assert(dst_hi != l_lo, "overwriting registers"); | |
2457 move_regs(l_hi, dst_hi); | |
2458 move_regs(l_lo, dst_lo); | |
2459 } else { | |
2460 assert(dst_lo != l_hi, "overwriting registers"); | |
2461 move_regs(l_lo, dst_lo); | |
2462 move_regs(l_hi, dst_hi); | |
2463 } | |
304 | 2464 #endif // _LP64 |
0 | 2465 } |
2466 } | |
2467 | |
2468 | |
2469 // we assume that rax, and rdx can be overwritten | |
2470 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
2471 | |
2472 assert(left->is_single_cpu(), "left must be register"); | |
2473 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
2474 assert(result->is_single_cpu(), "result must be register"); | |
2475 | |
2476 // assert(left->destroys_register(), "check"); | |
2477 // assert(right->destroys_register(), "check"); | |
2478 | |
2479 Register lreg = left->as_register(); | |
2480 Register dreg = result->as_register(); | |
2481 | |
2482 if (right->is_constant()) { | |
2483 int divisor = right->as_constant_ptr()->as_jint(); | |
2484 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
2485 if (code == lir_idiv) { | |
2486 assert(lreg == rax, "must be rax,"); | |
2487 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2488 __ cdql(); // sign extend into rdx:rax | |
2489 if (divisor == 2) { | |
2490 __ subl(lreg, rdx); | |
2491 } else { | |
2492 __ andl(rdx, divisor - 1); | |
2493 __ addl(lreg, rdx); | |
2494 } | |
2495 __ sarl(lreg, log2_intptr(divisor)); | |
2496 move_regs(lreg, dreg); | |
2497 } else if (code == lir_irem) { | |
2498 Label done; | |
304 | 2499 __ mov(dreg, lreg); |
0 | 2500 __ andl(dreg, 0x80000000 | (divisor - 1)); |
2501 __ jcc(Assembler::positive, done); | |
2502 __ decrement(dreg); | |
2503 __ orl(dreg, ~(divisor - 1)); | |
2504 __ increment(dreg); | |
2505 __ bind(done); | |
2506 } else { | |
2507 ShouldNotReachHere(); | |
2508 } | |
2509 } else { | |
2510 Register rreg = right->as_register(); | |
2511 assert(lreg == rax, "left register must be rax,"); | |
2512 assert(rreg != rdx, "right register must not be rdx"); | |
2513 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2514 | |
2515 move_regs(lreg, rax); | |
2516 | |
2517 int idivl_offset = __ corrected_idivl(rreg); | |
2518 add_debug_info_for_div0(idivl_offset, info); | |
2519 if (code == lir_irem) { | |
2520 move_regs(rdx, dreg); // result is in rdx | |
2521 } else { | |
2522 move_regs(rax, dreg); | |
2523 } | |
2524 } | |
2525 } | |
2526 | |
2527 | |
2528 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
2529 if (opr1->is_single_cpu()) { | |
2530 Register reg1 = opr1->as_register(); | |
2531 if (opr2->is_single_cpu()) { | |
2532 // cpu register - cpu register | |
304 | 2533 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2534 __ cmpptr(reg1, opr2->as_register()); | |
2535 } else { | |
2536 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
2537 __ cmpl(reg1, opr2->as_register()); | |
2538 } | |
0 | 2539 } else if (opr2->is_stack()) { |
2540 // cpu register - stack | |
304 | 2541 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2542 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2543 } else { | |
2544 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2545 } | |
0 | 2546 } else if (opr2->is_constant()) { |
2547 // cpu register - constant | |
2548 LIR_Const* c = opr2->as_constant_ptr(); | |
2549 if (c->type() == T_INT) { | |
2550 __ cmpl(reg1, c->as_jint()); | |
304 | 2551 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2552 // In 64bit oops are single register | |
0 | 2553 jobject o = c->as_jobject(); |
2554 if (o == NULL) { | |
304 | 2555 __ cmpptr(reg1, (int32_t)NULL_WORD); |
0 | 2556 } else { |
304 | 2557 #ifdef _LP64 |
2558 __ movoop(rscratch1, o); | |
2559 __ cmpptr(reg1, rscratch1); | |
2560 #else | |
0 | 2561 __ cmpoop(reg1, c->as_jobject()); |
304 | 2562 #endif // _LP64 |
0 | 2563 } |
2564 } else { | |
2565 ShouldNotReachHere(); | |
2566 } | |
2567 // cpu register - address | |
2568 } else if (opr2->is_address()) { | |
2569 if (op->info() != NULL) { | |
2570 add_debug_info_for_null_check_here(op->info()); | |
2571 } | |
2572 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
2573 } else { | |
2574 ShouldNotReachHere(); | |
2575 } | |
2576 | |
2577 } else if(opr1->is_double_cpu()) { | |
2578 Register xlo = opr1->as_register_lo(); | |
2579 Register xhi = opr1->as_register_hi(); | |
2580 if (opr2->is_double_cpu()) { | |
304 | 2581 #ifdef _LP64 |
2582 __ cmpptr(xlo, opr2->as_register_lo()); | |
2583 #else | |
0 | 2584 // cpu register - cpu register |
2585 Register ylo = opr2->as_register_lo(); | |
2586 Register yhi = opr2->as_register_hi(); | |
2587 __ subl(xlo, ylo); | |
2588 __ sbbl(xhi, yhi); | |
2589 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
2590 __ orl(xhi, xlo); | |
2591 } | |
304 | 2592 #endif // _LP64 |
0 | 2593 } else if (opr2->is_constant()) { |
2594 // cpu register - constant 0 | |
2595 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
304 | 2596 #ifdef _LP64 |
2597 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
2598 #else | |
0 | 2599 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
2600 __ orl(xhi, xlo); | |
304 | 2601 #endif // _LP64 |
0 | 2602 } else { |
2603 ShouldNotReachHere(); | |
2604 } | |
2605 | |
2606 } else if (opr1->is_single_xmm()) { | |
2607 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
2608 if (opr2->is_single_xmm()) { | |
2609 // xmm register - xmm register | |
2610 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
2611 } else if (opr2->is_stack()) { | |
2612 // xmm register - stack | |
2613 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2614 } else if (opr2->is_constant()) { | |
2615 // xmm register - constant | |
2616 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
2617 } else if (opr2->is_address()) { | |
2618 // xmm register - address | |
2619 if (op->info() != NULL) { | |
2620 add_debug_info_for_null_check_here(op->info()); | |
2621 } | |
2622 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
2623 } else { | |
2624 ShouldNotReachHere(); | |
2625 } | |
2626 | |
2627 } else if (opr1->is_double_xmm()) { | |
2628 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
2629 if (opr2->is_double_xmm()) { | |
2630 // xmm register - xmm register | |
2631 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
2632 } else if (opr2->is_stack()) { | |
2633 // xmm register - stack | |
2634 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
2635 } else if (opr2->is_constant()) { | |
2636 // xmm register - constant | |
2637 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
2638 } else if (opr2->is_address()) { | |
2639 // xmm register - address | |
2640 if (op->info() != NULL) { | |
2641 add_debug_info_for_null_check_here(op->info()); | |
2642 } | |
2643 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
2644 } else { | |
2645 ShouldNotReachHere(); | |
2646 } | |
2647 | |
2648 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
2649 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
2650 assert(opr2->is_fpu_register(), "both must be registers"); | |
2651 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2652 | |
2653 } else if (opr1->is_address() && opr2->is_constant()) { | |
304 | 2654 LIR_Const* c = opr2->as_constant_ptr(); |
2655 #ifdef _LP64 | |
2656 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
2657 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
2658 __ movoop(rscratch1, c->as_jobject()); | |
2659 } | |
2660 #endif // LP64 | |
0 | 2661 if (op->info() != NULL) { |
2662 add_debug_info_for_null_check_here(op->info()); | |
2663 } | |
2664 // special case: address - constant | |
2665 LIR_Address* addr = opr1->as_address_ptr(); | |
2666 if (c->type() == T_INT) { | |
2667 __ cmpl(as_Address(addr), c->as_jint()); | |
304 | 2668 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2669 #ifdef _LP64 | |
2670 // %%% Make this explode if addr isn't reachable until we figure out a | |
2671 // better strategy by giving noreg as the temp for as_Address | |
2672 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
2673 #else | |
0 | 2674 __ cmpoop(as_Address(addr), c->as_jobject()); |
304 | 2675 #endif // _LP64 |
0 | 2676 } else { |
2677 ShouldNotReachHere(); | |
2678 } | |
2679 | |
2680 } else { | |
2681 ShouldNotReachHere(); | |
2682 } | |
2683 } | |
2684 | |
2685 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
2686 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
2687 if (left->is_single_xmm()) { | |
2688 assert(right->is_single_xmm(), "must match"); | |
2689 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2690 } else if (left->is_double_xmm()) { | |
2691 assert(right->is_double_xmm(), "must match"); | |
2692 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2693 | |
2694 } else { | |
2695 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
2696 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
2697 | |
2698 assert(left->fpu() == 0, "left must be on TOS"); | |
2699 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
2700 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2701 } | |
2702 } else { | |
2703 assert(code == lir_cmp_l2i, "check"); | |
304 | 2704 #ifdef _LP64 |
2705 Register dest = dst->as_register(); | |
2706 __ xorptr(dest, dest); | |
2707 Label high, done; | |
2708 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
2709 __ jcc(Assembler::equal, done); | |
2710 __ jcc(Assembler::greater, high); | |
2711 __ decrement(dest); | |
2712 __ jmp(done); | |
2713 __ bind(high); | |
2714 __ increment(dest); | |
2715 | |
2716 __ bind(done); | |
2717 | |
2718 #else | |
0 | 2719 __ lcmp2int(left->as_register_hi(), |
2720 left->as_register_lo(), | |
2721 right->as_register_hi(), | |
2722 right->as_register_lo()); | |
2723 move_regs(left->as_register_hi(), dst->as_register()); | |
304 | 2724 #endif // _LP64 |
0 | 2725 } |
2726 } | |
2727 | |
2728 | |
2729 void LIR_Assembler::align_call(LIR_Code code) { | |
2730 if (os::is_MP()) { | |
2731 // make sure that the displacement word of the call ends up word aligned | |
2732 int offset = __ offset(); | |
2733 switch (code) { | |
2734 case lir_static_call: | |
2735 case lir_optvirtual_call: | |
2736 offset += NativeCall::displacement_offset; | |
2737 break; | |
2738 case lir_icvirtual_call: | |
2739 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
2740 break; | |
2741 case lir_virtual_call: // currently, sparc-specific for niagara | |
2742 default: ShouldNotReachHere(); | |
2743 } | |
2744 while (offset++ % BytesPerWord != 0) { | |
2745 __ nop(); | |
2746 } | |
2747 } | |
2748 } | |
2749 | |
2750 | |
2751 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { | |
2752 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
2753 "must be aligned"); | |
2754 __ call(AddressLiteral(entry, rtype)); | |
2755 add_call_info(code_offset(), info); | |
2756 } | |
2757 | |
2758 | |
2759 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { | |
2760 RelocationHolder rh = virtual_call_Relocation::spec(pc()); | |
2761 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
2762 assert(!os::is_MP() || | |
2763 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
2764 "must be aligned"); | |
2765 __ call(AddressLiteral(entry, rh)); | |
2766 add_call_info(code_offset(), info); | |
2767 } | |
2768 | |
2769 | |
2770 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
2771 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { | |
2772 ShouldNotReachHere(); | |
2773 } | |
2774 | |
2775 void LIR_Assembler::emit_static_call_stub() { | |
2776 address call_pc = __ pc(); | |
2777 address stub = __ start_a_stub(call_stub_size); | |
2778 if (stub == NULL) { | |
2779 bailout("static call stub overflow"); | |
2780 return; | |
2781 } | |
2782 | |
2783 int start = __ offset(); | |
2784 if (os::is_MP()) { | |
2785 // make sure that the displacement word of the call ends up word aligned | |
2786 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
2787 while (offset++ % BytesPerWord != 0) { | |
2788 __ nop(); | |
2789 } | |
2790 } | |
2791 __ relocate(static_stub_Relocation::spec(call_pc)); | |
2792 __ movoop(rbx, (jobject)NULL); | |
2793 // must be set to -1 at code generation time | |
2794 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
304 | 2795 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
2796 __ jump(RuntimeAddress(__ pc())); | |
0 | 2797 |
2798 assert(__ offset() - start <= call_stub_size, "stub too big") | |
2799 __ end_a_stub(); | |
2800 } | |
2801 | |
2802 | |
2803 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { | |
2804 assert(exceptionOop->as_register() == rax, "must match"); | |
2805 assert(unwind || exceptionPC->as_register() == rdx, "must match"); | |
2806 | |
2807 // exception object is not added to oop map by LinearScan | |
2808 // (LinearScan assumes that no oops are in fixed registers) | |
2809 info->add_register_oop(exceptionOop); | |
2810 Runtime1::StubID unwind_id; | |
2811 | |
2812 if (!unwind) { | |
2813 // get current pc information | |
2814 // pc is only needed if the method has an exception handler, the unwind code does not need it. | |
2815 int pc_for_athrow_offset = __ offset(); | |
2816 InternalAddress pc_for_athrow(__ pc()); | |
2817 __ lea(exceptionPC->as_register(), pc_for_athrow); | |
2818 add_call_info(pc_for_athrow_offset, info); // for exception handler | |
2819 | |
2820 __ verify_not_null_oop(rax); | |
2821 // search an exception handler (rax: exception oop, rdx: throwing pc) | |
2822 if (compilation()->has_fpu_code()) { | |
2823 unwind_id = Runtime1::handle_exception_id; | |
2824 } else { | |
2825 unwind_id = Runtime1::handle_exception_nofpu_id; | |
2826 } | |
2827 } else { | |
2828 unwind_id = Runtime1::unwind_exception_id; | |
2829 } | |
2830 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); | |
2831 | |
2832 // enough room for two byte trap | |
2833 __ nop(); | |
2834 } | |
2835 | |
2836 | |
2837 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
2838 | |
2839 // optimized version for linear scan: | |
2840 // * count must be already in ECX (guaranteed by LinearScan) | |
2841 // * left and dest must be equal | |
2842 // * tmp must be unused | |
2843 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
2844 assert(left == dest, "left and dest must be equal"); | |
2845 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
2846 | |
2847 if (left->is_single_cpu()) { | |
2848 Register value = left->as_register(); | |
2849 assert(value != SHIFT_count, "left cannot be ECX"); | |
2850 | |
2851 switch (code) { | |
2852 case lir_shl: __ shll(value); break; | |
2853 case lir_shr: __ sarl(value); break; | |
2854 case lir_ushr: __ shrl(value); break; | |
2855 default: ShouldNotReachHere(); | |
2856 } | |
2857 } else if (left->is_double_cpu()) { | |
2858 Register lo = left->as_register_lo(); | |
2859 Register hi = left->as_register_hi(); | |
2860 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
304 | 2861 #ifdef _LP64 |
2862 switch (code) { | |
2863 case lir_shl: __ shlptr(lo); break; | |
2864 case lir_shr: __ sarptr(lo); break; | |
2865 case lir_ushr: __ shrptr(lo); break; | |
2866 default: ShouldNotReachHere(); | |
2867 } | |
2868 #else | |
0 | 2869 |
2870 switch (code) { | |
2871 case lir_shl: __ lshl(hi, lo); break; | |
2872 case lir_shr: __ lshr(hi, lo, true); break; | |
2873 case lir_ushr: __ lshr(hi, lo, false); break; | |
2874 default: ShouldNotReachHere(); | |
2875 } | |
304 | 2876 #endif // LP64 |
0 | 2877 } else { |
2878 ShouldNotReachHere(); | |
2879 } | |
2880 } | |
2881 | |
2882 | |
2883 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
2884 if (dest->is_single_cpu()) { | |
2885 // first move left into dest so that left is not destroyed by the shift | |
2886 Register value = dest->as_register(); | |
2887 count = count & 0x1F; // Java spec | |
2888 | |
2889 move_regs(left->as_register(), value); | |
2890 switch (code) { | |
2891 case lir_shl: __ shll(value, count); break; | |
2892 case lir_shr: __ sarl(value, count); break; | |
2893 case lir_ushr: __ shrl(value, count); break; | |
2894 default: ShouldNotReachHere(); | |
2895 } | |
2896 } else if (dest->is_double_cpu()) { | |
304 | 2897 #ifndef _LP64 |
0 | 2898 Unimplemented(); |
304 | 2899 #else |
2900 // first move left into dest so that left is not destroyed by the shift | |
2901 Register value = dest->as_register_lo(); | |
2902 count = count & 0x1F; // Java spec | |
2903 | |
2904 move_regs(left->as_register_lo(), value); | |
2905 switch (code) { | |
2906 case lir_shl: __ shlptr(value, count); break; | |
2907 case lir_shr: __ sarptr(value, count); break; | |
2908 case lir_ushr: __ shrptr(value, count); break; | |
2909 default: ShouldNotReachHere(); | |
2910 } | |
2911 #endif // _LP64 | |
0 | 2912 } else { |
2913 ShouldNotReachHere(); | |
2914 } | |
2915 } | |
2916 | |
2917 | |
2918 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
2919 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
2920 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
2921 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 2922 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
0 | 2923 } |
2924 | |
2925 | |
2926 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
2927 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
2928 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
2929 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 2930 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
0 | 2931 } |
2932 | |
2933 | |
2934 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
2935 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
2936 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
2937 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
2938 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
2939 } | |
2940 | |
2941 | |
2942 // This code replaces a call to arraycopy; no exception may | |
2943 // be thrown in this code, they must be thrown in the System.arraycopy | |
2944 // activation frame; we could save some checks if this would not be the case | |
2945 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
2946 ciArrayKlass* default_type = op->expected_type(); | |
2947 Register src = op->src()->as_register(); | |
2948 Register dst = op->dst()->as_register(); | |
2949 Register src_pos = op->src_pos()->as_register(); | |
2950 Register dst_pos = op->dst_pos()->as_register(); | |
2951 Register length = op->length()->as_register(); | |
2952 Register tmp = op->tmp()->as_register(); | |
2953 | |
2954 CodeStub* stub = op->stub(); | |
2955 int flags = op->flags(); | |
2956 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
2957 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
2958 | |
2959 // if we don't know anything or it's an object array, just go through the generic arraycopy | |
2960 if (default_type == NULL) { | |
2961 Label done; | |
2962 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
2963 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
2964 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
2965 // For the moment until C1 gets the new register allocator I just force all the | |
2966 // args to the right place (except the register args) and then on the back side | |
2967 // reload the register args properly if we go slow path. Yuck | |
2968 | |
2969 // These are proper for the calling convention | |
2970 | |
2971 store_parameter(length, 2); | |
2972 store_parameter(dst_pos, 1); | |
2973 store_parameter(dst, 0); | |
2974 | |
2975 // these are just temporary placements until we need to reload | |
2976 store_parameter(src_pos, 3); | |
2977 store_parameter(src, 4); | |
304 | 2978 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
2979 | |
2980 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); | |
0 | 2981 |
2982 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
304 | 2983 #ifdef _LP64 |
2984 // The arguments are in java calling convention so we can trivially shift them to C | |
2985 // convention | |
2986 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
2987 __ mov(c_rarg0, j_rarg0); | |
2988 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
2989 __ mov(c_rarg1, j_rarg1); | |
2990 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
2991 __ mov(c_rarg2, j_rarg2); | |
2992 assert_different_registers(c_rarg3, j_rarg4); | |
2993 __ mov(c_rarg3, j_rarg3); | |
2994 #ifdef _WIN64 | |
2995 // Allocate abi space for args but be sure to keep stack aligned | |
2996 __ subptr(rsp, 6*wordSize); | |
2997 store_parameter(j_rarg4, 4); | |
2998 __ call(RuntimeAddress(entry)); | |
2999 __ addptr(rsp, 6*wordSize); | |
3000 #else | |
3001 __ mov(c_rarg4, j_rarg4); | |
3002 __ call(RuntimeAddress(entry)); | |
3003 #endif // _WIN64 | |
3004 #else | |
3005 __ push(length); | |
3006 __ push(dst_pos); | |
3007 __ push(dst); | |
3008 __ push(src_pos); | |
3009 __ push(src); | |
0 | 3010 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
3011 | |
304 | 3012 #endif // _LP64 |
3013 | |
0 | 3014 __ cmpl(rax, 0); |
3015 __ jcc(Assembler::equal, *stub->continuation()); | |
3016 | |
3017 // Reload values from the stack so they are where the stub | |
3018 // expects them. | |
304 | 3019 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
3020 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
3021 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
3022 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
3023 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
0 | 3024 __ jmp(*stub->entry()); |
3025 | |
3026 __ bind(*stub->continuation()); | |
3027 return; | |
3028 } | |
3029 | |
3030 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
3031 | |
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diff
changeset
|
3032 int elem_size = type2aelembytes(basic_type); |
0 | 3033 int shift_amount; |
3034 Address::ScaleFactor scale; | |
3035 | |
3036 switch (elem_size) { | |
3037 case 1 : | |
3038 shift_amount = 0; | |
3039 scale = Address::times_1; | |
3040 break; | |
3041 case 2 : | |
3042 shift_amount = 1; | |
3043 scale = Address::times_2; | |
3044 break; | |
3045 case 4 : | |
3046 shift_amount = 2; | |
3047 scale = Address::times_4; | |
3048 break; | |
3049 case 8 : | |
3050 shift_amount = 3; | |
3051 scale = Address::times_8; | |
3052 break; | |
3053 default: | |
3054 ShouldNotReachHere(); | |
3055 } | |
3056 | |
3057 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
3058 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
3059 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
3060 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
3061 | |
304 | 3062 // length and pos's are all sign extended at this point on 64bit |
3063 | |
0 | 3064 // test for NULL |
3065 if (flags & LIR_OpArrayCopy::src_null_check) { | |
304 | 3066 __ testptr(src, src); |
0 | 3067 __ jcc(Assembler::zero, *stub->entry()); |
3068 } | |
3069 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
304 | 3070 __ testptr(dst, dst); |
0 | 3071 __ jcc(Assembler::zero, *stub->entry()); |
3072 } | |
3073 | |
3074 // check if negative | |
3075 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
3076 __ testl(src_pos, src_pos); | |
3077 __ jcc(Assembler::less, *stub->entry()); | |
3078 } | |
3079 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
3080 __ testl(dst_pos, dst_pos); | |
3081 __ jcc(Assembler::less, *stub->entry()); | |
3082 } | |
3083 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
3084 __ testl(length, length); | |
3085 __ jcc(Assembler::less, *stub->entry()); | |
3086 } | |
3087 | |
3088 if (flags & LIR_OpArrayCopy::src_range_check) { | |
304 | 3089 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
0 | 3090 __ cmpl(tmp, src_length_addr); |
3091 __ jcc(Assembler::above, *stub->entry()); | |
3092 } | |
3093 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
304 | 3094 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
0 | 3095 __ cmpl(tmp, dst_length_addr); |
3096 __ jcc(Assembler::above, *stub->entry()); | |
3097 } | |
3098 | |
3099 if (flags & LIR_OpArrayCopy::type_check) { | |
304 | 3100 __ movptr(tmp, src_klass_addr); |
3101 __ cmpptr(tmp, dst_klass_addr); | |
0 | 3102 __ jcc(Assembler::notEqual, *stub->entry()); |
3103 } | |
3104 | |
3105 #ifdef ASSERT | |
3106 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
3107 // Sanity check the known type with the incoming class. For the | |
3108 // primitive case the types must match exactly with src.klass and | |
3109 // dst.klass each exactly matching the default type. For the | |
3110 // object array case, if no type check is needed then either the | |
3111 // dst type is exactly the expected type and the src type is a | |
3112 // subtype which we can't check or src is the same array as dst | |
3113 // but not necessarily exactly of type default_type. | |
3114 Label known_ok, halt; | |
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diff
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|
3115 __ movoop(tmp, default_type->constant_encoding()); |
0 | 3116 if (basic_type != T_OBJECT) { |
304 | 3117 __ cmpptr(tmp, dst_klass_addr); |
0 | 3118 __ jcc(Assembler::notEqual, halt); |
304 | 3119 __ cmpptr(tmp, src_klass_addr); |
0 | 3120 __ jcc(Assembler::equal, known_ok); |
3121 } else { | |
304 | 3122 __ cmpptr(tmp, dst_klass_addr); |
0 | 3123 __ jcc(Assembler::equal, known_ok); |
304 | 3124 __ cmpptr(src, dst); |
0 | 3125 __ jcc(Assembler::equal, known_ok); |
3126 } | |
3127 __ bind(halt); | |
3128 __ stop("incorrect type information in arraycopy"); | |
3129 __ bind(known_ok); | |
3130 } | |
3131 #endif | |
3132 | |
304 | 3133 if (shift_amount > 0 && basic_type != T_OBJECT) { |
3134 __ shlptr(length, shift_amount); | |
3135 } | |
3136 | |
3137 #ifdef _LP64 | |
3138 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
3139 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3140 assert_different_registers(c_rarg1, length); | |
3141 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3142 __ mov(c_rarg2, length); | |
3143 | |
3144 #else | |
3145 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
0 | 3146 store_parameter(tmp, 0); |
304 | 3147 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
0 | 3148 store_parameter(tmp, 1); |
3149 store_parameter(length, 2); | |
304 | 3150 #endif // _LP64 |
0 | 3151 if (basic_type == T_OBJECT) { |
3152 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); | |
3153 } else { | |
3154 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); | |
3155 } | |
3156 | |
3157 __ bind(*stub->continuation()); | |
3158 } | |
3159 | |
3160 | |
3161 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
3162 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
3163 Register hdr = op->hdr_opr()->as_register(); | |
3164 Register lock = op->lock_opr()->as_register(); | |
3165 if (!UseFastLocking) { | |
3166 __ jmp(*op->stub()->entry()); | |
3167 } else if (op->code() == lir_lock) { | |
3168 Register scratch = noreg; | |
3169 if (UseBiasedLocking) { | |
3170 scratch = op->scratch_opr()->as_register(); | |
3171 } | |
3172 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3173 // add debug info for NullPointerException only if one is possible | |
3174 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
3175 if (op->info() != NULL) { | |
3176 add_debug_info_for_null_check(null_check_offset, op->info()); | |
3177 } | |
3178 // done | |
3179 } else if (op->code() == lir_unlock) { | |
3180 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3181 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
3182 } else { | |
3183 Unimplemented(); | |
3184 } | |
3185 __ bind(*op->stub()->continuation()); | |
3186 } | |
3187 | |
3188 | |
3189 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
3190 ciMethod* method = op->profiled_method(); | |
3191 int bci = op->profiled_bci(); | |
3192 | |
3193 // Update counter for all call types | |
3194 ciMethodData* md = method->method_data(); | |
3195 if (md == NULL) { | |
3196 bailout("out of memory building methodDataOop"); | |
3197 return; | |
3198 } | |
3199 ciProfileData* data = md->bci_to_data(bci); | |
3200 assert(data->is_CounterData(), "need CounterData for calls"); | |
3201 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
3202 Register mdo = op->mdo()->as_register(); | |
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|
3203 __ movoop(mdo, md->constant_encoding()); |
0 | 3204 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
3205 __ addl(counter_addr, DataLayout::counter_increment); | |
3206 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
3207 // Perform additional virtual call profiling for invokevirtual and | |
3208 // invokeinterface bytecodes | |
3209 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
3210 Tier1ProfileVirtualCalls) { | |
3211 assert(op->recv()->is_single_cpu(), "recv must be allocated"); | |
3212 Register recv = op->recv()->as_register(); | |
3213 assert_different_registers(mdo, recv); | |
3214 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3215 ciKlass* known_klass = op->known_holder(); | |
3216 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { | |
3217 // We know the type that will be seen at this call site; we can | |
3218 // statically update the methodDataOop rather than needing to do | |
3219 // dynamic tests on the receiver type | |
3220 | |
3221 // NOTE: we should probably put a lock around this search to | |
3222 // avoid collisions by concurrent compilations | |
3223 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3224 uint i; | |
3225 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3226 ciKlass* receiver = vc_data->receiver(i); | |
3227 if (known_klass->equals(receiver)) { | |
3228 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
3229 __ addl(data_addr, DataLayout::counter_increment); | |
3230 return; | |
3231 } | |
3232 } | |
3233 | |
3234 // Receiver type not found in profile data; select an empty slot | |
3235 | |
3236 // Note that this is less efficient than it should be because it | |
3237 // always does a write to the receiver part of the | |
3238 // VirtualCallData rather than just the first time | |
3239 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3240 ciKlass* receiver = vc_data->receiver(i); | |
3241 if (receiver == NULL) { | |
3242 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
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diff
changeset
|
3243 __ movoop(recv_addr, known_klass->constant_encoding()); |
0 | 3244 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
3245 __ addl(data_addr, DataLayout::counter_increment); | |
3246 return; | |
3247 } | |
3248 } | |
3249 } else { | |
304 | 3250 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
0 | 3251 Label update_done; |
3252 uint i; | |
3253 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3254 Label next_test; | |
3255 // See if the receiver is receiver[n]. | |
304 | 3256 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); |
0 | 3257 __ jcc(Assembler::notEqual, next_test); |
3258 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
3259 __ addl(data_addr, DataLayout::counter_increment); | |
3260 __ jmp(update_done); | |
3261 __ bind(next_test); | |
3262 } | |
3263 | |
3264 // Didn't find receiver; find next empty slot and fill it in | |
3265 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3266 Label next_test; | |
3267 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
304 | 3268 __ cmpptr(recv_addr, (int32_t)NULL_WORD); |
0 | 3269 __ jcc(Assembler::notEqual, next_test); |
304 | 3270 __ movptr(recv_addr, recv); |
0 | 3271 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); |
3272 if (i < (VirtualCallData::row_limit() - 1)) { | |
3273 __ jmp(update_done); | |
3274 } | |
3275 __ bind(next_test); | |
3276 } | |
3277 | |
3278 __ bind(update_done); | |
3279 } | |
3280 } | |
3281 } | |
3282 | |
3283 | |
3284 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
3285 Unimplemented(); | |
3286 } | |
3287 | |
3288 | |
3289 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
304 | 3290 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
0 | 3291 } |
3292 | |
3293 | |
3294 void LIR_Assembler::align_backward_branch_target() { | |
3295 __ align(BytesPerWord); | |
3296 } | |
3297 | |
3298 | |
3299 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3300 if (left->is_single_cpu()) { | |
3301 __ negl(left->as_register()); | |
3302 move_regs(left->as_register(), dest->as_register()); | |
3303 | |
3304 } else if (left->is_double_cpu()) { | |
3305 Register lo = left->as_register_lo(); | |
304 | 3306 #ifdef _LP64 |
3307 Register dst = dest->as_register_lo(); | |
3308 __ movptr(dst, lo); | |
3309 __ negptr(dst); | |
3310 #else | |
0 | 3311 Register hi = left->as_register_hi(); |
3312 __ lneg(hi, lo); | |
3313 if (dest->as_register_lo() == hi) { | |
3314 assert(dest->as_register_hi() != lo, "destroying register"); | |
3315 move_regs(hi, dest->as_register_hi()); | |
3316 move_regs(lo, dest->as_register_lo()); | |
3317 } else { | |
3318 move_regs(lo, dest->as_register_lo()); | |
3319 move_regs(hi, dest->as_register_hi()); | |
3320 } | |
304 | 3321 #endif // _LP64 |
0 | 3322 |
3323 } else if (dest->is_single_xmm()) { | |
3324 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
3325 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
3326 } | |
3327 __ xorps(dest->as_xmm_float_reg(), | |
3328 ExternalAddress((address)float_signflip_pool)); | |
3329 | |
3330 } else if (dest->is_double_xmm()) { | |
3331 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
3332 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
3333 } | |
3334 __ xorpd(dest->as_xmm_double_reg(), | |
3335 ExternalAddress((address)double_signflip_pool)); | |
3336 | |
3337 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
3338 assert(left->fpu() == 0, "arg must be on TOS"); | |
3339 assert(dest->fpu() == 0, "dest must be TOS"); | |
3340 __ fchs(); | |
3341 | |
3342 } else { | |
3343 ShouldNotReachHere(); | |
3344 } | |
3345 } | |
3346 | |
3347 | |
3348 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
3349 assert(addr->is_address() && dest->is_register(), "check"); | |
304 | 3350 Register reg; |
3351 reg = dest->as_pointer_register(); | |
3352 __ lea(reg, as_Address(addr->as_address_ptr())); | |
0 | 3353 } |
3354 | |
3355 | |
3356 | |
3357 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3358 assert(!tmp->is_valid(), "don't need temporary"); | |
3359 __ call(RuntimeAddress(dest)); | |
3360 if (info != NULL) { | |
3361 add_call_info_here(info); | |
3362 } | |
3363 } | |
3364 | |
3365 | |
3366 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3367 assert(type == T_LONG, "only for volatile long fields"); | |
3368 | |
3369 if (info != NULL) { | |
3370 add_debug_info_for_null_check_here(info); | |
3371 } | |
3372 | |
3373 if (src->is_double_xmm()) { | |
3374 if (dest->is_double_cpu()) { | |
304 | 3375 #ifdef _LP64 |
3376 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
3377 #else | |
3378 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
0 | 3379 __ psrlq(src->as_xmm_double_reg(), 32); |
304 | 3380 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
3381 #endif // _LP64 | |
0 | 3382 } else if (dest->is_double_stack()) { |
3383 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
3384 } else if (dest->is_address()) { | |
3385 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
3386 } else { | |
3387 ShouldNotReachHere(); | |
3388 } | |
3389 | |
3390 } else if (dest->is_double_xmm()) { | |
3391 if (src->is_double_stack()) { | |
3392 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
3393 } else if (src->is_address()) { | |
3394 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
3395 } else { | |
3396 ShouldNotReachHere(); | |
3397 } | |
3398 | |
3399 } else if (src->is_double_fpu()) { | |
3400 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
3401 if (dest->is_double_stack()) { | |
3402 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
3403 } else if (dest->is_address()) { | |
3404 __ fistp_d(as_Address(dest->as_address_ptr())); | |
3405 } else { | |
3406 ShouldNotReachHere(); | |
3407 } | |
3408 | |
3409 } else if (dest->is_double_fpu()) { | |
3410 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
3411 if (src->is_double_stack()) { | |
3412 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
3413 } else if (src->is_address()) { | |
3414 __ fild_d(as_Address(src->as_address_ptr())); | |
3415 } else { | |
3416 ShouldNotReachHere(); | |
3417 } | |
3418 } else { | |
3419 ShouldNotReachHere(); | |
3420 } | |
3421 } | |
3422 | |
3423 | |
3424 void LIR_Assembler::membar() { | |
304 | 3425 // QQQ sparc TSO uses this, |
3426 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
0 | 3427 } |
3428 | |
3429 void LIR_Assembler::membar_acquire() { | |
3430 // No x86 machines currently require load fences | |
3431 // __ load_fence(); | |
3432 } | |
3433 | |
3434 void LIR_Assembler::membar_release() { | |
3435 // No x86 machines currently require store fences | |
3436 // __ store_fence(); | |
3437 } | |
3438 | |
3439 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
3440 assert(result_reg->is_register(), "check"); | |
304 | 3441 #ifdef _LP64 |
3442 // __ get_thread(result_reg->as_register_lo()); | |
3443 __ mov(result_reg->as_register(), r15_thread); | |
3444 #else | |
0 | 3445 __ get_thread(result_reg->as_register()); |
304 | 3446 #endif // _LP64 |
0 | 3447 } |
3448 | |
3449 | |
3450 void LIR_Assembler::peephole(LIR_List*) { | |
3451 // do nothing for now | |
3452 } | |
3453 | |
3454 | |
3455 #undef __ |