Mercurial > hg > truffle
annotate src/cpu/x86/vm/macroAssembler_x86.cpp @ 17877:17b2fbdb6637
8038297: Avoid placing CTI immediately following cbcond instruction on T4
Summary: Insert a nop between cbcond and CTI
Reviewed-by: kvn, twisti
author | iveresov |
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date | Thu, 10 Apr 2014 23:15:13 -0700 |
parents | 526acaf3626f |
children | 400709e275c1 |
rev | line source |
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7199 | 1 /* |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
7199 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |
20 * or visit www.oracle.com if you need additional information or have any | |
21 * questions. | |
22 * | |
23 */ | |
24 | |
25 #include "precompiled.hpp" | |
26 #include "asm/assembler.hpp" | |
27 #include "asm/assembler.inline.hpp" | |
28 #include "compiler/disassembler.hpp" | |
29 #include "gc_interface/collectedHeap.inline.hpp" | |
30 #include "interpreter/interpreter.hpp" | |
31 #include "memory/cardTableModRefBS.hpp" | |
32 #include "memory/resourceArea.hpp" | |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
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33 #include "memory/universe.hpp" |
7199 | 34 #include "prims/methodHandles.hpp" |
35 #include "runtime/biasedLocking.hpp" | |
36 #include "runtime/interfaceSupport.hpp" | |
37 #include "runtime/objectMonitor.hpp" | |
38 #include "runtime/os.hpp" | |
39 #include "runtime/sharedRuntime.hpp" | |
40 #include "runtime/stubRoutines.hpp" | |
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8005915: Unify SERIALGC and INCLUDE_ALTERNATE_GCS
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41 #include "utilities/macros.hpp" |
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8005915: Unify SERIALGC and INCLUDE_ALTERNATE_GCS
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42 #if INCLUDE_ALL_GCS |
7199 | 43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" |
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
45 #include "gc_implementation/g1/heapRegion.hpp" | |
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46 #endif // INCLUDE_ALL_GCS |
7199 | 47 |
48 #ifdef PRODUCT | |
49 #define BLOCK_COMMENT(str) /* nothing */ | |
50 #define STOP(error) stop(error) | |
51 #else | |
52 #define BLOCK_COMMENT(str) block_comment(str) | |
53 #define STOP(error) block_comment(error); stop(error) | |
54 #endif | |
55 | |
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
57 | |
58 | |
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8003250: SPARC: move MacroAssembler into separate file
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59 #ifdef ASSERT |
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60 bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
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61 #endif |
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8003250: SPARC: move MacroAssembler into separate file
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62 |
7199 | 63 static Assembler::Condition reverse[] = { |
64 Assembler::noOverflow /* overflow = 0x0 */ , | |
65 Assembler::overflow /* noOverflow = 0x1 */ , | |
66 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
67 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
68 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
69 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
70 Assembler::above /* belowEqual = 0x6 */ , | |
71 Assembler::belowEqual /* above = 0x7 */ , | |
72 Assembler::positive /* negative = 0x8 */ , | |
73 Assembler::negative /* positive = 0x9 */ , | |
74 Assembler::noParity /* parity = 0xa */ , | |
75 Assembler::parity /* noParity = 0xb */ , | |
76 Assembler::greaterEqual /* less = 0xc */ , | |
77 Assembler::less /* greaterEqual = 0xd */ , | |
78 Assembler::greater /* lessEqual = 0xe */ , | |
79 Assembler::lessEqual /* greater = 0xf, */ | |
80 | |
81 }; | |
82 | |
83 | |
84 // Implementation of MacroAssembler | |
85 | |
86 // First all the versions that have distinct versions depending on 32/64 bit | |
87 // Unless the difference is trivial (1 line or so). | |
88 | |
89 #ifndef _LP64 | |
90 | |
91 // 32bit versions | |
92 | |
93 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
94 return Address(adr.target(), adr.rspec()); | |
95 } | |
96 | |
97 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
98 return Address::make_array(adr); | |
99 } | |
100 | |
101 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
102 int number_of_arguments) { | |
103 call(RuntimeAddress(entry_point)); | |
104 increment(rsp, number_of_arguments * wordSize); | |
105 } | |
106 | |
107 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { | |
108 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); | |
109 } | |
110 | |
111 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { | |
112 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); | |
113 } | |
114 | |
115 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
116 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
117 } | |
118 | |
119 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
120 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
121 } | |
122 | |
123 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
124 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
125 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
126 cdql(); | |
127 } else { | |
128 movl(hi, lo); | |
129 sarl(hi, 31); | |
130 } | |
131 } | |
132 | |
133 void MacroAssembler::jC2(Register tmp, Label& L) { | |
134 // set parity bit if FPU flag C2 is set (via rax) | |
135 save_rax(tmp); | |
136 fwait(); fnstsw_ax(); | |
137 sahf(); | |
138 restore_rax(tmp); | |
139 // branch | |
140 jcc(Assembler::parity, L); | |
141 } | |
142 | |
143 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
144 // set parity bit if FPU flag C2 is set (via rax) | |
145 save_rax(tmp); | |
146 fwait(); fnstsw_ax(); | |
147 sahf(); | |
148 restore_rax(tmp); | |
149 // branch | |
150 jcc(Assembler::noParity, L); | |
151 } | |
152 | |
153 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
154 // to be installed in the Address class | |
155 void MacroAssembler::jump(ArrayAddress entry) { | |
156 jmp(as_Address(entry)); | |
157 } | |
158 | |
159 // Note: y_lo will be destroyed | |
160 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
161 // Long compare for Java (semantics as described in JVM spec.) | |
162 Label high, low, done; | |
163 | |
164 cmpl(x_hi, y_hi); | |
165 jcc(Assembler::less, low); | |
166 jcc(Assembler::greater, high); | |
167 // x_hi is the return register | |
168 xorl(x_hi, x_hi); | |
169 cmpl(x_lo, y_lo); | |
170 jcc(Assembler::below, low); | |
171 jcc(Assembler::equal, done); | |
172 | |
173 bind(high); | |
174 xorl(x_hi, x_hi); | |
175 increment(x_hi); | |
176 jmp(done); | |
177 | |
178 bind(low); | |
179 xorl(x_hi, x_hi); | |
180 decrementl(x_hi); | |
181 | |
182 bind(done); | |
183 } | |
184 | |
185 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
186 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
187 } | |
188 | |
189 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
190 // leal(dst, as_Address(adr)); | |
191 // see note in movl as to why we must use a move | |
192 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); | |
193 } | |
194 | |
195 void MacroAssembler::leave() { | |
196 mov(rsp, rbp); | |
197 pop(rbp); | |
198 } | |
199 | |
200 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
201 // Multiplication of two Java long values stored on the stack | |
202 // as illustrated below. Result is in rdx:rax. | |
203 // | |
204 // rsp ---> [ ?? ] \ \ | |
205 // .... | y_rsp_offset | | |
206 // [ y_lo ] / (in bytes) | x_rsp_offset | |
207 // [ y_hi ] | (in bytes) | |
208 // .... | | |
209 // [ x_lo ] / | |
210 // [ x_hi ] | |
211 // .... | |
212 // | |
213 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
214 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
215 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
216 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
217 Label quick; | |
218 // load x_hi, y_hi and check if quick | |
219 // multiplication is possible | |
220 movl(rbx, x_hi); | |
221 movl(rcx, y_hi); | |
222 movl(rax, rbx); | |
223 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
224 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
225 // do full multiplication | |
226 // 1st step | |
227 mull(y_lo); // x_hi * y_lo | |
228 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
229 // 2nd step | |
230 movl(rax, x_lo); | |
231 mull(rcx); // x_lo * y_hi | |
232 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
233 // 3rd step | |
234 bind(quick); // note: rbx, = 0 if quick multiply! | |
235 movl(rax, x_lo); | |
236 mull(y_lo); // x_lo * y_lo | |
237 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
238 } | |
239 | |
240 void MacroAssembler::lneg(Register hi, Register lo) { | |
241 negl(lo); | |
242 adcl(hi, 0); | |
243 negl(hi); | |
244 } | |
245 | |
246 void MacroAssembler::lshl(Register hi, Register lo) { | |
247 // Java shift left long support (semantics as described in JVM spec., p.305) | |
248 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
249 // shift value is in rcx ! | |
250 assert(hi != rcx, "must not use rcx"); | |
251 assert(lo != rcx, "must not use rcx"); | |
252 const Register s = rcx; // shift count | |
253 const int n = BitsPerWord; | |
254 Label L; | |
255 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
256 cmpl(s, n); // if (s < n) | |
257 jcc(Assembler::less, L); // else (s >= n) | |
258 movl(hi, lo); // x := x << n | |
259 xorl(lo, lo); | |
260 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
261 bind(L); // s (mod n) < n | |
262 shldl(hi, lo); // x := x << s | |
263 shll(lo); | |
264 } | |
265 | |
266 | |
267 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
268 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
269 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
270 assert(hi != rcx, "must not use rcx"); | |
271 assert(lo != rcx, "must not use rcx"); | |
272 const Register s = rcx; // shift count | |
273 const int n = BitsPerWord; | |
274 Label L; | |
275 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
276 cmpl(s, n); // if (s < n) | |
277 jcc(Assembler::less, L); // else (s >= n) | |
278 movl(lo, hi); // x := x >> n | |
279 if (sign_extension) sarl(hi, 31); | |
280 else xorl(hi, hi); | |
281 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
282 bind(L); // s (mod n) < n | |
283 shrdl(lo, hi); // x := x >> s | |
284 if (sign_extension) sarl(hi); | |
285 else shrl(hi); | |
286 } | |
287 | |
288 void MacroAssembler::movoop(Register dst, jobject obj) { | |
289 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
290 } | |
291 | |
292 void MacroAssembler::movoop(Address dst, jobject obj) { | |
293 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
294 } | |
295 | |
296 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { | |
297 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); | |
298 } | |
299 | |
300 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { | |
301 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); | |
302 } | |
303 | |
17780 | 304 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { |
305 // scratch register is not used, | |
306 // it is defined to match parameters of 64-bit version of this method. | |
7199 | 307 if (src.is_lval()) { |
308 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
309 } else { | |
310 movl(dst, as_Address(src)); | |
311 } | |
312 } | |
313 | |
314 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
315 movl(as_Address(dst), src); | |
316 } | |
317 | |
318 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
319 movl(dst, as_Address(src)); | |
320 } | |
321 | |
322 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
323 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
324 movl(dst, src); | |
325 } | |
326 | |
327 | |
328 void MacroAssembler::pop_callee_saved_registers() { | |
329 pop(rcx); | |
330 pop(rdx); | |
331 pop(rdi); | |
332 pop(rsi); | |
333 } | |
334 | |
335 void MacroAssembler::pop_fTOS() { | |
336 fld_d(Address(rsp, 0)); | |
337 addl(rsp, 2 * wordSize); | |
338 } | |
339 | |
340 void MacroAssembler::push_callee_saved_registers() { | |
341 push(rsi); | |
342 push(rdi); | |
343 push(rdx); | |
344 push(rcx); | |
345 } | |
346 | |
347 void MacroAssembler::push_fTOS() { | |
348 subl(rsp, 2 * wordSize); | |
349 fstp_d(Address(rsp, 0)); | |
350 } | |
351 | |
352 | |
353 void MacroAssembler::pushoop(jobject obj) { | |
354 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
355 } | |
356 | |
357 void MacroAssembler::pushklass(Metadata* obj) { | |
358 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); | |
359 } | |
360 | |
361 void MacroAssembler::pushptr(AddressLiteral src) { | |
362 if (src.is_lval()) { | |
363 push_literal32((int32_t)src.target(), src.rspec()); | |
364 } else { | |
365 pushl(as_Address(src)); | |
366 } | |
367 } | |
368 | |
369 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
370 xorl(dst, dst); | |
371 set_byte_if_not_zero(dst); | |
372 } | |
373 | |
374 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
375 masm->push(arg); | |
376 } | |
377 | |
378 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
379 masm->push(arg); | |
380 } | |
381 | |
382 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
383 masm->push(arg); | |
384 } | |
385 | |
386 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
387 masm->push(arg); | |
388 } | |
389 | |
390 #ifndef PRODUCT | |
391 extern "C" void findpc(intptr_t x); | |
392 #endif | |
393 | |
394 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
395 // In order to get locks to work, we need to fake a in_VM state | |
396 JavaThread* thread = JavaThread::current(); | |
397 JavaThreadState saved_state = thread->thread_state(); | |
398 thread->set_thread_state(_thread_in_vm); | |
399 if (ShowMessageBoxOnError) { | |
400 JavaThread* thread = JavaThread::current(); | |
401 JavaThreadState saved_state = thread->thread_state(); | |
402 thread->set_thread_state(_thread_in_vm); | |
403 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
404 ttyLocker ttyl; | |
405 BytecodeCounter::print(); | |
406 } | |
407 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
408 // This is the value of eip which points to where verify_oop will return. | |
409 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
410 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); | |
411 BREAKPOINT; | |
412 } | |
413 } else { | |
414 ttyLocker ttyl; | |
415 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
416 } | |
417 // Don't assert holding the ttyLock | |
418 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); | |
419 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
420 } | |
421 | |
422 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { | |
423 ttyLocker ttyl; | |
424 FlagSetting fs(Debugging, true); | |
425 tty->print_cr("eip = 0x%08x", eip); | |
426 #ifndef PRODUCT | |
427 if ((WizardMode || Verbose) && PrintMiscellaneous) { | |
428 tty->cr(); | |
429 findpc(eip); | |
430 tty->cr(); | |
431 } | |
432 #endif | |
433 #define PRINT_REG(rax) \ | |
434 { tty->print("%s = ", #rax); os::print_location(tty, rax); } | |
435 PRINT_REG(rax); | |
436 PRINT_REG(rbx); | |
437 PRINT_REG(rcx); | |
438 PRINT_REG(rdx); | |
439 PRINT_REG(rdi); | |
440 PRINT_REG(rsi); | |
441 PRINT_REG(rbp); | |
442 PRINT_REG(rsp); | |
443 #undef PRINT_REG | |
444 // Print some words near top of staack. | |
445 int* dump_sp = (int*) rsp; | |
446 for (int col1 = 0; col1 < 8; col1++) { | |
447 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); | |
448 os::print_location(tty, *dump_sp++); | |
449 } | |
450 for (int row = 0; row < 16; row++) { | |
451 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); | |
452 for (int col = 0; col < 8; col++) { | |
453 tty->print(" 0x%08x", *dump_sp++); | |
454 } | |
455 tty->cr(); | |
456 } | |
457 // Print some instructions around pc: | |
458 Disassembler::decode((address)eip-64, (address)eip); | |
459 tty->print_cr("--------"); | |
460 Disassembler::decode((address)eip, (address)eip+32); | |
461 } | |
462 | |
463 void MacroAssembler::stop(const char* msg) { | |
464 ExternalAddress message((address)msg); | |
465 // push address of message | |
466 pushptr(message.addr()); | |
467 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
468 pusha(); // push registers | |
469 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
470 hlt(); | |
471 } | |
472 | |
473 void MacroAssembler::warn(const char* msg) { | |
474 push_CPU_state(); | |
475 | |
476 ExternalAddress message((address) msg); | |
477 // push address of message | |
478 pushptr(message.addr()); | |
479 | |
480 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
481 addl(rsp, wordSize); // discard argument | |
482 pop_CPU_state(); | |
483 } | |
484 | |
485 void MacroAssembler::print_state() { | |
486 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
487 pusha(); // push registers | |
488 | |
489 push_CPU_state(); | |
490 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); | |
491 pop_CPU_state(); | |
492 | |
493 popa(); | |
494 addl(rsp, wordSize); | |
495 } | |
496 | |
497 #else // _LP64 | |
498 | |
499 // 64 bit versions | |
500 | |
501 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
502 // amd64 always does this as a pc-rel | |
503 // we can be absolute or disp based on the instruction type | |
504 // jmp/call are displacements others are absolute | |
505 assert(!adr.is_lval(), "must be rval"); | |
506 assert(reachable(adr), "must be"); | |
507 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
508 | |
509 } | |
510 | |
511 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
512 AddressLiteral base = adr.base(); | |
513 lea(rscratch1, base); | |
514 Address index = adr.index(); | |
515 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
516 Address array(rscratch1, index._index, index._scale, index._disp); | |
517 return array; | |
518 } | |
519 | |
520 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
521 Label L, E; | |
522 | |
523 #ifdef _WIN64 | |
524 // Windows always allocates space for it's register args | |
525 assert(num_args <= 4, "only register arguments supported"); | |
526 subq(rsp, frame::arg_reg_save_area_bytes); | |
527 #endif | |
528 | |
529 // Align stack if necessary | |
530 testl(rsp, 15); | |
531 jcc(Assembler::zero, L); | |
532 | |
533 subq(rsp, 8); | |
534 { | |
535 call(RuntimeAddress(entry_point)); | |
536 } | |
537 addq(rsp, 8); | |
538 jmp(E); | |
539 | |
540 bind(L); | |
541 { | |
542 call(RuntimeAddress(entry_point)); | |
543 } | |
544 | |
545 bind(E); | |
546 | |
547 #ifdef _WIN64 | |
548 // restore stack pointer | |
549 addq(rsp, frame::arg_reg_save_area_bytes); | |
550 #endif | |
551 | |
552 } | |
553 | |
554 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
555 assert(!src2.is_lval(), "should use cmpptr"); | |
556 | |
557 if (reachable(src2)) { | |
558 cmpq(src1, as_Address(src2)); | |
559 } else { | |
560 lea(rscratch1, src2); | |
561 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
562 } | |
563 } | |
564 | |
565 int MacroAssembler::corrected_idivq(Register reg) { | |
566 // Full implementation of Java ldiv and lrem; checks for special | |
567 // case as described in JVM spec., p.243 & p.271. The function | |
568 // returns the (pc) offset of the idivl instruction - may be needed | |
569 // for implicit exceptions. | |
570 // | |
571 // normal case special case | |
572 // | |
573 // input : rax: dividend min_long | |
574 // reg: divisor (may not be eax/edx) -1 | |
575 // | |
576 // output: rax: quotient (= rax idiv reg) min_long | |
577 // rdx: remainder (= rax irem reg) 0 | |
578 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
579 static const int64_t min_long = 0x8000000000000000; | |
580 Label normal_case, special_case; | |
581 | |
582 // check for special case | |
583 cmp64(rax, ExternalAddress((address) &min_long)); | |
584 jcc(Assembler::notEqual, normal_case); | |
585 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
586 // remainder = 0) | |
587 cmpq(reg, -1); | |
588 jcc(Assembler::equal, special_case); | |
589 | |
590 // handle normal case | |
591 bind(normal_case); | |
592 cdqq(); | |
593 int idivq_offset = offset(); | |
594 idivq(reg); | |
595 | |
596 // normal and special case exit | |
597 bind(special_case); | |
598 | |
599 return idivq_offset; | |
600 } | |
601 | |
602 void MacroAssembler::decrementq(Register reg, int value) { | |
603 if (value == min_jint) { subq(reg, value); return; } | |
604 if (value < 0) { incrementq(reg, -value); return; } | |
605 if (value == 0) { ; return; } | |
606 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
607 /* else */ { subq(reg, value) ; return; } | |
608 } | |
609 | |
610 void MacroAssembler::decrementq(Address dst, int value) { | |
611 if (value == min_jint) { subq(dst, value); return; } | |
612 if (value < 0) { incrementq(dst, -value); return; } | |
613 if (value == 0) { ; return; } | |
614 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
615 /* else */ { subq(dst, value) ; return; } | |
616 } | |
617 | |
17780 | 618 void MacroAssembler::incrementq(AddressLiteral dst) { |
619 if (reachable(dst)) { | |
620 incrementq(as_Address(dst)); | |
621 } else { | |
622 lea(rscratch1, dst); | |
623 incrementq(Address(rscratch1, 0)); | |
624 } | |
625 } | |
626 | |
7199 | 627 void MacroAssembler::incrementq(Register reg, int value) { |
628 if (value == min_jint) { addq(reg, value); return; } | |
629 if (value < 0) { decrementq(reg, -value); return; } | |
630 if (value == 0) { ; return; } | |
631 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
632 /* else */ { addq(reg, value) ; return; } | |
633 } | |
634 | |
635 void MacroAssembler::incrementq(Address dst, int value) { | |
636 if (value == min_jint) { addq(dst, value); return; } | |
637 if (value < 0) { decrementq(dst, -value); return; } | |
638 if (value == 0) { ; return; } | |
639 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
640 /* else */ { addq(dst, value) ; return; } | |
641 } | |
642 | |
643 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
644 // to be installed in the Address class | |
645 void MacroAssembler::jump(ArrayAddress entry) { | |
646 lea(rscratch1, entry.base()); | |
647 Address dispatch = entry.index(); | |
648 assert(dispatch._base == noreg, "must be"); | |
649 dispatch._base = rscratch1; | |
650 jmp(dispatch); | |
651 } | |
652 | |
653 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
654 ShouldNotReachHere(); // 64bit doesn't use two regs | |
655 cmpq(x_lo, y_lo); | |
656 } | |
657 | |
658 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
659 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
660 } | |
661 | |
662 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
663 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
664 movptr(dst, rscratch1); | |
665 } | |
666 | |
667 void MacroAssembler::leave() { | |
668 // %%% is this really better? Why not on 32bit too? | |
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669 emit_int8((unsigned char)0xC9); // LEAVE |
7199 | 670 } |
671 | |
672 void MacroAssembler::lneg(Register hi, Register lo) { | |
673 ShouldNotReachHere(); // 64bit doesn't use two regs | |
674 negq(lo); | |
675 } | |
676 | |
677 void MacroAssembler::movoop(Register dst, jobject obj) { | |
678 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
679 } | |
680 | |
681 void MacroAssembler::movoop(Address dst, jobject obj) { | |
682 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
683 movq(dst, rscratch1); | |
684 } | |
685 | |
686 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { | |
687 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); | |
688 } | |
689 | |
690 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { | |
691 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); | |
692 movq(dst, rscratch1); | |
693 } | |
694 | |
17780 | 695 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { |
7199 | 696 if (src.is_lval()) { |
697 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
698 } else { | |
699 if (reachable(src)) { | |
700 movq(dst, as_Address(src)); | |
701 } else { | |
17780 | 702 lea(scratch, src); |
703 movq(dst, Address(scratch, 0)); | |
7199 | 704 } |
705 } | |
706 } | |
707 | |
708 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
709 movq(as_Address(dst), src); | |
710 } | |
711 | |
712 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
713 movq(dst, as_Address(src)); | |
714 } | |
715 | |
716 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
717 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
718 mov64(rscratch1, src); | |
719 movq(dst, rscratch1); | |
720 } | |
721 | |
722 // These are mostly for initializing NULL | |
723 void MacroAssembler::movptr(Address dst, int32_t src) { | |
724 movslq(dst, src); | |
725 } | |
726 | |
727 void MacroAssembler::movptr(Register dst, int32_t src) { | |
728 mov64(dst, (intptr_t)src); | |
729 } | |
730 | |
731 void MacroAssembler::pushoop(jobject obj) { | |
732 movoop(rscratch1, obj); | |
733 push(rscratch1); | |
734 } | |
735 | |
736 void MacroAssembler::pushklass(Metadata* obj) { | |
737 mov_metadata(rscratch1, obj); | |
738 push(rscratch1); | |
739 } | |
740 | |
741 void MacroAssembler::pushptr(AddressLiteral src) { | |
742 lea(rscratch1, src); | |
743 if (src.is_lval()) { | |
744 push(rscratch1); | |
745 } else { | |
746 pushq(Address(rscratch1, 0)); | |
747 } | |
748 } | |
749 | |
750 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
751 bool clear_pc) { | |
752 // we must set sp to zero to clear frame | |
753 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); | |
754 // must clear fp, so that compiled frames are not confused; it is | |
755 // possible that we need it only for debugging | |
756 if (clear_fp) { | |
757 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); | |
758 } | |
759 | |
760 if (clear_pc) { | |
761 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); | |
762 } | |
763 } | |
764 | |
765 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
766 Register last_java_fp, | |
767 address last_java_pc) { | |
768 // determine last_java_sp register | |
769 if (!last_java_sp->is_valid()) { | |
770 last_java_sp = rsp; | |
771 } | |
772 | |
773 // last_java_fp is optional | |
774 if (last_java_fp->is_valid()) { | |
775 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
776 last_java_fp); | |
777 } | |
778 | |
779 // last_java_pc is optional | |
780 if (last_java_pc != NULL) { | |
781 Address java_pc(r15_thread, | |
782 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
783 lea(rscratch1, InternalAddress(last_java_pc)); | |
784 movptr(java_pc, rscratch1); | |
785 } | |
786 | |
787 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
788 } | |
789 | |
790 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
791 if (c_rarg0 != arg ) { | |
792 masm->mov(c_rarg0, arg); | |
793 } | |
794 } | |
795 | |
796 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
797 if (c_rarg1 != arg ) { | |
798 masm->mov(c_rarg1, arg); | |
799 } | |
800 } | |
801 | |
802 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
803 if (c_rarg2 != arg ) { | |
804 masm->mov(c_rarg2, arg); | |
805 } | |
806 } | |
807 | |
808 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
809 if (c_rarg3 != arg ) { | |
810 masm->mov(c_rarg3, arg); | |
811 } | |
812 } | |
813 | |
814 void MacroAssembler::stop(const char* msg) { | |
815 address rip = pc(); | |
816 pusha(); // get regs on stack | |
817 lea(c_rarg0, ExternalAddress((address) msg)); | |
818 lea(c_rarg1, InternalAddress(rip)); | |
819 movq(c_rarg2, rsp); // pass pointer to regs array | |
820 andq(rsp, -16); // align stack as required by ABI | |
821 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
822 hlt(); | |
823 } | |
824 | |
825 void MacroAssembler::warn(const char* msg) { | |
826 push(rbp); | |
827 movq(rbp, rsp); | |
828 andq(rsp, -16); // align stack as required by push_CPU_state and call | |
829 push_CPU_state(); // keeps alignment at 16 bytes | |
830 lea(c_rarg0, ExternalAddress((address) msg)); | |
831 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
832 pop_CPU_state(); | |
833 mov(rsp, rbp); | |
834 pop(rbp); | |
835 } | |
836 | |
837 void MacroAssembler::print_state() { | |
838 address rip = pc(); | |
839 pusha(); // get regs on stack | |
840 push(rbp); | |
841 movq(rbp, rsp); | |
842 andq(rsp, -16); // align stack as required by push_CPU_state and call | |
843 push_CPU_state(); // keeps alignment at 16 bytes | |
844 | |
845 lea(c_rarg0, InternalAddress(rip)); | |
846 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array | |
847 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); | |
848 | |
849 pop_CPU_state(); | |
850 mov(rsp, rbp); | |
851 pop(rbp); | |
852 popa(); | |
853 } | |
854 | |
855 #ifndef PRODUCT | |
856 extern "C" void findpc(intptr_t x); | |
857 #endif | |
858 | |
859 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
860 // In order to get locks to work, we need to fake a in_VM state | |
861 if (ShowMessageBoxOnError) { | |
862 JavaThread* thread = JavaThread::current(); | |
863 JavaThreadState saved_state = thread->thread_state(); | |
864 thread->set_thread_state(_thread_in_vm); | |
865 #ifndef PRODUCT | |
866 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
867 ttyLocker ttyl; | |
868 BytecodeCounter::print(); | |
869 } | |
870 #endif | |
871 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
872 // XXX correct this offset for amd64 | |
873 // This is the value of eip which points to where verify_oop will return. | |
874 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
875 print_state64(pc, regs); | |
876 BREAKPOINT; | |
877 assert(false, "start up GDB"); | |
878 } | |
879 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
880 } else { | |
881 ttyLocker ttyl; | |
882 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
883 msg); | |
884 assert(false, err_msg("DEBUG MESSAGE: %s", msg)); | |
885 } | |
886 } | |
887 | |
888 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { | |
889 ttyLocker ttyl; | |
890 FlagSetting fs(Debugging, true); | |
891 tty->print_cr("rip = 0x%016lx", pc); | |
892 #ifndef PRODUCT | |
893 tty->cr(); | |
894 findpc(pc); | |
895 tty->cr(); | |
896 #endif | |
897 #define PRINT_REG(rax, value) \ | |
898 { tty->print("%s = ", #rax); os::print_location(tty, value); } | |
899 PRINT_REG(rax, regs[15]); | |
900 PRINT_REG(rbx, regs[12]); | |
901 PRINT_REG(rcx, regs[14]); | |
902 PRINT_REG(rdx, regs[13]); | |
903 PRINT_REG(rdi, regs[8]); | |
904 PRINT_REG(rsi, regs[9]); | |
905 PRINT_REG(rbp, regs[10]); | |
906 PRINT_REG(rsp, regs[11]); | |
907 PRINT_REG(r8 , regs[7]); | |
908 PRINT_REG(r9 , regs[6]); | |
909 PRINT_REG(r10, regs[5]); | |
910 PRINT_REG(r11, regs[4]); | |
911 PRINT_REG(r12, regs[3]); | |
912 PRINT_REG(r13, regs[2]); | |
913 PRINT_REG(r14, regs[1]); | |
914 PRINT_REG(r15, regs[0]); | |
915 #undef PRINT_REG | |
916 // Print some words near top of staack. | |
917 int64_t* rsp = (int64_t*) regs[11]; | |
918 int64_t* dump_sp = rsp; | |
919 for (int col1 = 0; col1 < 8; col1++) { | |
920 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); | |
921 os::print_location(tty, *dump_sp++); | |
922 } | |
923 for (int row = 0; row < 25; row++) { | |
924 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); | |
925 for (int col = 0; col < 4; col++) { | |
926 tty->print(" 0x%016lx", *dump_sp++); | |
927 } | |
928 tty->cr(); | |
929 } | |
930 // Print some instructions around pc: | |
931 Disassembler::decode((address)pc-64, (address)pc); | |
932 tty->print_cr("--------"); | |
933 Disassembler::decode((address)pc, (address)pc+32); | |
934 } | |
935 | |
936 #endif // _LP64 | |
937 | |
938 // Now versions that are common to 32/64 bit | |
939 | |
940 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
941 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
942 } | |
943 | |
944 void MacroAssembler::addptr(Register dst, Register src) { | |
945 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
946 } | |
947 | |
948 void MacroAssembler::addptr(Address dst, Register src) { | |
949 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
950 } | |
951 | |
952 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { | |
953 if (reachable(src)) { | |
954 Assembler::addsd(dst, as_Address(src)); | |
955 } else { | |
956 lea(rscratch1, src); | |
957 Assembler::addsd(dst, Address(rscratch1, 0)); | |
958 } | |
959 } | |
960 | |
961 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { | |
962 if (reachable(src)) { | |
963 addss(dst, as_Address(src)); | |
964 } else { | |
965 lea(rscratch1, src); | |
966 addss(dst, Address(rscratch1, 0)); | |
967 } | |
968 } | |
969 | |
970 void MacroAssembler::align(int modulus) { | |
971 if (offset() % modulus != 0) { | |
972 nop(modulus - (offset() % modulus)); | |
973 } | |
974 } | |
975 | |
976 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
977 // Used in sign-masking with aligned address. | |
978 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
979 if (reachable(src)) { | |
980 Assembler::andpd(dst, as_Address(src)); | |
981 } else { | |
982 lea(rscratch1, src); | |
983 Assembler::andpd(dst, Address(rscratch1, 0)); | |
984 } | |
985 } | |
986 | |
987 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { | |
988 // Used in sign-masking with aligned address. | |
989 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
990 if (reachable(src)) { | |
991 Assembler::andps(dst, as_Address(src)); | |
992 } else { | |
993 lea(rscratch1, src); | |
994 Assembler::andps(dst, Address(rscratch1, 0)); | |
995 } | |
996 } | |
997 | |
998 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
999 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
1000 } | |
1001 | |
17780 | 1002 void MacroAssembler::atomic_incl(Address counter_addr) { |
1003 if (os::is_MP()) | |
1004 lock(); | |
1005 incrementl(counter_addr); | |
1006 } | |
1007 | |
1008 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { | |
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1009 if (reachable(counter_addr)) { |
17780 | 1010 atomic_incl(as_Address(counter_addr)); |
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1011 } else { |
17780 | 1012 lea(scr, counter_addr); |
1013 atomic_incl(Address(scr, 0)); | |
1014 } | |
1015 } | |
1016 | |
1017 #ifdef _LP64 | |
1018 void MacroAssembler::atomic_incq(Address counter_addr) { | |
1019 if (os::is_MP()) | |
1020 lock(); | |
1021 incrementq(counter_addr); | |
1022 } | |
1023 | |
1024 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { | |
1025 if (reachable(counter_addr)) { | |
1026 atomic_incq(as_Address(counter_addr)); | |
1027 } else { | |
1028 lea(scr, counter_addr); | |
1029 atomic_incq(Address(scr, 0)); | |
1030 } | |
1031 } | |
1032 #endif | |
7199 | 1033 |
1034 // Writes to stack successive pages until offset reached to check for | |
1035 // stack overflow + shadow pages. This clobbers tmp. | |
1036 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
1037 movptr(tmp, rsp); | |
1038 // Bang stack for total size given plus shadow page size. | |
1039 // Bang one page at a time because large size can bang beyond yellow and | |
1040 // red zones. | |
1041 Label loop; | |
1042 bind(loop); | |
1043 movl(Address(tmp, (-os::vm_page_size())), size ); | |
1044 subptr(tmp, os::vm_page_size()); | |
1045 subl(size, os::vm_page_size()); | |
1046 jcc(Assembler::greater, loop); | |
1047 | |
1048 // Bang down shadow pages too. | |
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1049 // At this point, (tmp-0) is the last address touched, so don't |
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1050 // touch it again. (It was touched as (tmp-pagesize) but then tmp |
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1051 // was post-decremented.) Skip this address by starting at i=1, and |
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1052 // touch a few more pages below. N.B. It is important to touch all |
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1053 // the way down to and including i=StackShadowPages. |
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1054 for (int i = 1; i <= StackShadowPages; i++) { |
7199 | 1055 // this could be any sized move but this is can be a debugging crumb |
1056 // so the bigger the better. | |
1057 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
1058 } | |
1059 } | |
1060 | |
17714
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1061 int MacroAssembler::biased_locking_enter(Register lock_reg, |
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1062 Register obj_reg, |
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1063 Register swap_reg, |
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1064 Register tmp_reg, |
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1065 bool swap_reg_contains_mark, |
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1066 Label& done, |
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1067 Label* slow_case, |
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1068 BiasedLockingCounters* counters) { |
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1069 assert(UseBiasedLocking, "why call this otherwise?"); |
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1070 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); |
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1071 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); ) |
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1072 bool need_tmp_reg = false; |
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1073 if (tmp_reg == noreg) { |
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1074 need_tmp_reg = true; |
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1075 tmp_reg = lock_reg; |
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1076 assert_different_registers(lock_reg, obj_reg, swap_reg); |
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1077 } else { |
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1078 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); |
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1079 } |
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1080 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); |
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1081 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); |
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1082 Address saved_mark_addr(lock_reg, 0); |
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1083 |
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1084 if (PrintBiasedLockingStatistics && counters == NULL) { |
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1085 counters = BiasedLocking::counters(); |
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1086 } |
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1087 // Biased locking |
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1088 // See whether the lock is currently biased toward our thread and |
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1089 // whether the epoch is still valid |
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1090 // Note that the runtime guarantees sufficient alignment of JavaThread |
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1091 // pointers to allow age to be placed into low bits |
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1092 // First check to see whether biasing is even enabled for this object |
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1093 Label cas_label; |
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1094 int null_check_offset = -1; |
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1095 if (!swap_reg_contains_mark) { |
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1096 null_check_offset = offset(); |
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1097 movptr(swap_reg, mark_addr); |
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1098 } |
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1099 if (need_tmp_reg) { |
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1100 push(tmp_reg); |
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1101 } |
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1102 movptr(tmp_reg, swap_reg); |
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1103 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); |
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1104 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); |
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1105 if (need_tmp_reg) { |
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1106 pop(tmp_reg); |
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1107 } |
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1108 jcc(Assembler::notEqual, cas_label); |
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1109 // The bias pattern is present in the object's header. Need to check |
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1110 // whether the bias owner and the epoch are both still current. |
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1111 #ifndef _LP64 |
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1112 // Note that because there is no current thread register on x86_32 we |
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1113 // need to store off the mark word we read out of the object to |
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1114 // avoid reloading it and needing to recheck invariants below. This |
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1115 // store is unfortunate but it makes the overall code shorter and |
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1116 // simpler. |
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1117 movptr(saved_mark_addr, swap_reg); |
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1118 #endif |
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1119 if (need_tmp_reg) { |
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1120 push(tmp_reg); |
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1121 } |
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1122 if (swap_reg_contains_mark) { |
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1123 null_check_offset = offset(); |
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1124 } |
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1125 load_prototype_header(tmp_reg, obj_reg); |
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1126 #ifdef _LP64 |
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1127 orptr(tmp_reg, r15_thread); |
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1128 xorptr(tmp_reg, swap_reg); |
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1129 Register header_reg = tmp_reg; |
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1130 #else |
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1131 xorptr(tmp_reg, swap_reg); |
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1132 get_thread(swap_reg); |
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1133 xorptr(swap_reg, tmp_reg); |
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1134 Register header_reg = swap_reg; |
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1135 #endif |
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1136 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); |
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1137 if (need_tmp_reg) { |
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1138 pop(tmp_reg); |
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|
1139 } |
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1140 if (counters != NULL) { |
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1141 cond_inc32(Assembler::zero, |
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1142 ExternalAddress((address) counters->biased_lock_entry_count_addr())); |
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1143 } |
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1144 jcc(Assembler::equal, done); |
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1145 |
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|
1146 Label try_revoke_bias; |
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|
1147 Label try_rebias; |
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|
1148 |
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|
1149 // At this point we know that the header has the bias pattern and |
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1150 // that we are not the bias owner in the current epoch. We need to |
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1151 // figure out more details about the state of the header in order to |
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1152 // know what operations can be legally performed on the object's |
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|
1153 // header. |
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|
1154 |
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|
1155 // If the low three bits in the xor result aren't clear, that means |
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1156 // the prototype header is no longer biased and we have to revoke |
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|
1157 // the bias on this object. |
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|
1158 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); |
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1159 jccb(Assembler::notZero, try_revoke_bias); |
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1160 |
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|
1161 // Biasing is still enabled for this data type. See whether the |
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|
1162 // epoch of the current bias is still valid, meaning that the epoch |
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1163 // bits of the mark word are equal to the epoch bits of the |
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1164 // prototype header. (Note that the prototype header's epoch bits |
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|
1165 // only change at a safepoint.) If not, attempt to rebias the object |
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|
1166 // toward the current thread. Note that we must be absolutely sure |
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1167 // that the current epoch is invalid in order to do this because |
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1168 // otherwise the manipulations it performs on the mark word are |
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|
1169 // illegal. |
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|
1170 testptr(header_reg, markOopDesc::epoch_mask_in_place); |
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|
1171 jccb(Assembler::notZero, try_rebias); |
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|
1172 |
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|
1173 // The epoch of the current bias is still valid but we know nothing |
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|
1174 // about the owner; it might be set or it might be clear. Try to |
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|
1175 // acquire the bias of the object using an atomic operation. If this |
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|
1176 // fails we will go in to the runtime to revoke the object's bias. |
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|
1177 // Note that we first construct the presumed unbiased header so we |
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|
1178 // don't accidentally blow away another thread's valid bias. |
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|
1179 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) |
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|
1180 andptr(swap_reg, |
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|
1181 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); |
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|
1182 if (need_tmp_reg) { |
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|
1183 push(tmp_reg); |
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|
1184 } |
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|
1185 #ifdef _LP64 |
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|
1186 movptr(tmp_reg, swap_reg); |
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|
1187 orptr(tmp_reg, r15_thread); |
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|
1188 #else |
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|
1189 get_thread(tmp_reg); |
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|
1190 orptr(tmp_reg, swap_reg); |
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|
1191 #endif |
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|
1192 if (os::is_MP()) { |
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|
1193 lock(); |
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|
1194 } |
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|
1195 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg |
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|
1196 if (need_tmp_reg) { |
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|
1197 pop(tmp_reg); |
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|
1198 } |
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|
1199 // If the biasing toward our thread failed, this means that |
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|
1200 // another thread succeeded in biasing it toward itself and we |
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|
1201 // need to revoke that bias. The revocation will occur in the |
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|
1202 // interpreter runtime in the slow case. |
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|
1203 if (counters != NULL) { |
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|
1204 cond_inc32(Assembler::zero, |
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|
1205 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); |
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|
1206 } |
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|
1207 if (slow_case != NULL) { |
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|
1208 jcc(Assembler::notZero, *slow_case); |
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|
1209 } |
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|
1210 jmp(done); |
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|
1211 |
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|
1212 bind(try_rebias); |
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|
1213 // At this point we know the epoch has expired, meaning that the |
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|
1214 // current "bias owner", if any, is actually invalid. Under these |
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|
1215 // circumstances _only_, we are allowed to use the current header's |
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|
1216 // value as the comparison value when doing the cas to acquire the |
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|
1217 // bias in the current epoch. In other words, we allow transfer of |
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|
1218 // the bias from one thread to another directly in this situation. |
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|
1219 // |
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|
1220 // FIXME: due to a lack of registers we currently blow away the age |
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|
1221 // bits in this situation. Should attempt to preserve them. |
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|
1222 if (need_tmp_reg) { |
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|
1223 push(tmp_reg); |
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|
1224 } |
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changeset
|
1225 load_prototype_header(tmp_reg, obj_reg); |
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|
1226 #ifdef _LP64 |
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|
1227 orptr(tmp_reg, r15_thread); |
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|
1228 #else |
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diff
changeset
|
1229 get_thread(swap_reg); |
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|
1230 orptr(tmp_reg, swap_reg); |
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|
1231 movptr(swap_reg, saved_mark_addr); |
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diff
changeset
|
1232 #endif |
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changeset
|
1233 if (os::is_MP()) { |
4d4ea046d32a
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kvn
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diff
changeset
|
1234 lock(); |
4d4ea046d32a
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parents:
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diff
changeset
|
1235 } |
4d4ea046d32a
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changeset
|
1236 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg |
4d4ea046d32a
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diff
changeset
|
1237 if (need_tmp_reg) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1238 pop(tmp_reg); |
4d4ea046d32a
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kvn
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diff
changeset
|
1239 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1240 // If the biasing toward our thread failed, then another thread |
4d4ea046d32a
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diff
changeset
|
1241 // succeeded in biasing it toward itself and we need to revoke that |
4d4ea046d32a
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diff
changeset
|
1242 // bias. The revocation will occur in the runtime in the slow case. |
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diff
changeset
|
1243 if (counters != NULL) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1244 cond_inc32(Assembler::zero, |
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diff
changeset
|
1245 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1246 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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parents:
13424
diff
changeset
|
1247 if (slow_case != NULL) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1248 jcc(Assembler::notZero, *slow_case); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1249 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1250 jmp(done); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
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13424
diff
changeset
|
1251 |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1252 bind(try_revoke_bias); |
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diff
changeset
|
1253 // The prototype mark in the klass doesn't have the bias bit set any |
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diff
changeset
|
1254 // more, indicating that objects of this data type are not supposed |
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diff
changeset
|
1255 // to be biased any more. We are going to try to reset the mark of |
4d4ea046d32a
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diff
changeset
|
1256 // this object to the prototype value and fall through to the |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1257 // CAS-based locking scheme. Note that if our CAS fails, it means |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1258 // that another thread raced us for the privilege of revoking the |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1259 // bias of this particular object, so it's okay to continue in the |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1260 // normal locking code. |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
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diff
changeset
|
1261 // |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1262 // FIXME: due to a lack of registers we currently blow away the age |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1263 // bits in this situation. Should attempt to preserve them. |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1264 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
13424
diff
changeset
|
1265 if (need_tmp_reg) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1266 push(tmp_reg); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
13424
diff
changeset
|
1267 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1268 load_prototype_header(tmp_reg, obj_reg); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1269 if (os::is_MP()) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1270 lock(); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
13424
diff
changeset
|
1271 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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parents:
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diff
changeset
|
1273 if (need_tmp_reg) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1274 pop(tmp_reg); |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
13424
diff
changeset
|
1275 } |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1276 // Fall through to the normal CAS-based lock, because no matter what |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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diff
changeset
|
1277 // the result of the above CAS, some thread must have succeeded in |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1278 // removing the bias bit from the object's header. |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
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parents:
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diff
changeset
|
1279 if (counters != NULL) { |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1280 cond_inc32(Assembler::zero, |
4d4ea046d32a
8033805: Move Fast_Lock/Fast_Unlock code from .ad files to macroassembler
kvn
parents:
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diff
changeset
|
1281 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); |
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1282 } |
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1283 |
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1284 bind(cas_label); |
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1285 |
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1286 return null_check_offset; |
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1287 } |
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1288 |
7199 | 1289 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { |
1290 assert(UseBiasedLocking, "why call this otherwise?"); | |
1291 | |
1292 // Check for biased locking unlock case, which is a no-op | |
1293 // Note: we do not have to check the thread ID for two reasons. | |
1294 // First, the interpreter checks for IllegalMonitorStateException at | |
1295 // a higher level. Second, if the bias was revoked while we held the | |
1296 // lock, the object could not be rebiased toward another thread, so | |
1297 // the bias bit would be clear. | |
1298 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
1299 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
1300 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
1301 jcc(Assembler::equal, done); | |
1302 } | |
1303 | |
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1304 #ifdef COMPILER2 |
17780 | 1305 |
1306 #if INCLUDE_RTM_OPT | |
1307 | |
1308 // Update rtm_counters based on abort status | |
1309 // input: abort_status | |
1310 // rtm_counters (RTMLockingCounters*) | |
1311 // flags are killed | |
1312 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { | |
1313 | |
1314 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); | |
1315 if (PrintPreciseRTMLockingStatistics) { | |
1316 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { | |
1317 Label check_abort; | |
1318 testl(abort_status, (1<<i)); | |
1319 jccb(Assembler::equal, check_abort); | |
1320 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); | |
1321 bind(check_abort); | |
1322 } | |
1323 } | |
1324 } | |
1325 | |
1326 // Branch if (random & (count-1) != 0), count is 2^n | |
1327 // tmp, scr and flags are killed | |
1328 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { | |
1329 assert(tmp == rax, ""); | |
1330 assert(scr == rdx, ""); | |
1331 rdtsc(); // modifies EDX:EAX | |
1332 andptr(tmp, count-1); | |
1333 jccb(Assembler::notZero, brLabel); | |
1334 } | |
1335 | |
1336 // Perform abort ratio calculation, set no_rtm bit if high ratio | |
1337 // input: rtm_counters_Reg (RTMLockingCounters* address) | |
1338 // tmpReg, rtm_counters_Reg and flags are killed | |
1339 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, | |
1340 Register rtm_counters_Reg, | |
1341 RTMLockingCounters* rtm_counters, | |
1342 Metadata* method_data) { | |
1343 Label L_done, L_check_always_rtm1, L_check_always_rtm2; | |
1344 | |
1345 if (RTMLockingCalculationDelay > 0) { | |
1346 // Delay calculation | |
1347 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); | |
1348 testptr(tmpReg, tmpReg); | |
1349 jccb(Assembler::equal, L_done); | |
1350 } | |
1351 // Abort ratio calculation only if abort_count > RTMAbortThreshold | |
1352 // Aborted transactions = abort_count * 100 | |
1353 // All transactions = total_count * RTMTotalCountIncrRate | |
1354 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) | |
1355 | |
1356 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); | |
1357 cmpptr(tmpReg, RTMAbortThreshold); | |
1358 jccb(Assembler::below, L_check_always_rtm2); | |
1359 imulptr(tmpReg, tmpReg, 100); | |
1360 | |
1361 Register scrReg = rtm_counters_Reg; | |
1362 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); | |
1363 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); | |
1364 imulptr(scrReg, scrReg, RTMAbortRatio); | |
1365 cmpptr(tmpReg, scrReg); | |
1366 jccb(Assembler::below, L_check_always_rtm1); | |
1367 if (method_data != NULL) { | |
1368 // set rtm_state to "no rtm" in MDO | |
1369 mov_metadata(tmpReg, method_data); | |
1370 if (os::is_MP()) { | |
1371 lock(); | |
1372 } | |
1373 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); | |
1374 } | |
1375 jmpb(L_done); | |
1376 bind(L_check_always_rtm1); | |
1377 // Reload RTMLockingCounters* address | |
1378 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); | |
1379 bind(L_check_always_rtm2); | |
1380 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); | |
1381 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); | |
1382 jccb(Assembler::below, L_done); | |
1383 if (method_data != NULL) { | |
1384 // set rtm_state to "always rtm" in MDO | |
1385 mov_metadata(tmpReg, method_data); | |
1386 if (os::is_MP()) { | |
1387 lock(); | |
1388 } | |
1389 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); | |
1390 } | |
1391 bind(L_done); | |
1392 } | |
1393 | |
1394 // Update counters and perform abort ratio calculation | |
1395 // input: abort_status_Reg | |
1396 // rtm_counters_Reg, flags are killed | |
1397 void MacroAssembler::rtm_profiling(Register abort_status_Reg, | |
1398 Register rtm_counters_Reg, | |
1399 RTMLockingCounters* rtm_counters, | |
1400 Metadata* method_data, | |
1401 bool profile_rtm) { | |
1402 | |
1403 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); | |
1404 // update rtm counters based on rax value at abort | |
1405 // reads abort_status_Reg, updates flags | |
1406 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); | |
1407 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); | |
1408 if (profile_rtm) { | |
1409 // Save abort status because abort_status_Reg is used by following code. | |
1410 if (RTMRetryCount > 0) { | |
1411 push(abort_status_Reg); | |
1412 } | |
1413 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); | |
1414 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); | |
1415 // restore abort status | |
1416 if (RTMRetryCount > 0) { | |
1417 pop(abort_status_Reg); | |
1418 } | |
1419 } | |
1420 } | |
1421 | |
1422 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) | |
1423 // inputs: retry_count_Reg | |
1424 // : abort_status_Reg | |
1425 // output: retry_count_Reg decremented by 1 | |
1426 // flags are killed | |
1427 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { | |
1428 Label doneRetry; | |
1429 assert(abort_status_Reg == rax, ""); | |
1430 // The abort reason bits are in eax (see all states in rtmLocking.hpp) | |
1431 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) | |
1432 // if reason is in 0x6 and retry count != 0 then retry | |
1433 andptr(abort_status_Reg, 0x6); | |
1434 jccb(Assembler::zero, doneRetry); | |
1435 testl(retry_count_Reg, retry_count_Reg); | |
1436 jccb(Assembler::zero, doneRetry); | |
1437 pause(); | |
1438 decrementl(retry_count_Reg); | |
1439 jmp(retryLabel); | |
1440 bind(doneRetry); | |
1441 } | |
1442 | |
1443 // Spin and retry if lock is busy, | |
1444 // inputs: box_Reg (monitor address) | |
1445 // : retry_count_Reg | |
1446 // output: retry_count_Reg decremented by 1 | |
1447 // : clear z flag if retry count exceeded | |
1448 // tmp_Reg, scr_Reg, flags are killed | |
1449 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, | |
1450 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { | |
1451 Label SpinLoop, SpinExit, doneRetry; | |
1452 // Clean monitor_value bit to get valid pointer | |
1453 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value; | |
1454 | |
1455 testl(retry_count_Reg, retry_count_Reg); | |
1456 jccb(Assembler::zero, doneRetry); | |
1457 decrementl(retry_count_Reg); | |
1458 movptr(scr_Reg, RTMSpinLoopCount); | |
1459 | |
1460 bind(SpinLoop); | |
1461 pause(); | |
1462 decrementl(scr_Reg); | |
1463 jccb(Assembler::lessEqual, SpinExit); | |
1464 movptr(tmp_Reg, Address(box_Reg, owner_offset)); | |
1465 testptr(tmp_Reg, tmp_Reg); | |
1466 jccb(Assembler::notZero, SpinLoop); | |
1467 | |
1468 bind(SpinExit); | |
1469 jmp(retryLabel); | |
1470 bind(doneRetry); | |
1471 incrementl(retry_count_Reg); // clear z flag | |
1472 } | |
1473 | |
1474 // Use RTM for normal stack locks | |
1475 // Input: objReg (object to lock) | |
1476 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, | |
1477 Register retry_on_abort_count_Reg, | |
1478 RTMLockingCounters* stack_rtm_counters, | |
1479 Metadata* method_data, bool profile_rtm, | |
1480 Label& DONE_LABEL, Label& IsInflated) { | |
1481 assert(UseRTMForStackLocks, "why call this otherwise?"); | |
1482 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); | |
1483 assert(tmpReg == rax, ""); | |
1484 assert(scrReg == rdx, ""); | |
1485 Label L_rtm_retry, L_decrement_retry, L_on_abort; | |
1486 | |
1487 if (RTMRetryCount > 0) { | |
1488 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort | |
1489 bind(L_rtm_retry); | |
1490 } | |
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1491 movptr(tmpReg, Address(objReg, 0)); |
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1492 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased |
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1493 jcc(Assembler::notZero, IsInflated); |
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1494 |
17780 | 1495 if (PrintPreciseRTMLockingStatistics || profile_rtm) { |
1496 Label L_noincrement; | |
1497 if (RTMTotalCountIncrRate > 1) { | |
1498 // tmpReg, scrReg and flags are killed | |
1499 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); | |
1500 } | |
1501 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); | |
1502 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); | |
1503 bind(L_noincrement); | |
1504 } | |
1505 xbegin(L_on_abort); | |
1506 movptr(tmpReg, Address(objReg, 0)); // fetch markword | |
1507 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits | |
1508 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked | |
1509 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked | |
1510 | |
1511 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX | |
1512 if (UseRTMXendForLockBusy) { | |
1513 xend(); | |
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1514 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) |
17780 | 1515 jmp(L_decrement_retry); |
1516 } | |
1517 else { | |
1518 xabort(0); | |
1519 } | |
1520 bind(L_on_abort); | |
1521 if (PrintPreciseRTMLockingStatistics || profile_rtm) { | |
1522 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); | |
1523 } | |
1524 bind(L_decrement_retry); | |
1525 if (RTMRetryCount > 0) { | |
1526 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) | |
1527 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); | |
1528 } | |
1529 } | |
1530 | |
1531 // Use RTM for inflating locks | |
1532 // inputs: objReg (object to lock) | |
1533 // boxReg (on-stack box address (displaced header location) - KILLED) | |
1534 // tmpReg (ObjectMonitor address + 2(monitor_value)) | |
1535 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, | |
1536 Register scrReg, Register retry_on_busy_count_Reg, | |
1537 Register retry_on_abort_count_Reg, | |
1538 RTMLockingCounters* rtm_counters, | |
1539 Metadata* method_data, bool profile_rtm, | |
1540 Label& DONE_LABEL) { | |
1541 assert(UseRTMLocking, "why call this otherwise?"); | |
1542 assert(tmpReg == rax, ""); | |
1543 assert(scrReg == rdx, ""); | |
1544 Label L_rtm_retry, L_decrement_retry, L_on_abort; | |
1545 // Clean monitor_value bit to get valid pointer | |
1546 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value; | |
1547 | |
1548 // Without cast to int32_t a movptr will destroy r10 which is typically obj | |
1549 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); | |
1550 movptr(boxReg, tmpReg); // Save ObjectMonitor address | |
1551 | |
1552 if (RTMRetryCount > 0) { | |
1553 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy | |
1554 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort | |
1555 bind(L_rtm_retry); | |
1556 } | |
1557 if (PrintPreciseRTMLockingStatistics || profile_rtm) { | |
1558 Label L_noincrement; | |
1559 if (RTMTotalCountIncrRate > 1) { | |
1560 // tmpReg, scrReg and flags are killed | |
1561 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); | |
1562 } | |
1563 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); | |
1564 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); | |
1565 bind(L_noincrement); | |
1566 } | |
1567 xbegin(L_on_abort); | |
1568 movptr(tmpReg, Address(objReg, 0)); | |
1569 movptr(tmpReg, Address(tmpReg, owner_offset)); | |
1570 testptr(tmpReg, tmpReg); | |
1571 jcc(Assembler::zero, DONE_LABEL); | |
1572 if (UseRTMXendForLockBusy) { | |
1573 xend(); | |
1574 jmp(L_decrement_retry); | |
1575 } | |
1576 else { | |
1577 xabort(0); | |
1578 } | |
1579 bind(L_on_abort); | |
1580 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX | |
1581 if (PrintPreciseRTMLockingStatistics || profile_rtm) { | |
1582 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); | |
1583 } | |
1584 if (RTMRetryCount > 0) { | |
1585 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) | |
1586 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); | |
1587 } | |
1588 | |
1589 movptr(tmpReg, Address(boxReg, owner_offset)) ; | |
1590 testptr(tmpReg, tmpReg) ; | |
1591 jccb(Assembler::notZero, L_decrement_retry) ; | |
1592 | |
1593 // Appears unlocked - try to swing _owner from null to non-null. | |
1594 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
1595 #ifdef _LP64 | |
1596 Register threadReg = r15_thread; | |
1597 #else | |
1598 get_thread(scrReg); | |
1599 Register threadReg = scrReg; | |
1600 #endif | |
1601 if (os::is_MP()) { | |
1602 lock(); | |
1603 } | |
1604 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg | |
1605 | |
1606 if (RTMRetryCount > 0) { | |
1607 // success done else retry | |
1608 jccb(Assembler::equal, DONE_LABEL) ; | |
1609 bind(L_decrement_retry); | |
1610 // Spin and retry if lock is busy. | |
1611 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); | |
1612 } | |
1613 else { | |
1614 bind(L_decrement_retry); | |
1615 } | |
1616 } | |
1617 | |
1618 #endif // INCLUDE_RTM_OPT | |
1619 | |
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1620 // Fast_Lock and Fast_Unlock used by C2 |
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1621 |
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1622 // Because the transitions from emitted code to the runtime |
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1623 // monitorenter/exit helper stubs are so slow it's critical that |
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1624 // we inline both the stack-locking fast-path and the inflated fast path. |
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1625 // |
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1626 // See also: cmpFastLock and cmpFastUnlock. |
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1627 // |
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1628 // What follows is a specialized inline transliteration of the code |
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1629 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat |
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1630 // another option would be to emit TrySlowEnter and TrySlowExit methods |
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1631 // at startup-time. These methods would accept arguments as |
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1632 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure |
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1633 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply |
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1634 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. |
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1635 // In practice, however, the # of lock sites is bounded and is usually small. |
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1636 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer |
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1637 // if the processor uses simple bimodal branch predictors keyed by EIP |
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1638 // Since the helper routines would be called from multiple synchronization |
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1639 // sites. |
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1640 // |
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1641 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" |
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1642 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites |
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1643 // to those specialized methods. That'd give us a mostly platform-independent |
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1644 // implementation that the JITs could optimize and inline at their pleasure. |
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1645 // Done correctly, the only time we'd need to cross to native could would be |
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1646 // to park() or unpark() threads. We'd also need a few more unsafe operators |
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1647 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and |
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1648 // (b) explicit barriers or fence operations. |
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1649 // |
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1650 // TODO: |
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|
1651 // |
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1652 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). |
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1653 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. |
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1654 // Given TLAB allocation, Self is usually manifested in a register, so passing it into |
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1655 // the lock operators would typically be faster than reifying Self. |
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|
1656 // |
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1657 // * Ideally I'd define the primitives as: |
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1658 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. |
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1659 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED |
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1660 // Unfortunately ADLC bugs prevent us from expressing the ideal form. |
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1661 // Instead, we're stuck with a rather awkward and brittle register assignments below. |
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1662 // Furthermore the register assignments are overconstrained, possibly resulting in |
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1663 // sub-optimal code near the synchronization site. |
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1664 // |
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1665 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. |
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1666 // Alternately, use a better sp-proximity test. |
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|
1667 // |
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|
1668 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. |
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1669 // Either one is sufficient to uniquely identify a thread. |
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|
1670 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. |
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|
1671 // |
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|
1672 // * Intrinsify notify() and notifyAll() for the common cases where the |
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|
1673 // object is locked by the calling thread but the waitlist is empty. |
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|
1674 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). |
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|
1675 // |
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|
1676 // * use jccb and jmpb instead of jcc and jmp to improve code density. |
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|
1677 // But beware of excessive branch density on AMD Opterons. |
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|
1678 // |
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|
1679 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success |
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|
1680 // or failure of the fast-path. If the fast-path fails then we pass |
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|
1681 // control to the slow-path, typically in C. In Fast_Lock and |
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|
1682 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 |
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|
1683 // will emit a conditional branch immediately after the node. |
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|
1684 // So we have branches to branches and lots of ICC.ZF games. |
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|
1685 // Instead, it might be better to have C2 pass a "FailureLabel" |
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|
1686 // into Fast_Lock and Fast_Unlock. In the case of success, control |
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|
1687 // will drop through the node. ICC.ZF is undefined at exit. |
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|
1688 // In the case of failure, the node will branch directly to the |
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|
1689 // FailureLabel |
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|
1690 |
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|
1691 |
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|
1692 // obj: object to lock |
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|
1693 // box: on-stack box address (displaced header location) - KILLED |
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|
1694 // rax,: tmp -- KILLED |
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|
1695 // scr: tmp -- KILLED |
17780 | 1696 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, |
1697 Register scrReg, Register cx1Reg, Register cx2Reg, | |
1698 BiasedLockingCounters* counters, | |
1699 RTMLockingCounters* rtm_counters, | |
1700 RTMLockingCounters* stack_rtm_counters, | |
1701 Metadata* method_data, | |
1702 bool use_rtm, bool profile_rtm) { | |
17714
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|
1703 // Ensure the register assignents are disjoint |
17780 | 1704 assert(tmpReg == rax, ""); |
1705 | |
1706 if (use_rtm) { | |
1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); | |
1708 } else { | |
1709 assert(cx1Reg == noreg, ""); | |
1710 assert(cx2Reg == noreg, ""); | |
1711 assert_different_registers(objReg, boxReg, tmpReg, scrReg); | |
1712 } | |
17714
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|
1713 |
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|
1714 if (counters != NULL) { |
17780 | 1715 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); |
17714
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|
1716 } |
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|
1717 if (EmitSync & 1) { |
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|
1718 // set box->dhw = unused_mark (3) |
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|
1719 // Force all sync thru slow-path: slow_enter() and slow_exit() |
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|
1720 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); |
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|
1721 cmpptr (rsp, (int32_t)NULL_WORD); |
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|
1722 } else |
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|
1723 if (EmitSync & 2) { |
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|
1724 Label DONE_LABEL ; |
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|
1725 if (UseBiasedLocking) { |
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|
1726 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. |
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|
1727 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); |
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|
1728 } |
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|
1729 |
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|
1730 movptr(tmpReg, Address(objReg, 0)); // fetch markword |
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|
1731 orptr (tmpReg, 0x1); |
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|
1732 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS |
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|
1733 if (os::is_MP()) { |
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|
1734 lock(); |
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|
1735 } |
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|
1736 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
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|
1737 jccb(Assembler::equal, DONE_LABEL); |
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|
1738 // Recursive locking |
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|
1739 subptr(tmpReg, rsp); |
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|
1740 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); |
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|
1741 movptr(Address(boxReg, 0), tmpReg); |
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|
1742 bind(DONE_LABEL); |
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|
1743 } else { |
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|
1744 // Possible cases that we'll encounter in fast_lock |
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|
1745 // ------------------------------------------------ |
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|
1746 // * Inflated |
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|
1747 // -- unlocked |
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|
1748 // -- Locked |
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|
1749 // = by self |
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|
1750 // = by other |
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|
1751 // * biased |
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|
1752 // -- by Self |
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|
1753 // -- by other |
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|
1754 // * neutral |
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|
1755 // * stack-locked |
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|
1756 // -- by self |
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|
1757 // = sp-proximity test hits |
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|
1758 // = sp-proximity test generates false-negative |
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|
1759 // -- by other |
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|
1760 // |
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|
1761 |
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|
1762 Label IsInflated, DONE_LABEL; |
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|
1763 |
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|
1764 // it's stack-locked, biased or neutral |
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|
1765 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage |
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1766 // order to reduce the number of conditional branches in the most common cases. |
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1767 // Beware -- there's a subtle invariant that fetch of the markword |
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1768 // at [FETCH], below, will never observe a biased encoding (*101b). |
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1769 // If this invariant is not held we risk exclusion (safety) failure. |
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1770 if (UseBiasedLocking && !UseOptoBiasInlining) { |
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1771 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, counters); |
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1772 } |
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1773 |
17780 | 1774 #if INCLUDE_RTM_OPT |
1775 if (UseRTMForStackLocks && use_rtm) { | |
1776 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, | |
1777 stack_rtm_counters, method_data, profile_rtm, | |
1778 DONE_LABEL, IsInflated); | |
1779 } | |
1780 #endif // INCLUDE_RTM_OPT | |
1781 | |
17714
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1782 movptr(tmpReg, Address(objReg, 0)); // [FETCH] |
17780 | 1783 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased |
1784 jccb(Assembler::notZero, IsInflated); | |
17714
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1785 |
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1786 // Attempt stack-locking ... |
17780 | 1787 orptr (tmpReg, markOopDesc::unlocked_value); |
17714
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1788 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS |
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1789 if (os::is_MP()) { |
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1790 lock(); |
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1791 } |
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1792 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
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1793 if (counters != NULL) { |
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1794 cond_inc32(Assembler::equal, |
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1795 ExternalAddress((address)counters->fast_path_entry_count_addr())); |
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1796 } |
17780 | 1797 jcc(Assembler::equal, DONE_LABEL); // Success |
1798 | |
1799 // Recursive locking. | |
1800 // The object is stack-locked: markword contains stack pointer to BasicLock. | |
1801 // Locked by current thread if difference with current SP is less than one page. | |
17714
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1802 subptr(tmpReg, rsp); |
17780 | 1803 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. |
17714
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1804 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); |
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1805 movptr(Address(boxReg, 0), tmpReg); |
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1806 if (counters != NULL) { |
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1807 cond_inc32(Assembler::equal, |
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1808 ExternalAddress((address)counters->fast_path_entry_count_addr())); |
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1809 } |
17780 | 1810 jmp(DONE_LABEL); |
17714
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1811 |
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1812 bind(IsInflated); |
17780 | 1813 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + 2(monitor_value) |
1814 | |
1815 #if INCLUDE_RTM_OPT | |
1816 // Use the same RTM locking code in 32- and 64-bit VM. | |
1817 if (use_rtm) { | |
1818 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, | |
1819 rtm_counters, method_data, profile_rtm, DONE_LABEL); | |
1820 } else { | |
1821 #endif // INCLUDE_RTM_OPT | |
1822 | |
17714
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1823 #ifndef _LP64 |
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1824 // The object is inflated. |
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1825 // |
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1826 // TODO-FIXME: eliminate the ugly use of manifest constants: |
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1827 // Use markOopDesc::monitor_value instead of "2". |
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1828 // use markOop::unused_mark() instead of "3". |
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1829 // The tmpReg value is an objectMonitor reference ORed with |
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1830 // markOopDesc::monitor_value (2). We can either convert tmpReg to an |
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1831 // objectmonitor pointer by masking off the "2" bit or we can just |
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1832 // use tmpReg as an objectmonitor pointer but bias the objectmonitor |
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1833 // field offsets with "-2" to compensate for and annul the low-order tag bit. |
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1834 // |
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1835 // I use the latter as it avoids AGI stalls. |
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1836 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" |
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1837 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". |
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1838 // |
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1839 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) |
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1840 |
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1841 // boxReg refers to the on-stack BasicLock in the current frame. |
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1842 // We'd like to write: |
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1843 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. |
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1844 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers |
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1845 // additional latency as we have another ST in the store buffer that must drain. |
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1846 |
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1847 if (EmitSync & 8192) { |
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1848 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty |
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1849 get_thread (scrReg); |
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1850 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] |
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1851 movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
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1852 if (os::is_MP()) { |
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|
1853 lock(); |
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|
1854 } |
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1855 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1856 } else |
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1857 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
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1858 movptr(scrReg, boxReg); |
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1859 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] |
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1860 |
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1861 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes |
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1862 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
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1863 // prefetchw [eax + Offset(_owner)-2] |
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1864 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1865 } |
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|
1866 |
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1867 if ((EmitSync & 64) == 0) { |
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1868 // Optimistic form: consider XORL tmpReg,tmpReg |
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1869 movptr(tmpReg, NULL_WORD); |
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1870 } else { |
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1871 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
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1872 // Test-And-CAS instead of CAS |
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1873 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner |
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1874 testptr(tmpReg, tmpReg); // Locked ? |
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1875 jccb (Assembler::notZero, DONE_LABEL); |
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1876 } |
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|
1877 |
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1878 // Appears unlocked - try to swing _owner from null to non-null. |
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1879 // Ideally, I'd manifest "Self" with get_thread and then attempt |
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1880 // to CAS the register containing Self into m->Owner. |
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1881 // But we don't have enough registers, so instead we can either try to CAS |
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1882 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds |
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1883 // we later store "Self" into m->Owner. Transiently storing a stack address |
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1884 // (rsp or the address of the box) into m->owner is harmless. |
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1885 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. |
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1886 if (os::is_MP()) { |
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1887 lock(); |
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1888 } |
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1889 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1890 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 |
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1891 jccb (Assembler::notZero, DONE_LABEL); |
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1892 get_thread (scrReg); // beware: clobbers ICCs |
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1893 movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg); |
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1894 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success |
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1895 |
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1896 // If the CAS fails we can either retry or pass control to the slow-path. |
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1897 // We use the latter tactic. |
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1898 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
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1899 // If the CAS was successful ... |
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1900 // Self has acquired the lock |
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1901 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. |
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1902 // Intentional fall-through into DONE_LABEL ... |
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1903 } else { |
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1904 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty |
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1905 movptr(boxReg, tmpReg); |
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1906 |
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1907 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes |
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1908 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
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1909 // prefetchw [eax + Offset(_owner)-2] |
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1910 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1911 } |
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1912 |
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1913 if ((EmitSync & 64) == 0) { |
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1914 // Optimistic form |
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1915 xorptr (tmpReg, tmpReg); |
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1916 } else { |
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1917 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
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1918 movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); // rax, = m->_owner |
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1919 testptr(tmpReg, tmpReg); // Locked ? |
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1920 jccb (Assembler::notZero, DONE_LABEL); |
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1921 } |
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1922 |
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1923 // Appears unlocked - try to swing _owner from null to non-null. |
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1924 // Use either "Self" (in scr) or rsp as thread identity in _owner. |
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1925 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. |
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1926 get_thread (scrReg); |
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1927 if (os::is_MP()) { |
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1928 lock(); |
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1929 } |
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1930 cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1931 |
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1932 // If the CAS fails we can either retry or pass control to the slow-path. |
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1933 // We use the latter tactic. |
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1934 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
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1935 // If the CAS was successful ... |
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1936 // Self has acquired the lock |
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1937 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. |
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1938 // Intentional fall-through into DONE_LABEL ... |
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1939 } |
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1940 #else // _LP64 |
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1941 // It's inflated |
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1942 |
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1943 // TODO: someday avoid the ST-before-CAS penalty by |
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1944 // relocating (deferring) the following ST. |
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1945 // We should also think about trying a CAS without having |
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1946 // fetched _owner. If the CAS is successful we may |
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1947 // avoid an RTO->RTS upgrade on the $line. |
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1948 |
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1949 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
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1950 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); |
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1951 |
17780 | 1952 movptr (boxReg, tmpReg); |
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1953 movptr (tmpReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1954 testptr(tmpReg, tmpReg); |
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1955 jccb (Assembler::notZero, DONE_LABEL); |
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1956 |
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1957 // It's inflated and appears unlocked |
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1958 if (os::is_MP()) { |
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1959 lock(); |
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1960 } |
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1961 cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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1962 // Intentional fall-through into DONE_LABEL ... |
17780 | 1963 #endif // _LP64 |
1964 | |
1965 #if INCLUDE_RTM_OPT | |
1966 } // use_rtm() | |
17714
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1967 #endif |
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1968 // DONE_LABEL is a hot target - we'd really like to place it at the |
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1969 // start of cache line by padding with NOPs. |
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1970 // See the AMD and Intel software optimization manuals for the |
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1971 // most efficient "long" NOP encodings. |
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1972 // Unfortunately none of our alignment mechanisms suffice. |
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1973 bind(DONE_LABEL); |
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1974 |
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1975 // At DONE_LABEL the icc ZFlag is set as follows ... |
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1976 // Fast_Unlock uses the same protocol. |
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1977 // ZFlag == 1 -> Success |
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1978 // ZFlag == 0 -> Failure - force control through the slow-path |
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1979 } |
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1980 } |
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1981 |
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1982 // obj: object to unlock |
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1983 // box: box address (displaced header location), killed. Must be EAX. |
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1984 // tmp: killed, cannot be obj nor box. |
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1985 // |
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1986 // Some commentary on balanced locking: |
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1987 // |
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1988 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. |
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1989 // Methods that don't have provably balanced locking are forced to run in the |
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1990 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. |
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1991 // The interpreter provides two properties: |
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1992 // I1: At return-time the interpreter automatically and quietly unlocks any |
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1993 // objects acquired the current activation (frame). Recall that the |
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1994 // interpreter maintains an on-stack list of locks currently held by |
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1995 // a frame. |
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1996 // I2: If a method attempts to unlock an object that is not held by the |
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1997 // the frame the interpreter throws IMSX. |
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1998 // |
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1999 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). |
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2000 // B() doesn't have provably balanced locking so it runs in the interpreter. |
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2001 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O |
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2002 // is still locked by A(). |
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2003 // |
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2004 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: |
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2005 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter |
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2006 // should not be unlocked by "normal" java-level locking and vice-versa. The specification |
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2007 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. |
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2008 |
17780 | 2009 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { |
2010 assert(boxReg == rax, ""); | |
2011 assert_different_registers(objReg, boxReg, tmpReg); | |
17714
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2012 |
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2013 if (EmitSync & 4) { |
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2014 // Disable - inhibit all inlining. Force control through the slow-path |
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2015 cmpptr (rsp, 0); |
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2016 } else |
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2017 if (EmitSync & 8) { |
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2018 Label DONE_LABEL; |
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2019 if (UseBiasedLocking) { |
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2020 biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
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2021 } |
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2022 // Classic stack-locking code ... |
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2023 // Check whether the displaced header is 0 |
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2024 //(=> recursive unlock) |
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2025 movptr(tmpReg, Address(boxReg, 0)); |
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2026 testptr(tmpReg, tmpReg); |
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2027 jccb(Assembler::zero, DONE_LABEL); |
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2028 // If not recursive lock, reset the header to displaced header |
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2029 if (os::is_MP()) { |
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2030 lock(); |
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2031 } |
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2032 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
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2033 bind(DONE_LABEL); |
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2034 } else { |
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2035 Label DONE_LABEL, Stacked, CheckSucc; |
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2036 |
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2037 // Critically, the biased locking test must have precedence over |
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2038 // and appear before the (box->dhw == 0) recursive stack-lock test. |
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2039 if (UseBiasedLocking && !UseOptoBiasInlining) { |
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2040 biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
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2041 } |
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2042 |
17780 | 2043 #if INCLUDE_RTM_OPT |
2044 if (UseRTMForStackLocks && use_rtm) { | |
2045 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); | |
2046 Label L_regular_unlock; | |
2047 movptr(tmpReg, Address(objReg, 0)); // fetch markword | |
2048 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits | |
2049 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked | |
2050 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock | |
2051 xend(); // otherwise end... | |
2052 jmp(DONE_LABEL); // ... and we're done | |
2053 bind(L_regular_unlock); | |
2054 } | |
2055 #endif | |
2056 | |
17714
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2057 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header |
17780 | 2058 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock |
17714
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2059 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword |
17780 | 2060 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? |
17714
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2061 jccb (Assembler::zero, Stacked); |
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2062 |
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2063 // It's inflated. |
17780 | 2064 #if INCLUDE_RTM_OPT |
2065 if (use_rtm) { | |
2066 Label L_regular_inflated_unlock; | |
2067 // Clean monitor_value bit to get valid pointer | |
2068 int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value; | |
2069 movptr(boxReg, Address(tmpReg, owner_offset)); | |
2070 testptr(boxReg, boxReg); | |
2071 jccb(Assembler::notZero, L_regular_inflated_unlock); | |
2072 xend(); | |
2073 jmpb(DONE_LABEL); | |
2074 bind(L_regular_inflated_unlock); | |
2075 } | |
2076 #endif | |
2077 | |
17714
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2078 // Despite our balanced locking property we still check that m->_owner == Self |
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2079 // as java routines or native JNI code called by this thread might |
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2080 // have released the lock. |
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2081 // Refer to the comments in synchronizer.cpp for how we might encode extra |
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2082 // state in _succ so we can avoid fetching EntryList|cxq. |
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2083 // |
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2084 // I'd like to add more cases in fast_lock() and fast_unlock() -- |
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2085 // such as recursive enter and exit -- but we have to be wary of |
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2086 // I$ bloat, T$ effects and BP$ effects. |
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2087 // |
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2088 // If there's no contention try a 1-0 exit. That is, exit without |
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2089 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how |
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2090 // we detect and recover from the race that the 1-0 exit admits. |
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2091 // |
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2092 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier |
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2093 // before it STs null into _owner, releasing the lock. Updates |
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2094 // to data protected by the critical section must be visible before |
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2095 // we drop the lock (and thus before any other thread could acquire |
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2096 // the lock and observe the fields protected by the lock). |
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2097 // IA32's memory-model is SPO, so STs are ordered with respect to |
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2098 // each other and there's no need for an explicit barrier (fence). |
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2099 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. |
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2100 #ifndef _LP64 |
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2101 get_thread (boxReg); |
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2102 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
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2103 // prefetchw [ebx + Offset(_owner)-2] |
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2104 prefetchw(Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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|
2105 } |
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|
2106 |
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|
2107 // Note that we could employ various encoding schemes to reduce |
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|
2108 // the number of loads below (currently 4) to just 2 or 3. |
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|
2109 // Refer to the comments in synchronizer.cpp. |
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2110 // In practice the chain of fetches doesn't seem to impact performance, however. |
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2111 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { |
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2112 // Attempt to reduce branch density - AMD's branch predictor. |
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|
2113 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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2114 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)); |
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2115 orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)); |
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2116 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)); |
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2117 jccb (Assembler::notZero, DONE_LABEL); |
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2118 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD); |
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2119 jmpb (DONE_LABEL); |
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|
2120 } else { |
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|
2121 xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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2122 orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)); |
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2123 jccb (Assembler::notZero, DONE_LABEL); |
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2124 movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)); |
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2125 orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)); |
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2126 jccb (Assembler::notZero, CheckSucc); |
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2127 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD); |
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|
2128 jmpb (DONE_LABEL); |
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|
2129 } |
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|
2130 |
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|
2131 // The Following code fragment (EmitSync & 65536) improves the performance of |
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|
2132 // contended applications and contended synchronization microbenchmarks. |
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|
2133 // Unfortunately the emission of the code - even though not executed - causes regressions |
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2134 // in scimark and jetstream, evidently because of $ effects. Replacing the code |
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|
2135 // with an equal number of never-executed NOPs results in the same regression. |
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|
2136 // We leave it off by default. |
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|
2137 |
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|
2138 if ((EmitSync & 65536) != 0) { |
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|
2139 Label LSuccess, LGoSlowPath ; |
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|
2140 |
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|
2141 bind (CheckSucc); |
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|
2142 |
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|
2143 // Optional pre-test ... it's safe to elide this |
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|
2144 if ((EmitSync & 16) == 0) { |
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|
2145 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD); |
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|
2146 jccb (Assembler::zero, LGoSlowPath); |
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|
2147 } |
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|
2148 |
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|
2149 // We have a classic Dekker-style idiom: |
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2150 // ST m->_owner = 0 ; MEMBAR; LD m->_succ |
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2151 // There are a number of ways to implement the barrier: |
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2152 // (1) lock:andl &m->_owner, 0 |
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2153 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. |
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2154 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 |
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2155 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 |
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2156 // (2) If supported, an explicit MFENCE is appealing. |
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2157 // In older IA32 processors MFENCE is slower than lock:add or xchg |
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2158 // particularly if the write-buffer is full as might be the case if |
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|
2159 // if stores closely precede the fence or fence-equivalent instruction. |
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2160 // In more modern implementations MFENCE appears faster, however. |
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2161 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack |
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2162 // The $lines underlying the top-of-stack should be in M-state. |
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|
2163 // The locked add instruction is serializing, of course. |
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2164 // (4) Use xchg, which is serializing |
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2165 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works |
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2166 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. |
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2167 // The integer condition codes will tell us if succ was 0. |
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|
2168 // Since _succ and _owner should reside in the same $line and |
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2169 // we just stored into _owner, it's likely that the $line |
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|
2170 // remains in M-state for the lock:orl. |
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2171 // |
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2172 // We currently use (3), although it's likely that switching to (2) |
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|
2173 // is correct for the future. |
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|
2174 |
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2175 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD); |
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2176 if (os::is_MP()) { |
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|
2177 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { |
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|
2178 mfence(); |
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|
2179 } else { |
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|
2180 lock (); addptr(Address(rsp, 0), 0); |
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|
2181 } |
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|
2182 } |
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|
2183 // Ratify _succ remains non-null |
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2184 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0); |
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|
2185 jccb (Assembler::notZero, LSuccess); |
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|
2186 |
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|
2187 xorptr(boxReg, boxReg); // box is really EAX |
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|
2188 if (os::is_MP()) { lock(); } |
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2189 cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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|
2190 jccb (Assembler::notEqual, LSuccess); |
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|
2191 // Since we're low on registers we installed rsp as a placeholding in _owner. |
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|
2192 // Now install Self over rsp. This is safe as we're transitioning from |
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|
2193 // non-null to non=null |
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|
2194 get_thread (boxReg); |
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|
2195 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg); |
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|
2196 // Intentional fall-through into LGoSlowPath ... |
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|
2197 |
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|
2198 bind (LGoSlowPath); |
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|
2199 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure |
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|
2200 jmpb (DONE_LABEL); |
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|
2201 |
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|
2202 bind (LSuccess); |
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|
2203 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success |
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|
2204 jmpb (DONE_LABEL); |
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|
2205 } |
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|
2206 |
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|
2207 bind (Stacked); |
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|
2208 // It's not inflated and it's not recursively stack-locked and it's not biased. |
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|
2209 // It must be stack-locked. |
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|
2210 // Try to reset the header to displaced header. |
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|
2211 // The "box" value on the stack is stable, so we can reload |
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|
2212 // and be assured we observe the same value as above. |
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|
2213 movptr(tmpReg, Address(boxReg, 0)); |
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|
2214 if (os::is_MP()) { |
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|
2215 lock(); |
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|
2216 } |
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|
2217 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
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|
2218 // Intention fall-thru into DONE_LABEL |
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|
2219 |
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|
2220 // DONE_LABEL is a hot target - we'd really like to place it at the |
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|
2221 // start of cache line by padding with NOPs. |
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|
2222 // See the AMD and Intel software optimization manuals for the |
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|
2223 // most efficient "long" NOP encodings. |
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|
2224 // Unfortunately none of our alignment mechanisms suffice. |
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|
2225 if ((EmitSync & 65536) == 0) { |
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|
2226 bind (CheckSucc); |
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|
2227 } |
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|
2228 #else // _LP64 |
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|
2229 // It's inflated |
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|
2230 movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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|
2231 xorptr(boxReg, r15_thread); |
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|
2232 orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)); |
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|
2233 jccb (Assembler::notZero, DONE_LABEL); |
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|
2234 movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)); |
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|
2235 orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)); |
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|
2236 jccb (Assembler::notZero, CheckSucc); |
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|
2237 movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD); |
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|
2238 jmpb (DONE_LABEL); |
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|
2239 |
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|
2240 if ((EmitSync & 65536) == 0) { |
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|
2241 Label LSuccess, LGoSlowPath ; |
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|
2242 bind (CheckSucc); |
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|
2243 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD); |
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|
2244 jccb (Assembler::zero, LGoSlowPath); |
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|
2245 |
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|
2246 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the |
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|
2247 // the explicit ST;MEMBAR combination, but masm doesn't currently support |
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|
2248 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc |
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|
2249 // are all faster when the write buffer is populated. |
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|
2250 movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD); |
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|
2251 if (os::is_MP()) { |
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|
2252 lock (); addl (Address(rsp, 0), 0); |
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|
2253 } |
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|
2254 cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD); |
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|
2255 jccb (Assembler::notZero, LSuccess); |
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|
2256 |
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|
2257 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX |
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|
2258 if (os::is_MP()) { lock(); } |
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2259 cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
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2260 jccb (Assembler::notEqual, LSuccess); |
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2261 // Intentional fall-through into slow-path |
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2262 |
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2263 bind (LGoSlowPath); |
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2264 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure |
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2265 jmpb (DONE_LABEL); |
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2266 |
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2267 bind (LSuccess); |
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2268 testl (boxReg, 0); // set ICC.ZF=1 to indicate success |
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2269 jmpb (DONE_LABEL); |
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2270 } |
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2271 |
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2272 bind (Stacked); |
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2273 movptr(tmpReg, Address (boxReg, 0)); // re-fetch |
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2274 if (os::is_MP()) { lock(); } |
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2275 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
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2276 |
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2277 if (EmitSync & 65536) { |
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2278 bind (CheckSucc); |
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2279 } |
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2280 #endif |
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2281 bind(DONE_LABEL); |
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2282 // Avoid branch to branch on AMD processors |
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2283 if (EmitSync & 32768) { |
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2284 nop(); |
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2285 } |
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2286 } |
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2287 } |
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2288 #endif // COMPILER2 |
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2289 |
7199 | 2290 void MacroAssembler::c2bool(Register x) { |
2291 // implements x == 0 ? 0 : 1 | |
2292 // note: must only look at least-significant byte of x | |
2293 // since C-style booleans are stored in one byte | |
2294 // only! (was bug) | |
2295 andl(x, 0xFF); | |
2296 setb(Assembler::notZero, x); | |
2297 } | |
2298 | |
2299 // Wouldn't need if AddressLiteral version had new name | |
2300 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
2301 Assembler::call(L, rtype); | |
2302 } | |
2303 | |
2304 void MacroAssembler::call(Register entry) { | |
2305 Assembler::call(entry); | |
2306 } | |
2307 | |
2308 void MacroAssembler::call(AddressLiteral entry) { | |
2309 if (reachable(entry)) { | |
2310 Assembler::call_literal(entry.target(), entry.rspec()); | |
2311 } else { | |
2312 lea(rscratch1, entry); | |
2313 Assembler::call(rscratch1); | |
2314 } | |
2315 } | |
2316 | |
2317 void MacroAssembler::ic_call(address entry) { | |
2318 RelocationHolder rh = virtual_call_Relocation::spec(pc()); | |
2319 movptr(rax, (intptr_t)Universe::non_oop_word()); | |
2320 call(AddressLiteral(entry, rh)); | |
2321 } | |
2322 | |
2323 // Implementation of call_VM versions | |
2324 | |
2325 void MacroAssembler::call_VM(Register oop_result, | |
2326 address entry_point, | |
2327 bool check_exceptions) { | |
2328 Label C, E; | |
2329 call(C, relocInfo::none); | |
2330 jmp(E); | |
2331 | |
2332 bind(C); | |
2333 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
2334 ret(0); | |
2335 | |
2336 bind(E); | |
2337 } | |
2338 | |
2339 void MacroAssembler::call_VM(Register oop_result, | |
2340 address entry_point, | |
2341 Register arg_1, | |
2342 bool check_exceptions) { | |
2343 Label C, E; | |
2344 call(C, relocInfo::none); | |
2345 jmp(E); | |
2346 | |
2347 bind(C); | |
2348 pass_arg1(this, arg_1); | |
2349 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
2350 ret(0); | |
2351 | |
2352 bind(E); | |
2353 } | |
2354 | |
2355 void MacroAssembler::call_VM(Register oop_result, | |
2356 address entry_point, | |
2357 Register arg_1, | |
2358 Register arg_2, | |
2359 bool check_exceptions) { | |
2360 Label C, E; | |
2361 call(C, relocInfo::none); | |
2362 jmp(E); | |
2363 | |
2364 bind(C); | |
2365 | |
2366 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2367 | |
2368 pass_arg2(this, arg_2); | |
2369 pass_arg1(this, arg_1); | |
2370 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
2371 ret(0); | |
2372 | |
2373 bind(E); | |
2374 } | |
2375 | |
2376 void MacroAssembler::call_VM(Register oop_result, | |
2377 address entry_point, | |
2378 Register arg_1, | |
2379 Register arg_2, | |
2380 Register arg_3, | |
2381 bool check_exceptions) { | |
2382 Label C, E; | |
2383 call(C, relocInfo::none); | |
2384 jmp(E); | |
2385 | |
2386 bind(C); | |
2387 | |
2388 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
2389 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
2390 pass_arg3(this, arg_3); | |
2391 | |
2392 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2393 pass_arg2(this, arg_2); | |
2394 | |
2395 pass_arg1(this, arg_1); | |
2396 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
2397 ret(0); | |
2398 | |
2399 bind(E); | |
2400 } | |
2401 | |
2402 void MacroAssembler::call_VM(Register oop_result, | |
2403 Register last_java_sp, | |
2404 address entry_point, | |
2405 int number_of_arguments, | |
2406 bool check_exceptions) { | |
2407 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
2408 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
2409 } | |
2410 | |
2411 void MacroAssembler::call_VM(Register oop_result, | |
2412 Register last_java_sp, | |
2413 address entry_point, | |
2414 Register arg_1, | |
2415 bool check_exceptions) { | |
2416 pass_arg1(this, arg_1); | |
2417 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
2418 } | |
2419 | |
2420 void MacroAssembler::call_VM(Register oop_result, | |
2421 Register last_java_sp, | |
2422 address entry_point, | |
2423 Register arg_1, | |
2424 Register arg_2, | |
2425 bool check_exceptions) { | |
2426 | |
2427 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2428 pass_arg2(this, arg_2); | |
2429 pass_arg1(this, arg_1); | |
2430 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
2431 } | |
2432 | |
2433 void MacroAssembler::call_VM(Register oop_result, | |
2434 Register last_java_sp, | |
2435 address entry_point, | |
2436 Register arg_1, | |
2437 Register arg_2, | |
2438 Register arg_3, | |
2439 bool check_exceptions) { | |
2440 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
2441 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
2442 pass_arg3(this, arg_3); | |
2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2444 pass_arg2(this, arg_2); | |
2445 pass_arg1(this, arg_1); | |
2446 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
2447 } | |
2448 | |
2449 void MacroAssembler::super_call_VM(Register oop_result, | |
2450 Register last_java_sp, | |
2451 address entry_point, | |
2452 int number_of_arguments, | |
2453 bool check_exceptions) { | |
2454 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
2455 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
2456 } | |
2457 | |
2458 void MacroAssembler::super_call_VM(Register oop_result, | |
2459 Register last_java_sp, | |
2460 address entry_point, | |
2461 Register arg_1, | |
2462 bool check_exceptions) { | |
2463 pass_arg1(this, arg_1); | |
2464 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
2465 } | |
2466 | |
2467 void MacroAssembler::super_call_VM(Register oop_result, | |
2468 Register last_java_sp, | |
2469 address entry_point, | |
2470 Register arg_1, | |
2471 Register arg_2, | |
2472 bool check_exceptions) { | |
2473 | |
2474 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2475 pass_arg2(this, arg_2); | |
2476 pass_arg1(this, arg_1); | |
2477 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
2478 } | |
2479 | |
2480 void MacroAssembler::super_call_VM(Register oop_result, | |
2481 Register last_java_sp, | |
2482 address entry_point, | |
2483 Register arg_1, | |
2484 Register arg_2, | |
2485 Register arg_3, | |
2486 bool check_exceptions) { | |
2487 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
2488 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
2489 pass_arg3(this, arg_3); | |
2490 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2491 pass_arg2(this, arg_2); | |
2492 pass_arg1(this, arg_1); | |
2493 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
2494 } | |
2495 | |
2496 void MacroAssembler::call_VM_base(Register oop_result, | |
2497 Register java_thread, | |
2498 Register last_java_sp, | |
2499 address entry_point, | |
2500 int number_of_arguments, | |
2501 bool check_exceptions) { | |
2502 // determine java_thread register | |
2503 if (!java_thread->is_valid()) { | |
2504 #ifdef _LP64 | |
2505 java_thread = r15_thread; | |
2506 #else | |
2507 java_thread = rdi; | |
2508 get_thread(java_thread); | |
2509 #endif // LP64 | |
2510 } | |
2511 // determine last_java_sp register | |
2512 if (!last_java_sp->is_valid()) { | |
2513 last_java_sp = rsp; | |
2514 } | |
2515 // debugging support | |
2516 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
2517 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
2518 #ifdef ASSERT | |
2519 // TraceBytecodes does not use r12 but saves it over the call, so don't verify | |
2520 // r12 is the heapbase. | |
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2521 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) |
7199 | 2522 #endif // ASSERT |
2523 | |
2524 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); | |
2525 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
2526 | |
2527 // push java thread (becomes first argument of C function) | |
2528 | |
2529 NOT_LP64(push(java_thread); number_of_arguments++); | |
2530 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
2531 | |
2532 // set last Java frame before call | |
2533 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
2534 | |
2535 // Only interpreter should have to set fp | |
2536 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
2537 | |
2538 // do the call, remove parameters | |
2539 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
2540 | |
2541 // restore the thread (cannot use the pushed argument since arguments | |
2542 // may be overwritten by C code generated by an optimizing compiler); | |
2543 // however can use the register value directly if it is callee saved. | |
2544 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
2545 // rdi & rsi (also r15) are callee saved -> nothing to do | |
2546 #ifdef ASSERT | |
2547 guarantee(java_thread != rax, "change this code"); | |
2548 push(rax); | |
2549 { Label L; | |
2550 get_thread(rax); | |
2551 cmpptr(java_thread, rax); | |
2552 jcc(Assembler::equal, L); | |
2553 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
2554 bind(L); | |
2555 } | |
2556 pop(rax); | |
2557 #endif | |
2558 } else { | |
2559 get_thread(java_thread); | |
2560 } | |
2561 // reset last Java frame | |
2562 // Only interpreter should have to clear fp | |
2563 reset_last_Java_frame(java_thread, true, false); | |
2564 | |
2565 #ifndef CC_INTERP | |
2566 // C++ interp handles this in the interpreter | |
2567 check_and_handle_popframe(java_thread); | |
2568 check_and_handle_earlyret(java_thread); | |
2569 #endif /* CC_INTERP */ | |
2570 | |
2571 if (check_exceptions) { | |
2572 // check for pending exceptions (java_thread is set upon return) | |
2573 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
2574 #ifndef _LP64 | |
2575 jump_cc(Assembler::notEqual, | |
2576 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
2577 #else | |
2578 // This used to conditionally jump to forward_exception however it is | |
2579 // possible if we relocate that the branch will not reach. So we must jump | |
2580 // around so we can always reach | |
2581 | |
2582 Label ok; | |
2583 jcc(Assembler::equal, ok); | |
2584 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
2585 bind(ok); | |
2586 #endif // LP64 | |
2587 } | |
2588 | |
2589 // get oop result if there is one and reset the value in the thread | |
2590 if (oop_result->is_valid()) { | |
2591 get_vm_result(oop_result, java_thread); | |
2592 } | |
2593 } | |
2594 | |
2595 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
2596 | |
2597 // Calculate the value for last_Java_sp | |
2598 // somewhat subtle. call_VM does an intermediate call | |
2599 // which places a return address on the stack just under the | |
2600 // stack pointer as the user finsihed with it. This allows | |
2601 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
2602 // On 32bit we then have to push additional args on the stack to accomplish | |
2603 // the actual requested call. On 64bit call_VM only can use register args | |
2604 // so the only extra space is the return address that call_VM created. | |
2605 // This hopefully explains the calculations here. | |
2606 | |
2607 #ifdef _LP64 | |
2608 // We've pushed one address, correct last_Java_sp | |
2609 lea(rax, Address(rsp, wordSize)); | |
2610 #else | |
2611 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
2612 #endif // LP64 | |
2613 | |
2614 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
2615 | |
2616 } | |
2617 | |
2618 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
2619 call_VM_leaf_base(entry_point, number_of_arguments); | |
2620 } | |
2621 | |
2622 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
2623 pass_arg0(this, arg_0); | |
2624 call_VM_leaf(entry_point, 1); | |
2625 } | |
2626 | |
2627 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
2628 | |
2629 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
2630 pass_arg1(this, arg_1); | |
2631 pass_arg0(this, arg_0); | |
2632 call_VM_leaf(entry_point, 2); | |
2633 } | |
2634 | |
2635 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
2636 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
2637 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2638 pass_arg2(this, arg_2); | |
2639 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
2640 pass_arg1(this, arg_1); | |
2641 pass_arg0(this, arg_0); | |
2642 call_VM_leaf(entry_point, 3); | |
2643 } | |
2644 | |
2645 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { | |
2646 pass_arg0(this, arg_0); | |
2647 MacroAssembler::call_VM_leaf_base(entry_point, 1); | |
2648 } | |
2649 | |
2650 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
2651 | |
2652 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
2653 pass_arg1(this, arg_1); | |
2654 pass_arg0(this, arg_0); | |
2655 MacroAssembler::call_VM_leaf_base(entry_point, 2); | |
2656 } | |
2657 | |
2658 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
2659 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
2660 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2661 pass_arg2(this, arg_2); | |
2662 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
2663 pass_arg1(this, arg_1); | |
2664 pass_arg0(this, arg_0); | |
2665 MacroAssembler::call_VM_leaf_base(entry_point, 3); | |
2666 } | |
2667 | |
2668 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { | |
2669 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); | |
2670 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
2671 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
2672 pass_arg3(this, arg_3); | |
2673 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
2674 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
2675 pass_arg2(this, arg_2); | |
2676 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
2677 pass_arg1(this, arg_1); | |
2678 pass_arg0(this, arg_0); | |
2679 MacroAssembler::call_VM_leaf_base(entry_point, 4); | |
2680 } | |
2681 | |
2682 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { | |
2683 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
2684 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); | |
2685 verify_oop(oop_result, "broken oop in call_VM_base"); | |
2686 } | |
2687 | |
2688 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { | |
2689 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); | |
2690 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); | |
2691 } | |
2692 | |
2693 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
2694 } | |
2695 | |
2696 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
2697 } | |
2698 | |
2699 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
2700 if (reachable(src1)) { | |
2701 cmpl(as_Address(src1), imm); | |
2702 } else { | |
2703 lea(rscratch1, src1); | |
2704 cmpl(Address(rscratch1, 0), imm); | |
2705 } | |
2706 } | |
2707 | |
2708 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
2709 assert(!src2.is_lval(), "use cmpptr"); | |
2710 if (reachable(src2)) { | |
2711 cmpl(src1, as_Address(src2)); | |
2712 } else { | |
2713 lea(rscratch1, src2); | |
2714 cmpl(src1, Address(rscratch1, 0)); | |
2715 } | |
2716 } | |
2717 | |
2718 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
2719 Assembler::cmpl(src1, imm); | |
2720 } | |
2721 | |
2722 void MacroAssembler::cmp32(Register src1, Address src2) { | |
2723 Assembler::cmpl(src1, src2); | |
2724 } | |
2725 | |
2726 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
2727 ucomisd(opr1, opr2); | |
2728 | |
2729 Label L; | |
2730 if (unordered_is_less) { | |
2731 movl(dst, -1); | |
2732 jcc(Assembler::parity, L); | |
2733 jcc(Assembler::below , L); | |
2734 movl(dst, 0); | |
2735 jcc(Assembler::equal , L); | |
2736 increment(dst); | |
2737 } else { // unordered is greater | |
2738 movl(dst, 1); | |
2739 jcc(Assembler::parity, L); | |
2740 jcc(Assembler::above , L); | |
2741 movl(dst, 0); | |
2742 jcc(Assembler::equal , L); | |
2743 decrementl(dst); | |
2744 } | |
2745 bind(L); | |
2746 } | |
2747 | |
2748 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
2749 ucomiss(opr1, opr2); | |
2750 | |
2751 Label L; | |
2752 if (unordered_is_less) { | |
2753 movl(dst, -1); | |
2754 jcc(Assembler::parity, L); | |
2755 jcc(Assembler::below , L); | |
2756 movl(dst, 0); | |
2757 jcc(Assembler::equal , L); | |
2758 increment(dst); | |
2759 } else { // unordered is greater | |
2760 movl(dst, 1); | |
2761 jcc(Assembler::parity, L); | |
2762 jcc(Assembler::above , L); | |
2763 movl(dst, 0); | |
2764 jcc(Assembler::equal , L); | |
2765 decrementl(dst); | |
2766 } | |
2767 bind(L); | |
2768 } | |
2769 | |
2770 | |
2771 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
2772 if (reachable(src1)) { | |
2773 cmpb(as_Address(src1), imm); | |
2774 } else { | |
2775 lea(rscratch1, src1); | |
2776 cmpb(Address(rscratch1, 0), imm); | |
2777 } | |
2778 } | |
2779 | |
2780 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
2781 #ifdef _LP64 | |
2782 if (src2.is_lval()) { | |
2783 movptr(rscratch1, src2); | |
2784 Assembler::cmpq(src1, rscratch1); | |
2785 } else if (reachable(src2)) { | |
2786 cmpq(src1, as_Address(src2)); | |
2787 } else { | |
2788 lea(rscratch1, src2); | |
2789 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
2790 } | |
2791 #else | |
2792 if (src2.is_lval()) { | |
2793 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
2794 } else { | |
2795 cmpl(src1, as_Address(src2)); | |
2796 } | |
2797 #endif // _LP64 | |
2798 } | |
2799 | |
2800 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
2801 assert(src2.is_lval(), "not a mem-mem compare"); | |
2802 #ifdef _LP64 | |
2803 // moves src2's literal address | |
2804 movptr(rscratch1, src2); | |
2805 Assembler::cmpq(src1, rscratch1); | |
2806 #else | |
2807 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
2808 #endif // _LP64 | |
2809 } | |
2810 | |
2811 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
2812 if (reachable(adr)) { | |
2813 if (os::is_MP()) | |
2814 lock(); | |
2815 cmpxchgptr(reg, as_Address(adr)); | |
2816 } else { | |
2817 lea(rscratch1, adr); | |
2818 if (os::is_MP()) | |
2819 lock(); | |
2820 cmpxchgptr(reg, Address(rscratch1, 0)); | |
2821 } | |
2822 } | |
2823 | |
2824 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
2825 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
2826 } | |
2827 | |
2828 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
2829 if (reachable(src)) { | |
2830 Assembler::comisd(dst, as_Address(src)); | |
2831 } else { | |
2832 lea(rscratch1, src); | |
2833 Assembler::comisd(dst, Address(rscratch1, 0)); | |
2834 } | |
2835 } | |
2836 | |
2837 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
2838 if (reachable(src)) { | |
2839 Assembler::comiss(dst, as_Address(src)); | |
2840 } else { | |
2841 lea(rscratch1, src); | |
2842 Assembler::comiss(dst, Address(rscratch1, 0)); | |
2843 } | |
2844 } | |
2845 | |
2846 | |
2847 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
2848 Condition negated_cond = negate_condition(cond); | |
2849 Label L; | |
2850 jcc(negated_cond, L); | |
17780 | 2851 pushf(); // Preserve flags |
7199 | 2852 atomic_incl(counter_addr); |
17780 | 2853 popf(); |
7199 | 2854 bind(L); |
2855 } | |
2856 | |
2857 int MacroAssembler::corrected_idivl(Register reg) { | |
2858 // Full implementation of Java idiv and irem; checks for | |
2859 // special case as described in JVM spec., p.243 & p.271. | |
2860 // The function returns the (pc) offset of the idivl | |
2861 // instruction - may be needed for implicit exceptions. | |
2862 // | |
2863 // normal case special case | |
2864 // | |
2865 // input : rax,: dividend min_int | |
2866 // reg: divisor (may not be rax,/rdx) -1 | |
2867 // | |
2868 // output: rax,: quotient (= rax, idiv reg) min_int | |
2869 // rdx: remainder (= rax, irem reg) 0 | |
2870 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
2871 const int min_int = 0x80000000; | |
2872 Label normal_case, special_case; | |
2873 | |
2874 // check for special case | |
2875 cmpl(rax, min_int); | |
2876 jcc(Assembler::notEqual, normal_case); | |
2877 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
2878 cmpl(reg, -1); | |
2879 jcc(Assembler::equal, special_case); | |
2880 | |
2881 // handle normal case | |
2882 bind(normal_case); | |
2883 cdql(); | |
2884 int idivl_offset = offset(); | |
2885 idivl(reg); | |
2886 | |
2887 // normal and special case exit | |
2888 bind(special_case); | |
2889 | |
2890 return idivl_offset; | |
2891 } | |
2892 | |
2893 | |
2894 | |
2895 void MacroAssembler::decrementl(Register reg, int value) { | |
2896 if (value == min_jint) {subl(reg, value) ; return; } | |
2897 if (value < 0) { incrementl(reg, -value); return; } | |
2898 if (value == 0) { ; return; } | |
2899 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
2900 /* else */ { subl(reg, value) ; return; } | |
2901 } | |
2902 | |
2903 void MacroAssembler::decrementl(Address dst, int value) { | |
2904 if (value == min_jint) {subl(dst, value) ; return; } | |
2905 if (value < 0) { incrementl(dst, -value); return; } | |
2906 if (value == 0) { ; return; } | |
2907 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
2908 /* else */ { subl(dst, value) ; return; } | |
2909 } | |
2910 | |
2911 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
2912 assert (shift_value > 0, "illegal shift value"); | |
2913 Label _is_positive; | |
2914 testl (reg, reg); | |
2915 jcc (Assembler::positive, _is_positive); | |
2916 int offset = (1 << shift_value) - 1 ; | |
2917 | |
2918 if (offset == 1) { | |
2919 incrementl(reg); | |
2920 } else { | |
2921 addl(reg, offset); | |
2922 } | |
2923 | |
2924 bind (_is_positive); | |
2925 sarl(reg, shift_value); | |
2926 } | |
2927 | |
2928 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { | |
2929 if (reachable(src)) { | |
2930 Assembler::divsd(dst, as_Address(src)); | |
2931 } else { | |
2932 lea(rscratch1, src); | |
2933 Assembler::divsd(dst, Address(rscratch1, 0)); | |
2934 } | |
2935 } | |
2936 | |
2937 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { | |
2938 if (reachable(src)) { | |
2939 Assembler::divss(dst, as_Address(src)); | |
2940 } else { | |
2941 lea(rscratch1, src); | |
2942 Assembler::divss(dst, Address(rscratch1, 0)); | |
2943 } | |
2944 } | |
2945 | |
2946 // !defined(COMPILER2) is because of stupid core builds | |
2947 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
2948 void MacroAssembler::empty_FPU_stack() { | |
2949 if (VM_Version::supports_mmx()) { | |
2950 emms(); | |
2951 } else { | |
2952 for (int i = 8; i-- > 0; ) ffree(i); | |
2953 } | |
2954 } | |
2955 #endif // !LP64 || C1 || !C2 | |
2956 | |
2957 | |
2958 // Defines obj, preserves var_size_in_bytes | |
2959 void MacroAssembler::eden_allocate(Register obj, | |
2960 Register var_size_in_bytes, | |
2961 int con_size_in_bytes, | |
2962 Register t1, | |
2963 Label& slow_case) { | |
2964 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
2965 assert_different_registers(obj, var_size_in_bytes, t1); | |
2966 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
2967 jmp(slow_case); | |
2968 } else { | |
2969 Register end = t1; | |
2970 Label retry; | |
2971 bind(retry); | |
2972 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
2973 movptr(obj, heap_top); | |
2974 if (var_size_in_bytes == noreg) { | |
2975 lea(end, Address(obj, con_size_in_bytes)); | |
2976 } else { | |
2977 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
2978 } | |
2979 // if end < obj then we wrapped around => object too long => slow case | |
2980 cmpptr(end, obj); | |
2981 jcc(Assembler::below, slow_case); | |
2982 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
2983 jcc(Assembler::above, slow_case); | |
2984 // Compare obj with the top addr, and if still equal, store the new top addr in | |
2985 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
2986 // it otherwise. Use lock prefix for atomicity on MPs. | |
2987 locked_cmpxchgptr(end, heap_top); | |
2988 jcc(Assembler::notEqual, retry); | |
2989 } | |
2990 } | |
2991 | |
2992 void MacroAssembler::enter() { | |
2993 push(rbp); | |
2994 mov(rbp, rsp); | |
2995 } | |
2996 | |
2997 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
2998 void MacroAssembler::fat_nop() { | |
2999 if (UseAddressNop) { | |
3000 addr_nop_5(); | |
3001 } else { | |
7430
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|
3002 emit_int8(0x26); // es: |
d02120b7a34f
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7427
diff
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|
3003 emit_int8(0x2e); // cs: |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
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|
3004 emit_int8(0x64); // fs: |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
3005 emit_int8(0x65); // gs: |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
3006 emit_int8((unsigned char)0x90); |
7199 | 3007 } |
3008 } | |
3009 | |
3010 void MacroAssembler::fcmp(Register tmp) { | |
3011 fcmp(tmp, 1, true, true); | |
3012 } | |
3013 | |
3014 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
3015 assert(!pop_right || pop_left, "usage error"); | |
3016 if (VM_Version::supports_cmov()) { | |
3017 assert(tmp == noreg, "unneeded temp"); | |
3018 if (pop_left) { | |
3019 fucomip(index); | |
3020 } else { | |
3021 fucomi(index); | |
3022 } | |
3023 if (pop_right) { | |
3024 fpop(); | |
3025 } | |
3026 } else { | |
3027 assert(tmp != noreg, "need temp"); | |
3028 if (pop_left) { | |
3029 if (pop_right) { | |
3030 fcompp(); | |
3031 } else { | |
3032 fcomp(index); | |
3033 } | |
3034 } else { | |
3035 fcom(index); | |
3036 } | |
3037 // convert FPU condition into eflags condition via rax, | |
3038 save_rax(tmp); | |
3039 fwait(); fnstsw_ax(); | |
3040 sahf(); | |
3041 restore_rax(tmp); | |
3042 } | |
3043 // condition codes set as follows: | |
3044 // | |
3045 // CF (corresponds to C0) if x < y | |
3046 // PF (corresponds to C2) if unordered | |
3047 // ZF (corresponds to C3) if x = y | |
3048 } | |
3049 | |
3050 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
3051 fcmp2int(dst, unordered_is_less, 1, true, true); | |
3052 } | |
3053 | |
3054 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
3055 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
3056 Label L; | |
3057 if (unordered_is_less) { | |
3058 movl(dst, -1); | |
3059 jcc(Assembler::parity, L); | |
3060 jcc(Assembler::below , L); | |
3061 movl(dst, 0); | |
3062 jcc(Assembler::equal , L); | |
3063 increment(dst); | |
3064 } else { // unordered is greater | |
3065 movl(dst, 1); | |
3066 jcc(Assembler::parity, L); | |
3067 jcc(Assembler::above , L); | |
3068 movl(dst, 0); | |
3069 jcc(Assembler::equal , L); | |
3070 decrementl(dst); | |
3071 } | |
3072 bind(L); | |
3073 } | |
3074 | |
3075 void MacroAssembler::fld_d(AddressLiteral src) { | |
3076 fld_d(as_Address(src)); | |
3077 } | |
3078 | |
3079 void MacroAssembler::fld_s(AddressLiteral src) { | |
3080 fld_s(as_Address(src)); | |
3081 } | |
3082 | |
3083 void MacroAssembler::fld_x(AddressLiteral src) { | |
3084 Assembler::fld_x(as_Address(src)); | |
3085 } | |
3086 | |
3087 void MacroAssembler::fldcw(AddressLiteral src) { | |
3088 Assembler::fldcw(as_Address(src)); | |
3089 } | |
3090 | |
3091 void MacroAssembler::pow_exp_core_encoding() { | |
3092 // kills rax, rcx, rdx | |
3093 subptr(rsp,sizeof(jdouble)); | |
3094 // computes 2^X. Stack: X ... | |
3095 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and | |
3096 // keep it on the thread's stack to compute 2^int(X) later | |
3097 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1) | |
3098 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X)) | |
3099 fld_s(0); // Stack: X X ... | |
3100 frndint(); // Stack: int(X) X ... | |
3101 fsuba(1); // Stack: int(X) X-int(X) ... | |
3102 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ... | |
3103 f2xm1(); // Stack: 2^(X-int(X))-1 ... | |
3104 fld1(); // Stack: 1 2^(X-int(X))-1 ... | |
3105 faddp(1); // Stack: 2^(X-int(X)) | |
3106 // computes 2^(int(X)): add exponent bias (1023) to int(X), then | |
3107 // shift int(X)+1023 to exponent position. | |
3108 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11 | |
3109 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent | |
3110 // values so detect them and set result to NaN. | |
3111 movl(rax,Address(rsp,0)); | |
3112 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding | |
3113 addl(rax, 1023); | |
3114 movl(rdx,rax); | |
3115 shll(rax,20); | |
3116 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN. | |
3117 addl(rdx,1); | |
3118 // Check that 1 < int(X)+1023+1 < 2048 | |
3119 // in 3 steps: | |
3120 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048 | |
3121 // 2- (int(X)+1023+1)&-2048 != 0 | |
3122 // 3- (int(X)+1023+1)&-2048 != 1 | |
3123 // Do 2- first because addl just updated the flags. | |
3124 cmov32(Assembler::equal,rax,rcx); | |
3125 cmpl(rdx,1); | |
3126 cmov32(Assembler::equal,rax,rcx); | |
3127 testl(rdx,rcx); | |
3128 cmov32(Assembler::notEqual,rax,rcx); | |
3129 movl(Address(rsp,4),rax); | |
3130 movl(Address(rsp,0),0); | |
3131 fmul_d(Address(rsp,0)); // Stack: 2^X ... | |
3132 addptr(rsp,sizeof(jdouble)); | |
3133 } | |
3134 | |
3135 void MacroAssembler::increase_precision() { | |
3136 subptr(rsp, BytesPerWord); | |
3137 fnstcw(Address(rsp, 0)); | |
3138 movl(rax, Address(rsp, 0)); | |
3139 orl(rax, 0x300); | |
3140 push(rax); | |
3141 fldcw(Address(rsp, 0)); | |
3142 pop(rax); | |
3143 } | |
3144 | |
3145 void MacroAssembler::restore_precision() { | |
3146 fldcw(Address(rsp, 0)); | |
3147 addptr(rsp, BytesPerWord); | |
3148 } | |
3149 | |
3150 void MacroAssembler::fast_pow() { | |
3151 // computes X^Y = 2^(Y * log2(X)) | |
3152 // if fast computation is not possible, result is NaN. Requires | |
3153 // fallback from user of this macro. | |
3154 // increase precision for intermediate steps of the computation | |
3155 increase_precision(); | |
3156 fyl2x(); // Stack: (Y*log2(X)) ... | |
3157 pow_exp_core_encoding(); // Stack: exp(X) ... | |
3158 restore_precision(); | |
3159 } | |
3160 | |
3161 void MacroAssembler::fast_exp() { | |
3162 // computes exp(X) = 2^(X * log2(e)) | |
3163 // if fast computation is not possible, result is NaN. Requires | |
3164 // fallback from user of this macro. | |
3165 // increase precision for intermediate steps of the computation | |
3166 increase_precision(); | |
3167 fldl2e(); // Stack: log2(e) X ... | |
3168 fmulp(1); // Stack: (X*log2(e)) ... | |
3169 pow_exp_core_encoding(); // Stack: exp(X) ... | |
3170 restore_precision(); | |
3171 } | |
3172 | |
3173 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) { | |
3174 // kills rax, rcx, rdx | |
3175 // pow and exp needs 2 extra registers on the fpu stack. | |
3176 Label slow_case, done; | |
3177 Register tmp = noreg; | |
3178 if (!VM_Version::supports_cmov()) { | |
3179 // fcmp needs a temporary so preserve rdx, | |
3180 tmp = rdx; | |
3181 } | |
3182 Register tmp2 = rax; | |
3183 Register tmp3 = rcx; | |
3184 | |
3185 if (is_exp) { | |
3186 // Stack: X | |
3187 fld_s(0); // duplicate argument for runtime call. Stack: X X | |
3188 fast_exp(); // Stack: exp(X) X | |
3189 fcmp(tmp, 0, false, false); // Stack: exp(X) X | |
3190 // exp(X) not equal to itself: exp(X) is NaN go to slow case. | |
3191 jcc(Assembler::parity, slow_case); | |
3192 // get rid of duplicate argument. Stack: exp(X) | |
3193 if (num_fpu_regs_in_use > 0) { | |
3194 fxch(); | |
3195 fpop(); | |
3196 } else { | |
3197 ffree(1); | |
3198 } | |
3199 jmp(done); | |
3200 } else { | |
3201 // Stack: X Y | |
3202 Label x_negative, y_odd; | |
3203 | |
3204 fldz(); // Stack: 0 X Y | |
3205 fcmp(tmp, 1, true, false); // Stack: X Y | |
3206 jcc(Assembler::above, x_negative); | |
3207 | |
3208 // X >= 0 | |
3209 | |
3210 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y | |
3211 fld_s(1); // Stack: X Y X Y | |
3212 fast_pow(); // Stack: X^Y X Y | |
3213 fcmp(tmp, 0, false, false); // Stack: X^Y X Y | |
3214 // X^Y not equal to itself: X^Y is NaN go to slow case. | |
3215 jcc(Assembler::parity, slow_case); | |
3216 // get rid of duplicate arguments. Stack: X^Y | |
3217 if (num_fpu_regs_in_use > 0) { | |
3218 fxch(); fpop(); | |
3219 fxch(); fpop(); | |
3220 } else { | |
3221 ffree(2); | |
3222 ffree(1); | |
3223 } | |
3224 jmp(done); | |
3225 | |
3226 // X <= 0 | |
3227 bind(x_negative); | |
3228 | |
3229 fld_s(1); // Stack: Y X Y | |
3230 frndint(); // Stack: int(Y) X Y | |
3231 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y | |
3232 jcc(Assembler::notEqual, slow_case); | |
3233 | |
3234 subptr(rsp, 8); | |
3235 | |
3236 // For X^Y, when X < 0, Y has to be an integer and the final | |
3237 // result depends on whether it's odd or even. We just checked | |
3238 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit | |
3239 // integer to test its parity. If int(Y) is huge and doesn't fit | |
3240 // in the 64 bit integer range, the integer indefinite value will | |
3241 // end up in the gp registers. Huge numbers are all even, the | |
3242 // integer indefinite number is even so it's fine. | |
3243 | |
3244 #ifdef ASSERT | |
3245 // Let's check we don't end up with an integer indefinite number | |
3246 // when not expected. First test for huge numbers: check whether | |
3247 // int(Y)+1 == int(Y) which is true for very large numbers and | |
3248 // those are all even. A 64 bit integer is guaranteed to not | |
3249 // overflow for numbers where y+1 != y (when precision is set to | |
3250 // double precision). | |
3251 Label y_not_huge; | |
3252 | |
3253 fld1(); // Stack: 1 int(Y) X Y | |
3254 fadd(1); // Stack: 1+int(Y) int(Y) X Y | |
3255 | |
3256 #ifdef _LP64 | |
3257 // trip to memory to force the precision down from double extended | |
3258 // precision | |
3259 fstp_d(Address(rsp, 0)); | |
3260 fld_d(Address(rsp, 0)); | |
3261 #endif | |
3262 | |
3263 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y | |
3264 #endif | |
3265 | |
3266 // move int(Y) as 64 bit integer to thread's stack | |
3267 fistp_d(Address(rsp,0)); // Stack: X Y | |
3268 | |
3269 #ifdef ASSERT | |
3270 jcc(Assembler::notEqual, y_not_huge); | |
3271 | |
3272 // Y is huge so we know it's even. It may not fit in a 64 bit | |
3273 // integer and we don't want the debug code below to see the | |
3274 // integer indefinite value so overwrite int(Y) on the thread's | |
3275 // stack with 0. | |
3276 movl(Address(rsp, 0), 0); | |
3277 movl(Address(rsp, 4), 0); | |
3278 | |
3279 bind(y_not_huge); | |
3280 #endif | |
3281 | |
3282 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y | |
3283 fld_s(1); // Stack: X Y X Y | |
3284 fabs(); // Stack: abs(X) Y X Y | |
3285 fast_pow(); // Stack: abs(X)^Y X Y | |
3286 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y | |
3287 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case. | |
3288 | |
3289 pop(tmp2); | |
3290 NOT_LP64(pop(tmp3)); | |
3291 jcc(Assembler::parity, slow_case); | |
3292 | |
3293 #ifdef ASSERT | |
3294 // Check that int(Y) is not integer indefinite value (int | |
3295 // overflow). Shouldn't happen because for values that would | |
3296 // overflow, 1+int(Y)==Y which was tested earlier. | |
3297 #ifndef _LP64 | |
3298 { | |
3299 Label integer; | |
3300 testl(tmp2, tmp2); | |
3301 jcc(Assembler::notZero, integer); | |
3302 cmpl(tmp3, 0x80000000); | |
3303 jcc(Assembler::notZero, integer); | |
3304 STOP("integer indefinite value shouldn't be seen here"); | |
3305 bind(integer); | |
3306 } | |
3307 #else | |
3308 { | |
3309 Label integer; | |
3310 mov(tmp3, tmp2); // preserve tmp2 for parity check below | |
3311 shlq(tmp3, 1); | |
3312 jcc(Assembler::carryClear, integer); | |
3313 jcc(Assembler::notZero, integer); | |
3314 STOP("integer indefinite value shouldn't be seen here"); | |
3315 bind(integer); | |
3316 } | |
3317 #endif | |
3318 #endif | |
3319 | |
3320 // get rid of duplicate arguments. Stack: X^Y | |
3321 if (num_fpu_regs_in_use > 0) { | |
3322 fxch(); fpop(); | |
3323 fxch(); fpop(); | |
3324 } else { | |
3325 ffree(2); | |
3326 ffree(1); | |
3327 } | |
3328 | |
3329 testl(tmp2, 1); | |
3330 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y | |
3331 // X <= 0, Y even: X^Y = -abs(X)^Y | |
3332 | |
3333 fchs(); // Stack: -abs(X)^Y Y | |
3334 jmp(done); | |
3335 } | |
3336 | |
3337 // slow case: runtime call | |
3338 bind(slow_case); | |
3339 | |
3340 fpop(); // pop incorrect result or int(Y) | |
3341 | |
3342 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow), | |
3343 is_exp ? 1 : 2, num_fpu_regs_in_use); | |
3344 | |
3345 // Come here with result in F-TOS | |
3346 bind(done); | |
3347 } | |
3348 | |
3349 void MacroAssembler::fpop() { | |
3350 ffree(); | |
3351 fincstp(); | |
3352 } | |
3353 | |
3354 void MacroAssembler::fremr(Register tmp) { | |
3355 save_rax(tmp); | |
3356 { Label L; | |
3357 bind(L); | |
3358 fprem(); | |
3359 fwait(); fnstsw_ax(); | |
3360 #ifdef _LP64 | |
3361 testl(rax, 0x400); | |
3362 jcc(Assembler::notEqual, L); | |
3363 #else | |
3364 sahf(); | |
3365 jcc(Assembler::parity, L); | |
3366 #endif // _LP64 | |
3367 } | |
3368 restore_rax(tmp); | |
3369 // Result is in ST0. | |
3370 // Note: fxch & fpop to get rid of ST1 | |
3371 // (otherwise FPU stack could overflow eventually) | |
3372 fxch(1); | |
3373 fpop(); | |
3374 } | |
3375 | |
3376 | |
3377 void MacroAssembler::incrementl(AddressLiteral dst) { | |
3378 if (reachable(dst)) { | |
3379 incrementl(as_Address(dst)); | |
3380 } else { | |
3381 lea(rscratch1, dst); | |
3382 incrementl(Address(rscratch1, 0)); | |
3383 } | |
3384 } | |
3385 | |
3386 void MacroAssembler::incrementl(ArrayAddress dst) { | |
3387 incrementl(as_Address(dst)); | |
3388 } | |
3389 | |
3390 void MacroAssembler::incrementl(Register reg, int value) { | |
3391 if (value == min_jint) {addl(reg, value) ; return; } | |
3392 if (value < 0) { decrementl(reg, -value); return; } | |
3393 if (value == 0) { ; return; } | |
3394 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
3395 /* else */ { addl(reg, value) ; return; } | |
3396 } | |
3397 | |
3398 void MacroAssembler::incrementl(Address dst, int value) { | |
3399 if (value == min_jint) {addl(dst, value) ; return; } | |
3400 if (value < 0) { decrementl(dst, -value); return; } | |
3401 if (value == 0) { ; return; } | |
3402 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
3403 /* else */ { addl(dst, value) ; return; } | |
3404 } | |
3405 | |
3406 void MacroAssembler::jump(AddressLiteral dst) { | |
3407 if (reachable(dst)) { | |
3408 jmp_literal(dst.target(), dst.rspec()); | |
3409 } else { | |
3410 lea(rscratch1, dst); | |
3411 jmp(rscratch1); | |
3412 } | |
3413 } | |
3414 | |
3415 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
3416 if (reachable(dst)) { | |
3417 InstructionMark im(this); | |
3418 relocate(dst.reloc()); | |
3419 const int short_size = 2; | |
3420 const int long_size = 6; | |
3421 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); | |
3422 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
3423 // 0111 tttn #8-bit disp | |
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3424 emit_int8(0x70 | cc); |
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3425 emit_int8((offs - short_size) & 0xFF); |
7199 | 3426 } else { |
3427 // 0000 1111 1000 tttn #32-bit disp | |
7430
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3428 emit_int8(0x0F); |
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3429 emit_int8((unsigned char)(0x80 | cc)); |
7476
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3430 emit_int32(offs - long_size); |
7199 | 3431 } |
3432 } else { | |
3433 #ifdef ASSERT | |
3434 warning("reversing conditional branch"); | |
3435 #endif /* ASSERT */ | |
3436 Label skip; | |
3437 jccb(reverse[cc], skip); | |
3438 lea(rscratch1, dst); | |
3439 Assembler::jmp(rscratch1); | |
3440 bind(skip); | |
3441 } | |
3442 } | |
3443 | |
3444 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
3445 if (reachable(src)) { | |
3446 Assembler::ldmxcsr(as_Address(src)); | |
3447 } else { | |
3448 lea(rscratch1, src); | |
3449 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
3450 } | |
3451 } | |
3452 | |
3453 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
3454 int off; | |
3455 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
3456 off = offset(); | |
3457 movsbl(dst, src); // movsxb | |
3458 } else { | |
3459 off = load_unsigned_byte(dst, src); | |
3460 shll(dst, 24); | |
3461 sarl(dst, 24); | |
3462 } | |
3463 return off; | |
3464 } | |
3465 | |
3466 // Note: load_signed_short used to be called load_signed_word. | |
3467 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler | |
3468 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. | |
3469 // The term "word" in HotSpot means a 32- or 64-bit machine word. | |
3470 int MacroAssembler::load_signed_short(Register dst, Address src) { | |
3471 int off; | |
3472 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
3473 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
3474 // version but this is what 64bit has always done. This seems to imply | |
3475 // that users are only using 32bits worth. | |
3476 off = offset(); | |
3477 movswl(dst, src); // movsxw | |
3478 } else { | |
3479 off = load_unsigned_short(dst, src); | |
3480 shll(dst, 16); | |
3481 sarl(dst, 16); | |
3482 } | |
3483 return off; | |
3484 } | |
3485 | |
3486 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
3487 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
3488 // and "3.9 Partial Register Penalties", p. 22). | |
3489 int off; | |
3490 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
3491 off = offset(); | |
3492 movzbl(dst, src); // movzxb | |
3493 } else { | |
3494 xorl(dst, dst); | |
3495 off = offset(); | |
3496 movb(dst, src); | |
3497 } | |
3498 return off; | |
3499 } | |
3500 | |
3501 // Note: load_unsigned_short used to be called load_unsigned_word. | |
3502 int MacroAssembler::load_unsigned_short(Register dst, Address src) { | |
3503 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
3504 // and "3.9 Partial Register Penalties", p. 22). | |
3505 int off; | |
3506 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
3507 off = offset(); | |
3508 movzwl(dst, src); // movzxw | |
3509 } else { | |
3510 xorl(dst, dst); | |
3511 off = offset(); | |
3512 movw(dst, src); | |
3513 } | |
3514 return off; | |
3515 } | |
3516 | |
3517 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { | |
3518 switch (size_in_bytes) { | |
3519 #ifndef _LP64 | |
3520 case 8: | |
3521 assert(dst2 != noreg, "second dest register required"); | |
3522 movl(dst, src); | |
3523 movl(dst2, src.plus_disp(BytesPerInt)); | |
3524 break; | |
3525 #else | |
3526 case 8: movq(dst, src); break; | |
3527 #endif | |
3528 case 4: movl(dst, src); break; | |
3529 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; | |
3530 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; | |
3531 default: ShouldNotReachHere(); | |
3532 } | |
3533 } | |
3534 | |
3535 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { | |
3536 switch (size_in_bytes) { | |
3537 #ifndef _LP64 | |
3538 case 8: | |
3539 assert(src2 != noreg, "second source register required"); | |
3540 movl(dst, src); | |
3541 movl(dst.plus_disp(BytesPerInt), src2); | |
3542 break; | |
3543 #else | |
3544 case 8: movq(dst, src); break; | |
3545 #endif | |
3546 case 4: movl(dst, src); break; | |
3547 case 2: movw(dst, src); break; | |
3548 case 1: movb(dst, src); break; | |
3549 default: ShouldNotReachHere(); | |
3550 } | |
3551 } | |
3552 | |
3553 void MacroAssembler::mov32(AddressLiteral dst, Register src) { | |
3554 if (reachable(dst)) { | |
3555 movl(as_Address(dst), src); | |
3556 } else { | |
3557 lea(rscratch1, dst); | |
3558 movl(Address(rscratch1, 0), src); | |
3559 } | |
3560 } | |
3561 | |
3562 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
3563 if (reachable(src)) { | |
3564 movl(dst, as_Address(src)); | |
3565 } else { | |
3566 lea(rscratch1, src); | |
3567 movl(dst, Address(rscratch1, 0)); | |
3568 } | |
3569 } | |
3570 | |
3571 // C++ bool manipulation | |
3572 | |
3573 void MacroAssembler::movbool(Register dst, Address src) { | |
3574 if(sizeof(bool) == 1) | |
3575 movb(dst, src); | |
3576 else if(sizeof(bool) == 2) | |
3577 movw(dst, src); | |
3578 else if(sizeof(bool) == 4) | |
3579 movl(dst, src); | |
3580 else | |
3581 // unsupported | |
3582 ShouldNotReachHere(); | |
3583 } | |
3584 | |
3585 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
3586 if(sizeof(bool) == 1) | |
3587 movb(dst, (int) boolconst); | |
3588 else if(sizeof(bool) == 2) | |
3589 movw(dst, (int) boolconst); | |
3590 else if(sizeof(bool) == 4) | |
3591 movl(dst, (int) boolconst); | |
3592 else | |
3593 // unsupported | |
3594 ShouldNotReachHere(); | |
3595 } | |
3596 | |
3597 void MacroAssembler::movbool(Address dst, Register src) { | |
3598 if(sizeof(bool) == 1) | |
3599 movb(dst, src); | |
3600 else if(sizeof(bool) == 2) | |
3601 movw(dst, src); | |
3602 else if(sizeof(bool) == 4) | |
3603 movl(dst, src); | |
3604 else | |
3605 // unsupported | |
3606 ShouldNotReachHere(); | |
3607 } | |
3608 | |
3609 void MacroAssembler::movbyte(ArrayAddress dst, int src) { | |
3610 movb(as_Address(dst), src); | |
3611 } | |
3612 | |
3613 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { | |
3614 if (reachable(src)) { | |
3615 movdl(dst, as_Address(src)); | |
3616 } else { | |
3617 lea(rscratch1, src); | |
3618 movdl(dst, Address(rscratch1, 0)); | |
3619 } | |
3620 } | |
3621 | |
3622 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { | |
3623 if (reachable(src)) { | |
3624 movq(dst, as_Address(src)); | |
3625 } else { | |
3626 lea(rscratch1, src); | |
3627 movq(dst, Address(rscratch1, 0)); | |
3628 } | |
3629 } | |
3630 | |
3631 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
3632 if (reachable(src)) { | |
3633 if (UseXmmLoadAndClearUpper) { | |
3634 movsd (dst, as_Address(src)); | |
3635 } else { | |
3636 movlpd(dst, as_Address(src)); | |
3637 } | |
3638 } else { | |
3639 lea(rscratch1, src); | |
3640 if (UseXmmLoadAndClearUpper) { | |
3641 movsd (dst, Address(rscratch1, 0)); | |
3642 } else { | |
3643 movlpd(dst, Address(rscratch1, 0)); | |
3644 } | |
3645 } | |
3646 } | |
3647 | |
3648 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
3649 if (reachable(src)) { | |
3650 movss(dst, as_Address(src)); | |
3651 } else { | |
3652 lea(rscratch1, src); | |
3653 movss(dst, Address(rscratch1, 0)); | |
3654 } | |
3655 } | |
3656 | |
3657 void MacroAssembler::movptr(Register dst, Register src) { | |
3658 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
3659 } | |
3660 | |
3661 void MacroAssembler::movptr(Register dst, Address src) { | |
3662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
3663 } | |
3664 | |
3665 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
3666 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
3667 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
3668 } | |
3669 | |
3670 void MacroAssembler::movptr(Address dst, Register src) { | |
3671 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
3672 } | |
3673 | |
3674 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { | |
3675 if (reachable(src)) { | |
3676 Assembler::movdqu(dst, as_Address(src)); | |
3677 } else { | |
3678 lea(rscratch1, src); | |
3679 Assembler::movdqu(dst, Address(rscratch1, 0)); | |
3680 } | |
3681 } | |
3682 | |
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3683 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { |
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3684 if (reachable(src)) { |
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3685 Assembler::movdqa(dst, as_Address(src)); |
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3686 } else { |
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3687 lea(rscratch1, src); |
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3688 Assembler::movdqa(dst, Address(rscratch1, 0)); |
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3689 } |
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3690 } |
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3691 |
7199 | 3692 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { |
3693 if (reachable(src)) { | |
3694 Assembler::movsd(dst, as_Address(src)); | |
3695 } else { | |
3696 lea(rscratch1, src); | |
3697 Assembler::movsd(dst, Address(rscratch1, 0)); | |
3698 } | |
3699 } | |
3700 | |
3701 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
3702 if (reachable(src)) { | |
3703 Assembler::movss(dst, as_Address(src)); | |
3704 } else { | |
3705 lea(rscratch1, src); | |
3706 Assembler::movss(dst, Address(rscratch1, 0)); | |
3707 } | |
3708 } | |
3709 | |
3710 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { | |
3711 if (reachable(src)) { | |
3712 Assembler::mulsd(dst, as_Address(src)); | |
3713 } else { | |
3714 lea(rscratch1, src); | |
3715 Assembler::mulsd(dst, Address(rscratch1, 0)); | |
3716 } | |
3717 } | |
3718 | |
3719 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { | |
3720 if (reachable(src)) { | |
3721 Assembler::mulss(dst, as_Address(src)); | |
3722 } else { | |
3723 lea(rscratch1, src); | |
3724 Assembler::mulss(dst, Address(rscratch1, 0)); | |
3725 } | |
3726 } | |
3727 | |
3728 void MacroAssembler::null_check(Register reg, int offset) { | |
3729 if (needs_explicit_null_check(offset)) { | |
3730 // provoke OS NULL exception if reg = NULL by | |
3731 // accessing M[reg] w/o changing any (non-CC) registers | |
3732 // NOTE: cmpl is plenty here to provoke a segv | |
3733 cmpptr(rax, Address(reg, 0)); | |
3734 // Note: should probably use testl(rax, Address(reg, 0)); | |
3735 // may be shorter code (however, this version of | |
3736 // testl needs to be implemented first) | |
3737 } else { | |
3738 // nothing to do, (later) access of M[reg + offset] | |
3739 // will provoke OS NULL exception if reg = NULL | |
3740 } | |
3741 } | |
3742 | |
3743 void MacroAssembler::os_breakpoint() { | |
3744 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
3745 // (e.g., MSVC can't call ps() otherwise) | |
3746 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
3747 } | |
3748 | |
3749 void MacroAssembler::pop_CPU_state() { | |
3750 pop_FPU_state(); | |
3751 pop_IU_state(); | |
3752 } | |
3753 | |
3754 void MacroAssembler::pop_FPU_state() { | |
3755 NOT_LP64(frstor(Address(rsp, 0));) | |
3756 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
3757 addptr(rsp, FPUStateSizeInWords * wordSize); | |
3758 } | |
3759 | |
3760 void MacroAssembler::pop_IU_state() { | |
3761 popa(); | |
3762 LP64_ONLY(addq(rsp, 8)); | |
3763 popf(); | |
3764 } | |
3765 | |
3766 // Save Integer and Float state | |
3767 // Warning: Stack must be 16 byte aligned (64bit) | |
3768 void MacroAssembler::push_CPU_state() { | |
3769 push_IU_state(); | |
3770 push_FPU_state(); | |
3771 } | |
3772 | |
3773 void MacroAssembler::push_FPU_state() { | |
3774 subptr(rsp, FPUStateSizeInWords * wordSize); | |
3775 #ifndef _LP64 | |
3776 fnsave(Address(rsp, 0)); | |
3777 fwait(); | |
3778 #else | |
3779 fxsave(Address(rsp, 0)); | |
3780 #endif // LP64 | |
3781 } | |
3782 | |
3783 void MacroAssembler::push_IU_state() { | |
3784 // Push flags first because pusha kills them | |
3785 pushf(); | |
3786 // Make sure rsp stays 16-byte aligned | |
3787 LP64_ONLY(subq(rsp, 8)); | |
3788 pusha(); | |
3789 } | |
3790 | |
3791 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
3792 // determine java_thread register | |
3793 if (!java_thread->is_valid()) { | |
3794 java_thread = rdi; | |
3795 get_thread(java_thread); | |
3796 } | |
3797 // we must set sp to zero to clear frame | |
3798 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); | |
3799 if (clear_fp) { | |
3800 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); | |
3801 } | |
3802 | |
3803 if (clear_pc) | |
3804 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); | |
3805 | |
3806 } | |
3807 | |
3808 void MacroAssembler::restore_rax(Register tmp) { | |
3809 if (tmp == noreg) pop(rax); | |
3810 else if (tmp != rax) mov(rax, tmp); | |
3811 } | |
3812 | |
3813 void MacroAssembler::round_to(Register reg, int modulus) { | |
3814 addptr(reg, modulus - 1); | |
3815 andptr(reg, -modulus); | |
3816 } | |
3817 | |
3818 void MacroAssembler::save_rax(Register tmp) { | |
3819 if (tmp == noreg) push(rax); | |
3820 else if (tmp != rax) mov(tmp, rax); | |
3821 } | |
3822 | |
3823 // Write serialization page so VM thread can do a pseudo remote membar. | |
3824 // We use the current thread pointer to calculate a thread specific | |
3825 // offset to write to within the page. This minimizes bus traffic | |
3826 // due to cache line collision. | |
3827 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
3828 movl(tmp, thread); | |
3829 shrl(tmp, os::get_serialize_page_shift_count()); | |
3830 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
3831 | |
3832 Address index(noreg, tmp, Address::times_1); | |
3833 ExternalAddress page(os::get_memory_serialize_page()); | |
3834 | |
3835 // Size of store must match masking code above | |
3836 movl(as_Address(ArrayAddress(page, index)), tmp); | |
3837 } | |
3838 | |
3839 // Calls to C land | |
3840 // | |
3841 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
3842 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
3843 // has to be reset to 0. This is required to allow proper stack traversal. | |
3844 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
3845 Register last_java_sp, | |
3846 Register last_java_fp, | |
3847 address last_java_pc) { | |
3848 // determine java_thread register | |
3849 if (!java_thread->is_valid()) { | |
3850 java_thread = rdi; | |
3851 get_thread(java_thread); | |
3852 } | |
3853 // determine last_java_sp register | |
3854 if (!last_java_sp->is_valid()) { | |
3855 last_java_sp = rsp; | |
3856 } | |
3857 | |
3858 // last_java_fp is optional | |
3859 | |
3860 if (last_java_fp->is_valid()) { | |
3861 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
3862 } | |
3863 | |
3864 // last_java_pc is optional | |
3865 | |
3866 if (last_java_pc != NULL) { | |
3867 lea(Address(java_thread, | |
3868 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
3869 InternalAddress(last_java_pc)); | |
3870 | |
3871 } | |
3872 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
3873 } | |
3874 | |
3875 void MacroAssembler::shlptr(Register dst, int imm8) { | |
3876 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
3877 } | |
3878 | |
3879 void MacroAssembler::shrptr(Register dst, int imm8) { | |
3880 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
3881 } | |
3882 | |
3883 void MacroAssembler::sign_extend_byte(Register reg) { | |
3884 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
3885 movsbl(reg, reg); // movsxb | |
3886 } else { | |
3887 shll(reg, 24); | |
3888 sarl(reg, 24); | |
3889 } | |
3890 } | |
3891 | |
3892 void MacroAssembler::sign_extend_short(Register reg) { | |
3893 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
3894 movswl(reg, reg); // movsxw | |
3895 } else { | |
3896 shll(reg, 16); | |
3897 sarl(reg, 16); | |
3898 } | |
3899 } | |
3900 | |
3901 void MacroAssembler::testl(Register dst, AddressLiteral src) { | |
3902 assert(reachable(src), "Address should be reachable"); | |
3903 testl(dst, as_Address(src)); | |
3904 } | |
3905 | |
3906 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { | |
3907 if (reachable(src)) { | |
3908 Assembler::sqrtsd(dst, as_Address(src)); | |
3909 } else { | |
3910 lea(rscratch1, src); | |
3911 Assembler::sqrtsd(dst, Address(rscratch1, 0)); | |
3912 } | |
3913 } | |
3914 | |
3915 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { | |
3916 if (reachable(src)) { | |
3917 Assembler::sqrtss(dst, as_Address(src)); | |
3918 } else { | |
3919 lea(rscratch1, src); | |
3920 Assembler::sqrtss(dst, Address(rscratch1, 0)); | |
3921 } | |
3922 } | |
3923 | |
3924 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { | |
3925 if (reachable(src)) { | |
3926 Assembler::subsd(dst, as_Address(src)); | |
3927 } else { | |
3928 lea(rscratch1, src); | |
3929 Assembler::subsd(dst, Address(rscratch1, 0)); | |
3930 } | |
3931 } | |
3932 | |
3933 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { | |
3934 if (reachable(src)) { | |
3935 Assembler::subss(dst, as_Address(src)); | |
3936 } else { | |
3937 lea(rscratch1, src); | |
3938 Assembler::subss(dst, Address(rscratch1, 0)); | |
3939 } | |
3940 } | |
3941 | |
3942 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { | |
3943 if (reachable(src)) { | |
3944 Assembler::ucomisd(dst, as_Address(src)); | |
3945 } else { | |
3946 lea(rscratch1, src); | |
3947 Assembler::ucomisd(dst, Address(rscratch1, 0)); | |
3948 } | |
3949 } | |
3950 | |
3951 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
3952 if (reachable(src)) { | |
3953 Assembler::ucomiss(dst, as_Address(src)); | |
3954 } else { | |
3955 lea(rscratch1, src); | |
3956 Assembler::ucomiss(dst, Address(rscratch1, 0)); | |
3957 } | |
3958 } | |
3959 | |
3960 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
3961 // Used in sign-bit flipping with aligned address. | |
3962 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
3963 if (reachable(src)) { | |
3964 Assembler::xorpd(dst, as_Address(src)); | |
3965 } else { | |
3966 lea(rscratch1, src); | |
3967 Assembler::xorpd(dst, Address(rscratch1, 0)); | |
3968 } | |
3969 } | |
3970 | |
3971 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
3972 // Used in sign-bit flipping with aligned address. | |
3973 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); | |
3974 if (reachable(src)) { | |
3975 Assembler::xorps(dst, as_Address(src)); | |
3976 } else { | |
3977 lea(rscratch1, src); | |
3978 Assembler::xorps(dst, Address(rscratch1, 0)); | |
3979 } | |
3980 } | |
3981 | |
3982 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { | |
3983 // Used in sign-bit flipping with aligned address. | |
7427 | 3984 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); |
3985 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); | |
7199 | 3986 if (reachable(src)) { |
3987 Assembler::pshufb(dst, as_Address(src)); | |
3988 } else { | |
3989 lea(rscratch1, src); | |
3990 Assembler::pshufb(dst, Address(rscratch1, 0)); | |
3991 } | |
3992 } | |
3993 | |
3994 // AVX 3-operands instructions | |
3995 | |
3996 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
3997 if (reachable(src)) { | |
3998 vaddsd(dst, nds, as_Address(src)); | |
3999 } else { | |
4000 lea(rscratch1, src); | |
4001 vaddsd(dst, nds, Address(rscratch1, 0)); | |
4002 } | |
4003 } | |
4004 | |
4005 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4006 if (reachable(src)) { | |
4007 vaddss(dst, nds, as_Address(src)); | |
4008 } else { | |
4009 lea(rscratch1, src); | |
4010 vaddss(dst, nds, Address(rscratch1, 0)); | |
4011 } | |
4012 } | |
4013 | |
4014 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { | |
4015 if (reachable(src)) { | |
4016 vandpd(dst, nds, as_Address(src), vector256); | |
4017 } else { | |
4018 lea(rscratch1, src); | |
4019 vandpd(dst, nds, Address(rscratch1, 0), vector256); | |
4020 } | |
4021 } | |
4022 | |
4023 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { | |
4024 if (reachable(src)) { | |
4025 vandps(dst, nds, as_Address(src), vector256); | |
4026 } else { | |
4027 lea(rscratch1, src); | |
4028 vandps(dst, nds, Address(rscratch1, 0), vector256); | |
4029 } | |
4030 } | |
4031 | |
4032 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4033 if (reachable(src)) { | |
4034 vdivsd(dst, nds, as_Address(src)); | |
4035 } else { | |
4036 lea(rscratch1, src); | |
4037 vdivsd(dst, nds, Address(rscratch1, 0)); | |
4038 } | |
4039 } | |
4040 | |
4041 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4042 if (reachable(src)) { | |
4043 vdivss(dst, nds, as_Address(src)); | |
4044 } else { | |
4045 lea(rscratch1, src); | |
4046 vdivss(dst, nds, Address(rscratch1, 0)); | |
4047 } | |
4048 } | |
4049 | |
4050 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4051 if (reachable(src)) { | |
4052 vmulsd(dst, nds, as_Address(src)); | |
4053 } else { | |
4054 lea(rscratch1, src); | |
4055 vmulsd(dst, nds, Address(rscratch1, 0)); | |
4056 } | |
4057 } | |
4058 | |
4059 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4060 if (reachable(src)) { | |
4061 vmulss(dst, nds, as_Address(src)); | |
4062 } else { | |
4063 lea(rscratch1, src); | |
4064 vmulss(dst, nds, Address(rscratch1, 0)); | |
4065 } | |
4066 } | |
4067 | |
4068 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4069 if (reachable(src)) { | |
4070 vsubsd(dst, nds, as_Address(src)); | |
4071 } else { | |
4072 lea(rscratch1, src); | |
4073 vsubsd(dst, nds, Address(rscratch1, 0)); | |
4074 } | |
4075 } | |
4076 | |
4077 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { | |
4078 if (reachable(src)) { | |
4079 vsubss(dst, nds, as_Address(src)); | |
4080 } else { | |
4081 lea(rscratch1, src); | |
4082 vsubss(dst, nds, Address(rscratch1, 0)); | |
4083 } | |
4084 } | |
4085 | |
4086 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { | |
4087 if (reachable(src)) { | |
4088 vxorpd(dst, nds, as_Address(src), vector256); | |
4089 } else { | |
4090 lea(rscratch1, src); | |
4091 vxorpd(dst, nds, Address(rscratch1, 0), vector256); | |
4092 } | |
4093 } | |
4094 | |
4095 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) { | |
4096 if (reachable(src)) { | |
4097 vxorps(dst, nds, as_Address(src), vector256); | |
4098 } else { | |
4099 lea(rscratch1, src); | |
4100 vxorps(dst, nds, Address(rscratch1, 0), vector256); | |
4101 } | |
4102 } | |
4103 | |
4104 | |
4105 ////////////////////////////////////////////////////////////////////////////////// | |
8001
db9981fd3124
8005915: Unify SERIALGC and INCLUDE_ALTERNATE_GCS
jprovino
parents:
7477
diff
changeset
|
4106 #if INCLUDE_ALL_GCS |
7199 | 4107 |
4108 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
4109 Register pre_val, | |
4110 Register thread, | |
4111 Register tmp, | |
4112 bool tosca_live, | |
4113 bool expand_call) { | |
4114 | |
4115 // If expand_call is true then we expand the call_VM_leaf macro | |
4116 // directly to skip generating the check by | |
4117 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. | |
4118 | |
4119 #ifdef _LP64 | |
4120 assert(thread == r15_thread, "must be"); | |
4121 #endif // _LP64 | |
4122 | |
4123 Label done; | |
4124 Label runtime; | |
4125 | |
4126 assert(pre_val != noreg, "check this code"); | |
4127 | |
4128 if (obj != noreg) { | |
4129 assert_different_registers(obj, pre_val, tmp); | |
4130 assert(pre_val != rax, "check this code"); | |
4131 } | |
4132 | |
4133 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
4134 PtrQueue::byte_offset_of_active())); | |
4135 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
4136 PtrQueue::byte_offset_of_index())); | |
4137 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
4138 PtrQueue::byte_offset_of_buf())); | |
4139 | |
4140 | |
4141 // Is marking active? | |
4142 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
4143 cmpl(in_progress, 0); | |
4144 } else { | |
4145 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
4146 cmpb(in_progress, 0); | |
4147 } | |
4148 jcc(Assembler::equal, done); | |
4149 | |
4150 // Do we need to load the previous value? | |
4151 if (obj != noreg) { | |
4152 load_heap_oop(pre_val, Address(obj, 0)); | |
4153 } | |
4154 | |
4155 // Is the previous value null? | |
4156 cmpptr(pre_val, (int32_t) NULL_WORD); | |
4157 jcc(Assembler::equal, done); | |
4158 | |
4159 // Can we store original value in the thread's buffer? | |
4160 // Is index == 0? | |
4161 // (The index field is typed as size_t.) | |
4162 | |
4163 movptr(tmp, index); // tmp := *index_adr | |
4164 cmpptr(tmp, 0); // tmp == 0? | |
4165 jcc(Assembler::equal, runtime); // If yes, goto runtime | |
4166 | |
4167 subptr(tmp, wordSize); // tmp := tmp - wordSize | |
4168 movptr(index, tmp); // *index_adr := tmp | |
4169 addptr(tmp, buffer); // tmp := tmp + *buffer_adr | |
4170 | |
4171 // Record the previous value | |
4172 movptr(Address(tmp, 0), pre_val); | |
4173 jmp(done); | |
4174 | |
4175 bind(runtime); | |
4176 // save the live input values | |
4177 if(tosca_live) push(rax); | |
4178 | |
4179 if (obj != noreg && obj != rax) | |
4180 push(obj); | |
4181 | |
4182 if (pre_val != rax) | |
4183 push(pre_val); | |
4184 | |
4185 // Calling the runtime using the regular call_VM_leaf mechanism generates | |
4186 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) | |
4187 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. | |
4188 // | |
4189 // If we care generating the pre-barrier without a frame (e.g. in the | |
4190 // intrinsified Reference.get() routine) then ebp might be pointing to | |
4191 // the caller frame and so this check will most likely fail at runtime. | |
4192 // | |
4193 // Expanding the call directly bypasses the generation of the check. | |
4194 // So when we do not have have a full interpreter frame on the stack | |
4195 // expand_call should be passed true. | |
4196 | |
4197 NOT_LP64( push(thread); ) | |
4198 | |
4199 if (expand_call) { | |
4200 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) | |
4201 pass_arg1(this, thread); | |
4202 pass_arg0(this, pre_val); | |
4203 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); | |
4204 } else { | |
4205 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); | |
4206 } | |
4207 | |
4208 NOT_LP64( pop(thread); ) | |
4209 | |
4210 // save the live input values | |
4211 if (pre_val != rax) | |
4212 pop(pre_val); | |
4213 | |
4214 if (obj != noreg && obj != rax) | |
4215 pop(obj); | |
4216 | |
4217 if(tosca_live) pop(rax); | |
4218 | |
4219 bind(done); | |
4220 } | |
4221 | |
4222 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
4223 Register new_val, | |
4224 Register thread, | |
4225 Register tmp, | |
4226 Register tmp2) { | |
4227 #ifdef _LP64 | |
4228 assert(thread == r15_thread, "must be"); | |
4229 #endif // _LP64 | |
4230 | |
4231 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
4232 PtrQueue::byte_offset_of_index())); | |
4233 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
4234 PtrQueue::byte_offset_of_buf())); | |
4235 | |
4236 BarrierSet* bs = Universe::heap()->barrier_set(); | |
4237 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
13424
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diff
changeset
|
4238 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4239 |
7199 | 4240 Label done; |
4241 Label runtime; | |
4242 | |
4243 // Does store cross heap regions? | |
4244 | |
4245 movptr(tmp, store_addr); | |
4246 xorptr(tmp, new_val); | |
4247 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
4248 jcc(Assembler::equal, done); | |
4249 | |
4250 // crosses regions, storing NULL? | |
4251 | |
4252 cmpptr(new_val, (int32_t) NULL_WORD); | |
4253 jcc(Assembler::equal, done); | |
4254 | |
4255 // storing region crossing non-NULL, is card already dirty? | |
4256 | |
4257 const Register card_addr = tmp; | |
13424
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4258 const Register cardtable = tmp2; |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4259 |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4260 movptr(card_addr, store_addr); |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4261 shrptr(card_addr, CardTableModRefBS::card_shift); |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
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parents:
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diff
changeset
|
4262 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4263 // a valid address and therefore is not properly handled by the relocation code. |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4264 movptr(cardtable, (intptr_t)ct->byte_map_base); |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4265 addptr(card_addr, cardtable); |
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8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
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diff
changeset
|
4266 |
12835
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
parents:
12226
diff
changeset
|
4267 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); |
7199 | 4268 jcc(Assembler::equal, done); |
4269 | |
12835
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
parents:
12226
diff
changeset
|
4270 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
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diff
changeset
|
4271 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); |
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
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diff
changeset
|
4272 jcc(Assembler::equal, done); |
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
parents:
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diff
changeset
|
4273 |
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
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changeset
|
4274 |
7199 | 4275 // storing a region crossing, non-NULL oop, card is clean. |
4276 // dirty card and log. | |
4277 | |
12835
69944b868a32
8014555: G1: Memory ordering problem with Conc refinement and card marking
mgerdin
parents:
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diff
changeset
|
4278 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); |
7199 | 4279 |
4280 cmpl(queue_index, 0); | |
4281 jcc(Assembler::equal, runtime); | |
4282 subl(queue_index, wordSize); | |
4283 movptr(tmp2, buffer); | |
4284 #ifdef _LP64 | |
4285 movslq(rscratch1, queue_index); | |
4286 addq(tmp2, rscratch1); | |
4287 movq(Address(tmp2, 0), card_addr); | |
4288 #else | |
4289 addl(tmp2, queue_index); | |
13424
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changeset
|
4290 movl(Address(tmp2, 0), card_addr); |
7199 | 4291 #endif |
4292 jmp(done); | |
4293 | |
4294 bind(runtime); | |
4295 // save the live input values | |
4296 push(store_addr); | |
4297 push(new_val); | |
4298 #ifdef _LP64 | |
4299 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
4300 #else | |
4301 push(thread); | |
4302 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
4303 pop(thread); | |
4304 #endif | |
4305 pop(new_val); | |
4306 pop(store_addr); | |
4307 | |
4308 bind(done); | |
4309 } | |
4310 | |
8001
db9981fd3124
8005915: Unify SERIALGC and INCLUDE_ALTERNATE_GCS
jprovino
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diff
changeset
|
4311 #endif // INCLUDE_ALL_GCS |
7199 | 4312 ////////////////////////////////////////////////////////////////////////////////// |
4313 | |
4314 | |
4315 void MacroAssembler::store_check(Register obj) { | |
4316 // Does a store check for the oop in register obj. The content of | |
4317 // register obj is destroyed afterwards. | |
4318 store_check_part_1(obj); | |
4319 store_check_part_2(obj); | |
4320 } | |
4321 | |
4322 void MacroAssembler::store_check(Register obj, Address dst) { | |
4323 store_check(obj); | |
4324 } | |
4325 | |
4326 | |
4327 // split the store check operation so that other instructions can be scheduled inbetween | |
4328 void MacroAssembler::store_check_part_1(Register obj) { | |
4329 BarrierSet* bs = Universe::heap()->barrier_set(); | |
4330 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
4331 shrptr(obj, CardTableModRefBS::card_shift); | |
4332 } | |
4333 | |
4334 void MacroAssembler::store_check_part_2(Register obj) { | |
4335 BarrierSet* bs = Universe::heap()->barrier_set(); | |
4336 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
4337 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
4338 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
4339 | |
4340 // The calculation for byte_map_base is as follows: | |
4341 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
13424
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diff
changeset
|
4342 // So this essentially converts an address to a displacement and it will |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4343 // never need to be relocated. On 64bit however the value may be too |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4344 // large for a 32bit displacement. |
7199 | 4345 intptr_t disp = (intptr_t) ct->byte_map_base; |
4346 if (is_simm32(disp)) { | |
4347 Address cardtable(noreg, obj, Address::times_1, disp); | |
4348 movb(cardtable, 0); | |
4349 } else { | |
13424
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parents:
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diff
changeset
|
4350 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
13047
diff
changeset
|
4351 // displacement and done in a single instruction given favorable mapping and a |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
13047
diff
changeset
|
4352 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
parents:
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diff
changeset
|
4353 // entry and that entry is not properly handled by the relocation code. |
61746b5f0ed3
8028109: compiler/codecache/CheckReservedInitialCodeCacheSizeArgOrder.java crashes in RT_Baseline
anoll
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diff
changeset
|
4354 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); |
7199 | 4355 Address index(noreg, obj, Address::times_1); |
4356 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
4357 } | |
4358 } | |
4359 | |
4360 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
4361 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
4362 } | |
4363 | |
4364 // Force generation of a 4 byte immediate value even if it fits into 8bit | |
4365 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { | |
4366 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); | |
4367 } | |
4368 | |
4369 void MacroAssembler::subptr(Register dst, Register src) { | |
4370 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
4371 } | |
4372 | |
4373 // C++ bool manipulation | |
4374 void MacroAssembler::testbool(Register dst) { | |
4375 if(sizeof(bool) == 1) | |
4376 testb(dst, 0xff); | |
4377 else if(sizeof(bool) == 2) { | |
4378 // testw implementation needed for two byte bools | |
4379 ShouldNotReachHere(); | |
4380 } else if(sizeof(bool) == 4) | |
4381 testl(dst, dst); | |
4382 else | |
4383 // unsupported | |
4384 ShouldNotReachHere(); | |
4385 } | |
4386 | |
4387 void MacroAssembler::testptr(Register dst, Register src) { | |
4388 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
4389 } | |
4390 | |
4391 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
4392 void MacroAssembler::tlab_allocate(Register obj, | |
4393 Register var_size_in_bytes, | |
4394 int con_size_in_bytes, | |
4395 Register t1, | |
4396 Register t2, | |
4397 Label& slow_case) { | |
4398 assert_different_registers(obj, t1, t2); | |
4399 assert_different_registers(obj, var_size_in_bytes, t1); | |
4400 Register end = t2; | |
4401 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
4402 | |
4403 verify_tlab(); | |
4404 | |
4405 NOT_LP64(get_thread(thread)); | |
4406 | |
4407 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
4408 if (var_size_in_bytes == noreg) { | |
4409 lea(end, Address(obj, con_size_in_bytes)); | |
4410 } else { | |
4411 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
4412 } | |
4413 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
4414 jcc(Assembler::above, slow_case); | |
4415 | |
4416 // update the tlab top pointer | |
4417 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
4418 | |
4419 // recover var_size_in_bytes if necessary | |
4420 if (var_size_in_bytes == end) { | |
4421 subptr(var_size_in_bytes, obj); | |
4422 } | |
4423 verify_tlab(); | |
4424 } | |
4425 | |
4426 // Preserves rbx, and rdx. | |
4427 Register MacroAssembler::tlab_refill(Label& retry, | |
4428 Label& try_eden, | |
4429 Label& slow_case) { | |
4430 Register top = rax; | |
4431 Register t1 = rcx; | |
4432 Register t2 = rsi; | |
4433 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
4434 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
4435 Label do_refill, discard_tlab; | |
4436 | |
4437 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
4438 // No allocation in the shared eden. | |
4439 jmp(slow_case); | |
4440 } | |
4441 | |
4442 NOT_LP64(get_thread(thread_reg)); | |
4443 | |
4444 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
4445 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
4446 | |
4447 // calculate amount of free space | |
4448 subptr(t1, top); | |
4449 shrptr(t1, LogHeapWordSize); | |
4450 | |
4451 // Retain tlab and allocate object in shared space if | |
4452 // the amount free in the tlab is too large to discard. | |
4453 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
4454 jcc(Assembler::lessEqual, discard_tlab); | |
4455 | |
4456 // Retain | |
4457 // %%% yuck as movptr... | |
4458 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
4459 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
4460 if (TLABStats) { | |
4461 // increment number of slow_allocations | |
4462 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
4463 } | |
4464 jmp(try_eden); | |
4465 | |
4466 bind(discard_tlab); | |
4467 if (TLABStats) { | |
4468 // increment number of refills | |
4469 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
4470 // accumulate wastage -- t1 is amount free in tlab | |
4471 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
4472 } | |
4473 | |
4474 // if tlab is currently allocated (top or end != null) then | |
4475 // fill [top, end + alignment_reserve) with array object | |
4476 testptr(top, top); | |
4477 jcc(Assembler::zero, do_refill); | |
4478 | |
4479 // set up the mark word | |
4480 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
4481 // set the length to the remaining space | |
4482 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
4483 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
4484 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
4485 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); | |
4486 // set klass to intArrayKlass | |
4487 // dubious reloc why not an oop reloc? | |
4488 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); | |
4489 // store klass last. concurrent gcs assumes klass length is valid if | |
4490 // klass field is not null. | |
4491 store_klass(top, t1); | |
4492 | |
4493 movptr(t1, top); | |
4494 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
4495 incr_allocated_bytes(thread_reg, t1, 0); | |
4496 | |
4497 // refill the tlab with an eden allocation | |
4498 bind(do_refill); | |
4499 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
4500 shlptr(t1, LogHeapWordSize); | |
4501 // allocate new tlab, address returned in top | |
4502 eden_allocate(top, t1, 0, t2, slow_case); | |
4503 | |
4504 // Check that t1 was preserved in eden_allocate. | |
4505 #ifdef ASSERT | |
4506 if (UseTLAB) { | |
4507 Label ok; | |
4508 Register tsize = rsi; | |
4509 assert_different_registers(tsize, thread_reg, t1); | |
4510 push(tsize); | |
4511 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
4512 shlptr(tsize, LogHeapWordSize); | |
4513 cmpptr(t1, tsize); | |
4514 jcc(Assembler::equal, ok); | |
4515 STOP("assert(t1 != tlab size)"); | |
4516 should_not_reach_here(); | |
4517 | |
4518 bind(ok); | |
4519 pop(tsize); | |
4520 } | |
4521 #endif | |
4522 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
4523 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
4524 addptr(top, t1); | |
4525 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
4526 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
4527 verify_tlab(); | |
4528 jmp(retry); | |
4529 | |
4530 return thread_reg; // for use by caller | |
4531 } | |
4532 | |
4533 void MacroAssembler::incr_allocated_bytes(Register thread, | |
4534 Register var_size_in_bytes, | |
4535 int con_size_in_bytes, | |
4536 Register t1) { | |
4537 if (!thread->is_valid()) { | |
4538 #ifdef _LP64 | |
4539 thread = r15_thread; | |
4540 #else | |
4541 assert(t1->is_valid(), "need temp reg"); | |
4542 thread = t1; | |
4543 get_thread(thread); | |
4544 #endif | |
4545 } | |
4546 | |
4547 #ifdef _LP64 | |
4548 if (var_size_in_bytes->is_valid()) { | |
4549 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); | |
4550 } else { | |
4551 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); | |
4552 } | |
4553 #else | |
4554 if (var_size_in_bytes->is_valid()) { | |
4555 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); | |
4556 } else { | |
4557 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); | |
4558 } | |
4559 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); | |
4560 #endif | |
4561 } | |
4562 | |
4563 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { | |
4564 pusha(); | |
4565 | |
4566 // if we are coming from c1, xmm registers may be live | |
4567 int off = 0; | |
4568 if (UseSSE == 1) { | |
4569 subptr(rsp, sizeof(jdouble)*8); | |
4570 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0); | |
4571 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1); | |
4572 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2); | |
4573 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3); | |
4574 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4); | |
4575 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5); | |
4576 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6); | |
4577 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7); | |
4578 } else if (UseSSE >= 2) { | |
4579 #ifdef COMPILER2 | |
4580 if (MaxVectorSize > 16) { | |
4581 assert(UseAVX > 0, "256bit vectors are supported only with AVX"); | |
4582 // Save upper half of YMM registes | |
4583 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); | |
4584 vextractf128h(Address(rsp, 0),xmm0); | |
4585 vextractf128h(Address(rsp, 16),xmm1); | |
4586 vextractf128h(Address(rsp, 32),xmm2); | |
4587 vextractf128h(Address(rsp, 48),xmm3); | |
4588 vextractf128h(Address(rsp, 64),xmm4); | |
4589 vextractf128h(Address(rsp, 80),xmm5); | |
4590 vextractf128h(Address(rsp, 96),xmm6); | |
4591 vextractf128h(Address(rsp,112),xmm7); | |
4592 #ifdef _LP64 | |
4593 vextractf128h(Address(rsp,128),xmm8); | |
4594 vextractf128h(Address(rsp,144),xmm9); | |
4595 vextractf128h(Address(rsp,160),xmm10); | |
4596 vextractf128h(Address(rsp,176),xmm11); | |
4597 vextractf128h(Address(rsp,192),xmm12); | |
4598 vextractf128h(Address(rsp,208),xmm13); | |
4599 vextractf128h(Address(rsp,224),xmm14); | |
4600 vextractf128h(Address(rsp,240),xmm15); | |
4601 #endif | |
4602 } | |
4603 #endif | |
4604 // Save whole 128bit (16 bytes) XMM regiters | |
4605 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); | |
4606 movdqu(Address(rsp,off++*16),xmm0); | |
4607 movdqu(Address(rsp,off++*16),xmm1); | |
4608 movdqu(Address(rsp,off++*16),xmm2); | |
4609 movdqu(Address(rsp,off++*16),xmm3); | |
4610 movdqu(Address(rsp,off++*16),xmm4); | |
4611 movdqu(Address(rsp,off++*16),xmm5); | |
4612 movdqu(Address(rsp,off++*16),xmm6); | |
4613 movdqu(Address(rsp,off++*16),xmm7); | |
4614 #ifdef _LP64 | |
4615 movdqu(Address(rsp,off++*16),xmm8); | |
4616 movdqu(Address(rsp,off++*16),xmm9); | |
4617 movdqu(Address(rsp,off++*16),xmm10); | |
4618 movdqu(Address(rsp,off++*16),xmm11); | |
4619 movdqu(Address(rsp,off++*16),xmm12); | |
4620 movdqu(Address(rsp,off++*16),xmm13); | |
4621 movdqu(Address(rsp,off++*16),xmm14); | |
4622 movdqu(Address(rsp,off++*16),xmm15); | |
4623 #endif | |
4624 } | |
4625 | |
4626 // Preserve registers across runtime call | |
4627 int incoming_argument_and_return_value_offset = -1; | |
4628 if (num_fpu_regs_in_use > 1) { | |
4629 // Must preserve all other FPU regs (could alternatively convert | |
4630 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash | |
4631 // FPU state, but can not trust C compiler) | |
4632 NEEDS_CLEANUP; | |
4633 // NOTE that in this case we also push the incoming argument(s) to | |
4634 // the stack and restore it later; we also use this stack slot to | |
4635 // hold the return value from dsin, dcos etc. | |
4636 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
4637 subptr(rsp, sizeof(jdouble)); | |
4638 fstp_d(Address(rsp, 0)); | |
4639 } | |
4640 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
4641 for (int i = nb_args-1; i >= 0; i--) { | |
4642 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); | |
4643 } | |
4644 } | |
4645 | |
4646 subptr(rsp, nb_args*sizeof(jdouble)); | |
4647 for (int i = 0; i < nb_args; i++) { | |
4648 fstp_d(Address(rsp, i*sizeof(jdouble))); | |
4649 } | |
4650 | |
4651 #ifdef _LP64 | |
4652 if (nb_args > 0) { | |
4653 movdbl(xmm0, Address(rsp, 0)); | |
4654 } | |
4655 if (nb_args > 1) { | |
4656 movdbl(xmm1, Address(rsp, sizeof(jdouble))); | |
4657 } | |
4658 assert(nb_args <= 2, "unsupported number of args"); | |
4659 #endif // _LP64 | |
4660 | |
4661 // NOTE: we must not use call_VM_leaf here because that requires a | |
4662 // complete interpreter frame in debug mode -- same bug as 4387334 | |
4663 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
4664 // do proper 64bit abi | |
4665 | |
4666 NEEDS_CLEANUP; | |
4667 // Need to add stack banging before this runtime call if it needs to | |
4668 // be taken; however, there is no generic stack banging routine at | |
4669 // the MacroAssembler level | |
4670 | |
4671 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); | |
4672 | |
4673 #ifdef _LP64 | |
4674 movsd(Address(rsp, 0), xmm0); | |
4675 fld_d(Address(rsp, 0)); | |
4676 #endif // _LP64 | |
4677 addptr(rsp, sizeof(jdouble) * nb_args); | |
4678 if (num_fpu_regs_in_use > 1) { | |
4679 // Must save return value to stack and then restore entire FPU | |
4680 // stack except incoming arguments | |
4681 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
4682 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { | |
4683 fld_d(Address(rsp, 0)); | |
4684 addptr(rsp, sizeof(jdouble)); | |
4685 } | |
4686 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); | |
4687 addptr(rsp, sizeof(jdouble) * nb_args); | |
4688 } | |
4689 | |
4690 off = 0; | |
4691 if (UseSSE == 1) { | |
4692 movflt(xmm0, Address(rsp,off++*sizeof(jdouble))); | |
4693 movflt(xmm1, Address(rsp,off++*sizeof(jdouble))); | |
4694 movflt(xmm2, Address(rsp,off++*sizeof(jdouble))); | |
4695 movflt(xmm3, Address(rsp,off++*sizeof(jdouble))); | |
4696 movflt(xmm4, Address(rsp,off++*sizeof(jdouble))); | |
4697 movflt(xmm5, Address(rsp,off++*sizeof(jdouble))); | |
4698 movflt(xmm6, Address(rsp,off++*sizeof(jdouble))); | |
4699 movflt(xmm7, Address(rsp,off++*sizeof(jdouble))); | |
4700 addptr(rsp, sizeof(jdouble)*8); | |
4701 } else if (UseSSE >= 2) { | |
4702 // Restore whole 128bit (16 bytes) XMM regiters | |
4703 movdqu(xmm0, Address(rsp,off++*16)); | |
4704 movdqu(xmm1, Address(rsp,off++*16)); | |
4705 movdqu(xmm2, Address(rsp,off++*16)); | |
4706 movdqu(xmm3, Address(rsp,off++*16)); | |
4707 movdqu(xmm4, Address(rsp,off++*16)); | |
4708 movdqu(xmm5, Address(rsp,off++*16)); | |
4709 movdqu(xmm6, Address(rsp,off++*16)); | |
4710 movdqu(xmm7, Address(rsp,off++*16)); | |
4711 #ifdef _LP64 | |
4712 movdqu(xmm8, Address(rsp,off++*16)); | |
4713 movdqu(xmm9, Address(rsp,off++*16)); | |
4714 movdqu(xmm10, Address(rsp,off++*16)); | |
4715 movdqu(xmm11, Address(rsp,off++*16)); | |
4716 movdqu(xmm12, Address(rsp,off++*16)); | |
4717 movdqu(xmm13, Address(rsp,off++*16)); | |
4718 movdqu(xmm14, Address(rsp,off++*16)); | |
4719 movdqu(xmm15, Address(rsp,off++*16)); | |
4720 #endif | |
4721 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); | |
4722 #ifdef COMPILER2 | |
4723 if (MaxVectorSize > 16) { | |
4724 // Restore upper half of YMM registes. | |
4725 vinsertf128h(xmm0, Address(rsp, 0)); | |
4726 vinsertf128h(xmm1, Address(rsp, 16)); | |
4727 vinsertf128h(xmm2, Address(rsp, 32)); | |
4728 vinsertf128h(xmm3, Address(rsp, 48)); | |
4729 vinsertf128h(xmm4, Address(rsp, 64)); | |
4730 vinsertf128h(xmm5, Address(rsp, 80)); | |
4731 vinsertf128h(xmm6, Address(rsp, 96)); | |
4732 vinsertf128h(xmm7, Address(rsp,112)); | |
4733 #ifdef _LP64 | |
4734 vinsertf128h(xmm8, Address(rsp,128)); | |
4735 vinsertf128h(xmm9, Address(rsp,144)); | |
4736 vinsertf128h(xmm10, Address(rsp,160)); | |
4737 vinsertf128h(xmm11, Address(rsp,176)); | |
4738 vinsertf128h(xmm12, Address(rsp,192)); | |
4739 vinsertf128h(xmm13, Address(rsp,208)); | |
4740 vinsertf128h(xmm14, Address(rsp,224)); | |
4741 vinsertf128h(xmm15, Address(rsp,240)); | |
4742 #endif | |
4743 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8)); | |
4744 } | |
4745 #endif | |
4746 } | |
4747 popa(); | |
4748 } | |
4749 | |
4750 static const double pi_4 = 0.7853981633974483; | |
4751 | |
4752 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
4753 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
4754 // was attempted in this code; unfortunately it appears that the | |
4755 // switch to 80-bit precision and back causes this to be | |
4756 // unprofitable compared with simply performing a runtime call if | |
4757 // the argument is out of the (-pi/4, pi/4) range. | |
4758 | |
4759 Register tmp = noreg; | |
4760 if (!VM_Version::supports_cmov()) { | |
4761 // fcmp needs a temporary so preserve rbx, | |
4762 tmp = rbx; | |
4763 push(tmp); | |
4764 } | |
4765 | |
4766 Label slow_case, done; | |
4767 | |
4768 ExternalAddress pi4_adr = (address)&pi_4; | |
4769 if (reachable(pi4_adr)) { | |
4770 // x ?<= pi/4 | |
4771 fld_d(pi4_adr); | |
4772 fld_s(1); // Stack: X PI/4 X | |
4773 fabs(); // Stack: |X| PI/4 X | |
4774 fcmp(tmp); | |
4775 jcc(Assembler::above, slow_case); | |
4776 | |
4777 // fastest case: -pi/4 <= x <= pi/4 | |
4778 switch(trig) { | |
4779 case 's': | |
4780 fsin(); | |
4781 break; | |
4782 case 'c': | |
4783 fcos(); | |
4784 break; | |
4785 case 't': | |
4786 ftan(); | |
4787 break; | |
4788 default: | |
4789 assert(false, "bad intrinsic"); | |
4790 break; | |
4791 } | |
4792 jmp(done); | |
4793 } | |
4794 | |
4795 // slow case: runtime call | |
4796 bind(slow_case); | |
4797 | |
4798 switch(trig) { | |
4799 case 's': | |
4800 { | |
4801 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); | |
4802 } | |
4803 break; | |
4804 case 'c': | |
4805 { | |
4806 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); | |
4807 } | |
4808 break; | |
4809 case 't': | |
4810 { | |
4811 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); | |
4812 } | |
4813 break; | |
4814 default: | |
4815 assert(false, "bad intrinsic"); | |
4816 break; | |
4817 } | |
4818 | |
4819 // Come here with result in F-TOS | |
4820 bind(done); | |
4821 | |
4822 if (tmp != noreg) { | |
4823 pop(tmp); | |
4824 } | |
4825 } | |
4826 | |
4827 | |
4828 // Look up the method for a megamorphic invokeinterface call. | |
4829 // The target method is determined by <intf_klass, itable_index>. | |
4830 // The receiver klass is in recv_klass. | |
4831 // On success, the result will be in method_result, and execution falls through. | |
4832 // On failure, execution transfers to the given label. | |
4833 void MacroAssembler::lookup_interface_method(Register recv_klass, | |
4834 Register intf_klass, | |
4835 RegisterOrConstant itable_index, | |
4836 Register method_result, | |
4837 Register scan_temp, | |
4838 Label& L_no_such_interface) { | |
4839 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); | |
4840 assert(itable_index.is_constant() || itable_index.as_register() == method_result, | |
4841 "caller must use same register for non-constant itable index as for method"); | |
4842 | |
4843 // Compute start of first itableOffsetEntry (which is at the end of the vtable) | |
4844 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; | |
4845 int itentry_off = itableMethodEntry::method_offset_in_bytes(); | |
4846 int scan_step = itableOffsetEntry::size() * wordSize; | |
4847 int vte_size = vtableEntry::size() * wordSize; | |
4848 Address::ScaleFactor times_vte_scale = Address::times_ptr; | |
4849 assert(vte_size == wordSize, "else adjust times_vte_scale"); | |
4850 | |
4851 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize)); | |
4852 | |
4853 // %%% Could store the aligned, prescaled offset in the klassoop. | |
4854 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); | |
4855 if (HeapWordsPerLong > 1) { | |
4856 // Round up to align_object_offset boundary | |
4857 // see code for InstanceKlass::start_of_itable! | |
4858 round_to(scan_temp, BytesPerLong); | |
4859 } | |
4860 | |
4861 // Adjust recv_klass by scaled itable_index, so we can free itable_index. | |
4862 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); | |
4863 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); | |
4864 | |
4865 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { | |
4866 // if (scan->interface() == intf) { | |
4867 // result = (klass + scan->offset() + itable_index); | |
4868 // } | |
4869 // } | |
4870 Label search, found_method; | |
4871 | |
4872 for (int peel = 1; peel >= 0; peel--) { | |
4873 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); | |
4874 cmpptr(intf_klass, method_result); | |
4875 | |
4876 if (peel) { | |
4877 jccb(Assembler::equal, found_method); | |
4878 } else { | |
4879 jccb(Assembler::notEqual, search); | |
4880 // (invert the test to fall through to found_method...) | |
4881 } | |
4882 | |
4883 if (!peel) break; | |
4884 | |
4885 bind(search); | |
4886 | |
4887 // Check that the previous entry is non-null. A null entry means that | |
4888 // the receiver class doesn't implement the interface, and wasn't the | |
4889 // same as when the caller was compiled. | |
4890 testptr(method_result, method_result); | |
4891 jcc(Assembler::zero, L_no_such_interface); | |
4892 addptr(scan_temp, scan_step); | |
4893 } | |
4894 | |
4895 bind(found_method); | |
4896 | |
4897 // Got a hit. | |
4898 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); | |
4899 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); | |
4900 } | |
4901 | |
4902 | |
4903 // virtual method calling | |
4904 void MacroAssembler::lookup_virtual_method(Register recv_klass, | |
4905 RegisterOrConstant vtable_index, | |
4906 Register method_result) { | |
4907 const int base = InstanceKlass::vtable_start_offset() * wordSize; | |
4908 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); | |
4909 Address vtable_entry_addr(recv_klass, | |
4910 vtable_index, Address::times_ptr, | |
4911 base + vtableEntry::method_offset_in_bytes()); | |
4912 movptr(method_result, vtable_entry_addr); | |
4913 } | |
4914 | |
4915 | |
4916 void MacroAssembler::check_klass_subtype(Register sub_klass, | |
4917 Register super_klass, | |
4918 Register temp_reg, | |
4919 Label& L_success) { | |
4920 Label L_failure; | |
4921 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); | |
4922 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); | |
4923 bind(L_failure); | |
4924 } | |
4925 | |
4926 | |
4927 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, | |
4928 Register super_klass, | |
4929 Register temp_reg, | |
4930 Label* L_success, | |
4931 Label* L_failure, | |
4932 Label* L_slow_path, | |
4933 RegisterOrConstant super_check_offset) { | |
4934 assert_different_registers(sub_klass, super_klass, temp_reg); | |
4935 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); | |
4936 if (super_check_offset.is_register()) { | |
4937 assert_different_registers(sub_klass, super_klass, | |
4938 super_check_offset.as_register()); | |
4939 } else if (must_load_sco) { | |
4940 assert(temp_reg != noreg, "supply either a temp or a register offset"); | |
4941 } | |
4942 | |
4943 Label L_fallthrough; | |
4944 int label_nulls = 0; | |
4945 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | |
4946 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | |
4947 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } | |
4948 assert(label_nulls <= 1, "at most one NULL in the batch"); | |
4949 | |
4950 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); | |
4951 int sco_offset = in_bytes(Klass::super_check_offset_offset()); | |
4952 Address super_check_offset_addr(super_klass, sco_offset); | |
4953 | |
4954 // Hacked jcc, which "knows" that L_fallthrough, at least, is in | |
4955 // range of a jccb. If this routine grows larger, reconsider at | |
4956 // least some of these. | |
4957 #define local_jcc(assembler_cond, label) \ | |
4958 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ | |
4959 else jcc( assembler_cond, label) /*omit semi*/ | |
4960 | |
4961 // Hacked jmp, which may only be used just before L_fallthrough. | |
4962 #define final_jmp(label) \ | |
4963 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ | |
4964 else jmp(label) /*omit semi*/ | |
4965 | |
4966 // If the pointers are equal, we are done (e.g., String[] elements). | |
4967 // This self-check enables sharing of secondary supertype arrays among | |
4968 // non-primary types such as array-of-interface. Otherwise, each such | |
4969 // type would need its own customized SSA. | |
4970 // We move this check to the front of the fast path because many | |
4971 // type checks are in fact trivially successful in this manner, | |
4972 // so we get a nicely predicted branch right at the start of the check. | |
4973 cmpptr(sub_klass, super_klass); | |
4974 local_jcc(Assembler::equal, *L_success); | |
4975 | |
4976 // Check the supertype display: | |
4977 if (must_load_sco) { | |
4978 // Positive movl does right thing on LP64. | |
4979 movl(temp_reg, super_check_offset_addr); | |
4980 super_check_offset = RegisterOrConstant(temp_reg); | |
4981 } | |
4982 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); | |
4983 cmpptr(super_klass, super_check_addr); // load displayed supertype | |
4984 | |
4985 // This check has worked decisively for primary supers. | |
4986 // Secondary supers are sought in the super_cache ('super_cache_addr'). | |
4987 // (Secondary supers are interfaces and very deeply nested subtypes.) | |
4988 // This works in the same check above because of a tricky aliasing | |
4989 // between the super_cache and the primary super display elements. | |
4990 // (The 'super_check_addr' can address either, as the case requires.) | |
4991 // Note that the cache is updated below if it does not help us find | |
4992 // what we need immediately. | |
4993 // So if it was a primary super, we can just fail immediately. | |
4994 // Otherwise, it's the slow path for us (no success at this point). | |
4995 | |
4996 if (super_check_offset.is_register()) { | |
4997 local_jcc(Assembler::equal, *L_success); | |
4998 cmpl(super_check_offset.as_register(), sc_offset); | |
4999 if (L_failure == &L_fallthrough) { | |
5000 local_jcc(Assembler::equal, *L_slow_path); | |
5001 } else { | |
5002 local_jcc(Assembler::notEqual, *L_failure); | |
5003 final_jmp(*L_slow_path); | |
5004 } | |
5005 } else if (super_check_offset.as_constant() == sc_offset) { | |
5006 // Need a slow path; fast failure is impossible. | |
5007 if (L_slow_path == &L_fallthrough) { | |
5008 local_jcc(Assembler::equal, *L_success); | |
5009 } else { | |
5010 local_jcc(Assembler::notEqual, *L_slow_path); | |
5011 final_jmp(*L_success); | |
5012 } | |
5013 } else { | |
5014 // No slow path; it's a fast decision. | |
5015 if (L_failure == &L_fallthrough) { | |
5016 local_jcc(Assembler::equal, *L_success); | |
5017 } else { | |
5018 local_jcc(Assembler::notEqual, *L_failure); | |
5019 final_jmp(*L_success); | |
5020 } | |
5021 } | |
5022 | |
5023 bind(L_fallthrough); | |
5024 | |
5025 #undef local_jcc | |
5026 #undef final_jmp | |
5027 } | |
5028 | |
5029 | |
5030 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, | |
5031 Register super_klass, | |
5032 Register temp_reg, | |
5033 Register temp2_reg, | |
5034 Label* L_success, | |
5035 Label* L_failure, | |
5036 bool set_cond_codes) { | |
5037 assert_different_registers(sub_klass, super_klass, temp_reg); | |
5038 if (temp2_reg != noreg) | |
5039 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); | |
5040 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) | |
5041 | |
5042 Label L_fallthrough; | |
5043 int label_nulls = 0; | |
5044 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } | |
5045 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } | |
5046 assert(label_nulls <= 1, "at most one NULL in the batch"); | |
5047 | |
5048 // a couple of useful fields in sub_klass: | |
5049 int ss_offset = in_bytes(Klass::secondary_supers_offset()); | |
5050 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); | |
5051 Address secondary_supers_addr(sub_klass, ss_offset); | |
5052 Address super_cache_addr( sub_klass, sc_offset); | |
5053 | |
5054 // Do a linear scan of the secondary super-klass chain. | |
5055 // This code is rarely used, so simplicity is a virtue here. | |
5056 // The repne_scan instruction uses fixed registers, which we must spill. | |
5057 // Don't worry too much about pre-existing connections with the input regs. | |
5058 | |
5059 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) | |
5060 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) | |
5061 | |
5062 // Get super_klass value into rax (even if it was in rdi or rcx). | |
5063 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; | |
5064 if (super_klass != rax || UseCompressedOops) { | |
5065 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } | |
5066 mov(rax, super_klass); | |
5067 } | |
5068 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } | |
5069 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } | |
5070 | |
5071 #ifndef PRODUCT | |
5072 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; | |
5073 ExternalAddress pst_counter_addr((address) pst_counter); | |
5074 NOT_LP64( incrementl(pst_counter_addr) ); | |
5075 LP64_ONLY( lea(rcx, pst_counter_addr) ); | |
5076 LP64_ONLY( incrementl(Address(rcx, 0)) ); | |
5077 #endif //PRODUCT | |
5078 | |
5079 // We will consult the secondary-super array. | |
5080 movptr(rdi, secondary_supers_addr); | |
5081 // Load the array length. (Positive movl does right thing on LP64.) | |
5082 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); | |
5083 // Skip to start of data. | |
5084 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); | |
5085 | |
5086 // Scan RCX words at [RDI] for an occurrence of RAX. | |
5087 // Set NZ/Z based on last compare. | |
5088 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does | |
5089 // not change flags (only scas instruction which is repeated sets flags). | |
5090 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. | |
5091 | |
5092 testptr(rax,rax); // Set Z = 0 | |
5093 repne_scan(); | |
5094 | |
5095 // Unspill the temp. registers: | |
5096 if (pushed_rdi) pop(rdi); | |
5097 if (pushed_rcx) pop(rcx); | |
5098 if (pushed_rax) pop(rax); | |
5099 | |
5100 if (set_cond_codes) { | |
5101 // Special hack for the AD files: rdi is guaranteed non-zero. | |
5102 assert(!pushed_rdi, "rdi must be left non-NULL"); | |
5103 // Also, the condition codes are properly set Z/NZ on succeed/failure. | |
5104 } | |
5105 | |
5106 if (L_failure == &L_fallthrough) | |
5107 jccb(Assembler::notEqual, *L_failure); | |
5108 else jcc(Assembler::notEqual, *L_failure); | |
5109 | |
5110 // Success. Cache the super we found and proceed in triumph. | |
5111 movptr(super_cache_addr, super_klass); | |
5112 | |
5113 if (L_success != &L_fallthrough) { | |
5114 jmp(*L_success); | |
5115 } | |
5116 | |
5117 #undef IS_A_TEMP | |
5118 | |
5119 bind(L_fallthrough); | |
5120 } | |
5121 | |
5122 | |
5123 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { | |
5124 if (VM_Version::supports_cmov()) { | |
5125 cmovl(cc, dst, src); | |
5126 } else { | |
5127 Label L; | |
5128 jccb(negate_condition(cc), L); | |
5129 movl(dst, src); | |
5130 bind(L); | |
5131 } | |
5132 } | |
5133 | |
5134 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { | |
5135 if (VM_Version::supports_cmov()) { | |
5136 cmovl(cc, dst, src); | |
5137 } else { | |
5138 Label L; | |
5139 jccb(negate_condition(cc), L); | |
5140 movl(dst, src); | |
5141 bind(L); | |
5142 } | |
5143 } | |
5144 | |
5145 void MacroAssembler::verify_oop(Register reg, const char* s) { | |
5146 if (!VerifyOops) return; | |
5147 | |
5148 // Pass register number to verify_oop_subroutine | |
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5149 const char* b = NULL; |
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5150 { |
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5151 ResourceMark rm; |
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5152 stringStream ss; |
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5153 ss.print("verify_oop: %s: %s", reg->name(), s); |
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5154 b = code_string(ss.as_string()); |
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5155 } |
7199 | 5156 BLOCK_COMMENT("verify_oop {"); |
5157 #ifdef _LP64 | |
5158 push(rscratch1); // save r10, trashed by movptr() | |
5159 #endif | |
5160 push(rax); // save rax, | |
5161 push(reg); // pass register argument | |
5162 ExternalAddress buffer((address) b); | |
5163 // avoid using pushptr, as it modifies scratch registers | |
5164 // and our contract is not to modify anything | |
5165 movptr(rax, buffer.addr()); | |
5166 push(rax); | |
5167 // call indirectly to solve generation ordering problem | |
5168 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
5169 call(rax); | |
5170 // Caller pops the arguments (oop, message) and restores rax, r10 | |
5171 BLOCK_COMMENT("} verify_oop"); | |
5172 } | |
5173 | |
5174 | |
5175 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, | |
5176 Register tmp, | |
5177 int offset) { | |
5178 intptr_t value = *delayed_value_addr; | |
5179 if (value != 0) | |
5180 return RegisterOrConstant(value + offset); | |
5181 | |
5182 // load indirectly to solve generation ordering problem | |
5183 movptr(tmp, ExternalAddress((address) delayed_value_addr)); | |
5184 | |
5185 #ifdef ASSERT | |
5186 { Label L; | |
5187 testptr(tmp, tmp); | |
5188 if (WizardMode) { | |
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5189 const char* buf = NULL; |
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5190 { |
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5191 ResourceMark rm; |
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5192 stringStream ss; |
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5193 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
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5194 buf = code_string(ss.as_string()); |
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5195 } |
7199 | 5196 jcc(Assembler::notZero, L); |
5197 STOP(buf); | |
5198 } else { | |
5199 jccb(Assembler::notZero, L); | |
5200 hlt(); | |
5201 } | |
5202 bind(L); | |
5203 } | |
5204 #endif | |
5205 | |
5206 if (offset != 0) | |
5207 addptr(tmp, offset); | |
5208 | |
5209 return RegisterOrConstant(tmp); | |
5210 } | |
5211 | |
5212 | |
5213 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
5214 int extra_slot_offset) { | |
5215 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
5216 int stackElementSize = Interpreter::stackElementSize; | |
5217 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); | |
5218 #ifdef ASSERT | |
5219 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
5220 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
5221 #endif | |
5222 Register scale_reg = noreg; | |
5223 Address::ScaleFactor scale_factor = Address::no_scale; | |
5224 if (arg_slot.is_constant()) { | |
5225 offset += arg_slot.as_constant() * stackElementSize; | |
5226 } else { | |
5227 scale_reg = arg_slot.as_register(); | |
5228 scale_factor = Address::times(stackElementSize); | |
5229 } | |
5230 offset += wordSize; // return PC is on stack | |
5231 return Address(rsp, scale_reg, scale_factor, offset); | |
5232 } | |
5233 | |
5234 | |
5235 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { | |
5236 if (!VerifyOops) return; | |
5237 | |
5238 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); | |
5239 // Pass register number to verify_oop_subroutine | |
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5240 const char* b = NULL; |
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5241 { |
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5242 ResourceMark rm; |
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5243 stringStream ss; |
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5244 ss.print("verify_oop_addr: %s", s); |
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5245 b = code_string(ss.as_string()); |
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5246 } |
7199 | 5247 #ifdef _LP64 |
5248 push(rscratch1); // save r10, trashed by movptr() | |
5249 #endif | |
5250 push(rax); // save rax, | |
5251 // addr may contain rsp so we will have to adjust it based on the push | |
5252 // we just did (and on 64 bit we do two pushes) | |
5253 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which | |
5254 // stores rax into addr which is backwards of what was intended. | |
5255 if (addr.uses(rsp)) { | |
5256 lea(rax, addr); | |
5257 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); | |
5258 } else { | |
5259 pushptr(addr); | |
5260 } | |
5261 | |
5262 ExternalAddress buffer((address) b); | |
5263 // pass msg argument | |
5264 // avoid using pushptr, as it modifies scratch registers | |
5265 // and our contract is not to modify anything | |
5266 movptr(rax, buffer.addr()); | |
5267 push(rax); | |
5268 | |
5269 // call indirectly to solve generation ordering problem | |
5270 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
5271 call(rax); | |
5272 // Caller pops the arguments (addr, message) and restores rax, r10. | |
5273 } | |
5274 | |
5275 void MacroAssembler::verify_tlab() { | |
5276 #ifdef ASSERT | |
5277 if (UseTLAB && VerifyOops) { | |
5278 Label next, ok; | |
5279 Register t1 = rsi; | |
5280 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
5281 | |
5282 push(t1); | |
5283 NOT_LP64(push(thread_reg)); | |
5284 NOT_LP64(get_thread(thread_reg)); | |
5285 | |
5286 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
5287 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
5288 jcc(Assembler::aboveEqual, next); | |
5289 STOP("assert(top >= start)"); | |
5290 should_not_reach_here(); | |
5291 | |
5292 bind(next); | |
5293 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
5294 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
5295 jcc(Assembler::aboveEqual, ok); | |
5296 STOP("assert(top <= end)"); | |
5297 should_not_reach_here(); | |
5298 | |
5299 bind(ok); | |
5300 NOT_LP64(pop(thread_reg)); | |
5301 pop(t1); | |
5302 } | |
5303 #endif | |
5304 } | |
5305 | |
5306 class ControlWord { | |
5307 public: | |
5308 int32_t _value; | |
5309 | |
5310 int rounding_control() const { return (_value >> 10) & 3 ; } | |
5311 int precision_control() const { return (_value >> 8) & 3 ; } | |
5312 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
5313 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
5314 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
5315 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
5316 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
5317 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
5318 | |
5319 void print() const { | |
5320 // rounding control | |
5321 const char* rc; | |
5322 switch (rounding_control()) { | |
5323 case 0: rc = "round near"; break; | |
5324 case 1: rc = "round down"; break; | |
5325 case 2: rc = "round up "; break; | |
5326 case 3: rc = "chop "; break; | |
5327 }; | |
5328 // precision control | |
5329 const char* pc; | |
5330 switch (precision_control()) { | |
5331 case 0: pc = "24 bits "; break; | |
5332 case 1: pc = "reserved"; break; | |
5333 case 2: pc = "53 bits "; break; | |
5334 case 3: pc = "64 bits "; break; | |
5335 }; | |
5336 // flags | |
5337 char f[9]; | |
5338 f[0] = ' '; | |
5339 f[1] = ' '; | |
5340 f[2] = (precision ()) ? 'P' : 'p'; | |
5341 f[3] = (underflow ()) ? 'U' : 'u'; | |
5342 f[4] = (overflow ()) ? 'O' : 'o'; | |
5343 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
5344 f[6] = (denormalized()) ? 'D' : 'd'; | |
5345 f[7] = (invalid ()) ? 'I' : 'i'; | |
5346 f[8] = '\x0'; | |
5347 // output | |
5348 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
5349 } | |
5350 | |
5351 }; | |
5352 | |
5353 class StatusWord { | |
5354 public: | |
5355 int32_t _value; | |
5356 | |
5357 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
5358 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
5359 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
5360 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
5361 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
5362 int top() const { return (_value >> 11) & 7 ; } | |
5363 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
5364 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
5365 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
5366 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
5367 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
5368 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
5369 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
5370 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
5371 | |
5372 void print() const { | |
5373 // condition codes | |
5374 char c[5]; | |
5375 c[0] = (C3()) ? '3' : '-'; | |
5376 c[1] = (C2()) ? '2' : '-'; | |
5377 c[2] = (C1()) ? '1' : '-'; | |
5378 c[3] = (C0()) ? '0' : '-'; | |
5379 c[4] = '\x0'; | |
5380 // flags | |
5381 char f[9]; | |
5382 f[0] = (error_status()) ? 'E' : '-'; | |
5383 f[1] = (stack_fault ()) ? 'S' : '-'; | |
5384 f[2] = (precision ()) ? 'P' : '-'; | |
5385 f[3] = (underflow ()) ? 'U' : '-'; | |
5386 f[4] = (overflow ()) ? 'O' : '-'; | |
5387 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
5388 f[6] = (denormalized()) ? 'D' : '-'; | |
5389 f[7] = (invalid ()) ? 'I' : '-'; | |
5390 f[8] = '\x0'; | |
5391 // output | |
5392 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
5393 } | |
5394 | |
5395 }; | |
5396 | |
5397 class TagWord { | |
5398 public: | |
5399 int32_t _value; | |
5400 | |
5401 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
5402 | |
5403 void print() const { | |
5404 printf("%04x", _value & 0xFFFF); | |
5405 } | |
5406 | |
5407 }; | |
5408 | |
5409 class FPU_Register { | |
5410 public: | |
5411 int32_t _m0; | |
5412 int32_t _m1; | |
5413 int16_t _ex; | |
5414 | |
5415 bool is_indefinite() const { | |
5416 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
5417 } | |
5418 | |
5419 void print() const { | |
5420 char sign = (_ex < 0) ? '-' : '+'; | |
5421 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
5422 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
5423 }; | |
5424 | |
5425 }; | |
5426 | |
5427 class FPU_State { | |
5428 public: | |
5429 enum { | |
5430 register_size = 10, | |
5431 number_of_registers = 8, | |
5432 register_mask = 7 | |
5433 }; | |
5434 | |
5435 ControlWord _control_word; | |
5436 StatusWord _status_word; | |
5437 TagWord _tag_word; | |
5438 int32_t _error_offset; | |
5439 int32_t _error_selector; | |
5440 int32_t _data_offset; | |
5441 int32_t _data_selector; | |
5442 int8_t _register[register_size * number_of_registers]; | |
5443 | |
5444 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
5445 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
5446 | |
5447 const char* tag_as_string(int tag) const { | |
5448 switch (tag) { | |
5449 case 0: return "valid"; | |
5450 case 1: return "zero"; | |
5451 case 2: return "special"; | |
5452 case 3: return "empty"; | |
5453 } | |
5454 ShouldNotReachHere(); | |
5455 return NULL; | |
5456 } | |
5457 | |
5458 void print() const { | |
5459 // print computation registers | |
5460 { int t = _status_word.top(); | |
5461 for (int i = 0; i < number_of_registers; i++) { | |
5462 int j = (i - t) & register_mask; | |
5463 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
5464 st(j)->print(); | |
5465 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
5466 } | |
5467 } | |
5468 printf("\n"); | |
5469 // print control registers | |
5470 printf("ctrl = "); _control_word.print(); printf("\n"); | |
5471 printf("stat = "); _status_word .print(); printf("\n"); | |
5472 printf("tags = "); _tag_word .print(); printf("\n"); | |
5473 } | |
5474 | |
5475 }; | |
5476 | |
5477 class Flag_Register { | |
5478 public: | |
5479 int32_t _value; | |
5480 | |
5481 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
5482 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
5483 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
5484 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
5485 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
5486 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
5487 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
5488 | |
5489 void print() const { | |
5490 // flags | |
5491 char f[8]; | |
5492 f[0] = (overflow ()) ? 'O' : '-'; | |
5493 f[1] = (direction ()) ? 'D' : '-'; | |
5494 f[2] = (sign ()) ? 'S' : '-'; | |
5495 f[3] = (zero ()) ? 'Z' : '-'; | |
5496 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
5497 f[5] = (parity ()) ? 'P' : '-'; | |
5498 f[6] = (carry ()) ? 'C' : '-'; | |
5499 f[7] = '\x0'; | |
5500 // output | |
5501 printf("%08x flags = %s", _value, f); | |
5502 } | |
5503 | |
5504 }; | |
5505 | |
5506 class IU_Register { | |
5507 public: | |
5508 int32_t _value; | |
5509 | |
5510 void print() const { | |
5511 printf("%08x %11d", _value, _value); | |
5512 } | |
5513 | |
5514 }; | |
5515 | |
5516 class IU_State { | |
5517 public: | |
5518 Flag_Register _eflags; | |
5519 IU_Register _rdi; | |
5520 IU_Register _rsi; | |
5521 IU_Register _rbp; | |
5522 IU_Register _rsp; | |
5523 IU_Register _rbx; | |
5524 IU_Register _rdx; | |
5525 IU_Register _rcx; | |
5526 IU_Register _rax; | |
5527 | |
5528 void print() const { | |
5529 // computation registers | |
5530 printf("rax, = "); _rax.print(); printf("\n"); | |
5531 printf("rbx, = "); _rbx.print(); printf("\n"); | |
5532 printf("rcx = "); _rcx.print(); printf("\n"); | |
5533 printf("rdx = "); _rdx.print(); printf("\n"); | |
5534 printf("rdi = "); _rdi.print(); printf("\n"); | |
5535 printf("rsi = "); _rsi.print(); printf("\n"); | |
5536 printf("rbp, = "); _rbp.print(); printf("\n"); | |
5537 printf("rsp = "); _rsp.print(); printf("\n"); | |
5538 printf("\n"); | |
5539 // control registers | |
5540 printf("flgs = "); _eflags.print(); printf("\n"); | |
5541 } | |
5542 }; | |
5543 | |
5544 | |
5545 class CPU_State { | |
5546 public: | |
5547 FPU_State _fpu_state; | |
5548 IU_State _iu_state; | |
5549 | |
5550 void print() const { | |
5551 printf("--------------------------------------------------\n"); | |
5552 _iu_state .print(); | |
5553 printf("\n"); | |
5554 _fpu_state.print(); | |
5555 printf("--------------------------------------------------\n"); | |
5556 } | |
5557 | |
5558 }; | |
5559 | |
5560 | |
5561 static void _print_CPU_state(CPU_State* state) { | |
5562 state->print(); | |
5563 }; | |
5564 | |
5565 | |
5566 void MacroAssembler::print_CPU_state() { | |
5567 push_CPU_state(); | |
5568 push(rsp); // pass CPU state | |
5569 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); | |
5570 addptr(rsp, wordSize); // discard argument | |
5571 pop_CPU_state(); | |
5572 } | |
5573 | |
5574 | |
5575 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
5576 static int counter = 0; | |
5577 FPU_State* fs = &state->_fpu_state; | |
5578 counter++; | |
5579 // For leaf calls, only verify that the top few elements remain empty. | |
5580 // We only need 1 empty at the top for C2 code. | |
5581 if( stack_depth < 0 ) { | |
5582 if( fs->tag_for_st(7) != 3 ) { | |
5583 printf("FPR7 not empty\n"); | |
5584 state->print(); | |
5585 assert(false, "error"); | |
5586 return false; | |
5587 } | |
5588 return true; // All other stack states do not matter | |
5589 } | |
5590 | |
5591 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
5592 "bad FPU control word"); | |
5593 | |
5594 // compute stack depth | |
5595 int i = 0; | |
5596 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
5597 int d = i; | |
5598 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
5599 // verify findings | |
5600 if (i != FPU_State::number_of_registers) { | |
5601 // stack not contiguous | |
5602 printf("%s: stack not contiguous at ST%d\n", s, i); | |
5603 state->print(); | |
5604 assert(false, "error"); | |
5605 return false; | |
5606 } | |
5607 // check if computed stack depth corresponds to expected stack depth | |
5608 if (stack_depth < 0) { | |
5609 // expected stack depth is -stack_depth or less | |
5610 if (d > -stack_depth) { | |
5611 // too many elements on the stack | |
5612 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
5613 state->print(); | |
5614 assert(false, "error"); | |
5615 return false; | |
5616 } | |
5617 } else { | |
5618 // expected stack depth is stack_depth | |
5619 if (d != stack_depth) { | |
5620 // wrong stack depth | |
5621 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
5622 state->print(); | |
5623 assert(false, "error"); | |
5624 return false; | |
5625 } | |
5626 } | |
5627 // everything is cool | |
5628 return true; | |
5629 } | |
5630 | |
5631 | |
5632 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
5633 if (!VerifyFPU) return; | |
5634 push_CPU_state(); | |
5635 push(rsp); // pass CPU state | |
5636 ExternalAddress msg((address) s); | |
5637 // pass message string s | |
5638 pushptr(msg.addr()); | |
5639 push(stack_depth); // pass stack depth | |
5640 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); | |
5641 addptr(rsp, 3 * wordSize); // discard arguments | |
5642 // check for error | |
5643 { Label L; | |
5644 testl(rax, rax); | |
5645 jcc(Assembler::notZero, L); | |
5646 int3(); // break if error condition | |
5647 bind(L); | |
5648 } | |
5649 pop_CPU_state(); | |
5650 } | |
5651 | |
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5652 void MacroAssembler::restore_cpu_control_state_after_jni() { |
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5653 // Either restore the MXCSR register after returning from the JNI Call |
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5654 // or verify that it wasn't changed (with -Xcheck:jni flag). |
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5655 if (VM_Version::supports_sse()) { |
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changeset
|
5656 if (RestoreMXCSROnJNICalls) { |
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5657 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); |
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5658 } else if (CheckJNICalls) { |
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5659 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); |
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|
5660 } |
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|
5661 } |
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diff
changeset
|
5662 if (VM_Version::supports_avx()) { |
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diff
changeset
|
5663 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. |
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diff
changeset
|
5664 vzeroupper(); |
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|
5665 } |
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changeset
|
5666 |
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changeset
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5667 #ifndef _LP64 |
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5668 // Either restore the x87 floating pointer control word after returning |
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changeset
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5669 // from the JNI call or verify that it wasn't changed. |
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|
5670 if (CheckJNICalls) { |
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changeset
|
5671 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); |
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|
5672 } |
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changeset
|
5673 #endif // _LP64 |
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changeset
|
5674 } |
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changeset
|
5675 |
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|
5676 |
7199 | 5677 void MacroAssembler::load_klass(Register dst, Register src) { |
5678 #ifdef _LP64 | |
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diff
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|
5679 if (UseCompressedClassPointers) { |
7199 | 5680 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
5681 decode_klass_not_null(dst); | |
5682 } else | |
5683 #endif | |
5684 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
5685 } | |
5686 | |
5687 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
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11080
diff
changeset
|
5688 load_klass(dst, src); |
740e263c80c6
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diff
changeset
|
5689 movptr(dst, Address(dst, Klass::prototype_header_offset())); |
7199 | 5690 } |
5691 | |
5692 void MacroAssembler::store_klass(Register dst, Register src) { | |
5693 #ifdef _LP64 | |
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diff
changeset
|
5694 if (UseCompressedClassPointers) { |
7199 | 5695 encode_klass_not_null(src); |
5696 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
5697 } else | |
5698 #endif | |
5699 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
5700 } | |
5701 | |
5702 void MacroAssembler::load_heap_oop(Register dst, Address src) { | |
5703 #ifdef _LP64 | |
5704 // FIXME: Must change all places where we try to load the klass. | |
5705 if (UseCompressedOops) { | |
5706 movl(dst, src); | |
5707 decode_heap_oop(dst); | |
5708 } else | |
5709 #endif | |
5710 movptr(dst, src); | |
5711 } | |
5712 | |
5713 // Doesn't do verfication, generates fixed size code | |
5714 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { | |
5715 #ifdef _LP64 | |
5716 if (UseCompressedOops) { | |
5717 movl(dst, src); | |
5718 decode_heap_oop_not_null(dst); | |
5719 } else | |
5720 #endif | |
5721 movptr(dst, src); | |
5722 } | |
5723 | |
5724 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
5725 #ifdef _LP64 | |
5726 if (UseCompressedOops) { | |
5727 assert(!dst.uses(src), "not enough registers"); | |
5728 encode_heap_oop(src); | |
5729 movl(dst, src); | |
5730 } else | |
5731 #endif | |
5732 movptr(dst, src); | |
5733 } | |
5734 | |
5735 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { | |
5736 assert_different_registers(src1, tmp); | |
5737 #ifdef _LP64 | |
5738 if (UseCompressedOops) { | |
5739 bool did_push = false; | |
5740 if (tmp == noreg) { | |
5741 tmp = rax; | |
5742 push(tmp); | |
5743 did_push = true; | |
5744 assert(!src2.uses(rsp), "can't push"); | |
5745 } | |
5746 load_heap_oop(tmp, src2); | |
5747 cmpptr(src1, tmp); | |
5748 if (did_push) pop(tmp); | |
5749 } else | |
5750 #endif | |
5751 cmpptr(src1, src2); | |
5752 } | |
5753 | |
5754 // Used for storing NULLs. | |
5755 void MacroAssembler::store_heap_oop_null(Address dst) { | |
5756 #ifdef _LP64 | |
5757 if (UseCompressedOops) { | |
5758 movl(dst, (int32_t)NULL_WORD); | |
5759 } else { | |
5760 movslq(dst, (int32_t)NULL_WORD); | |
5761 } | |
5762 #else | |
5763 movl(dst, (int32_t)NULL_WORD); | |
5764 #endif | |
5765 } | |
5766 | |
5767 #ifdef _LP64 | |
5768 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
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diff
changeset
|
5769 if (UseCompressedClassPointers) { |
7199 | 5770 // Store to klass gap in destination |
5771 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
5772 } | |
5773 } | |
5774 | |
5775 #ifdef ASSERT | |
5776 void MacroAssembler::verify_heapbase(const char* msg) { | |
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diff
changeset
|
5777 assert (UseCompressedOops, "should be compressed"); |
7199 | 5778 assert (Universe::heap() != NULL, "java heap should be initialized"); |
5779 if (CheckCompressedOops) { | |
5780 Label ok; | |
5781 push(rscratch1); // cmpptr trashes rscratch1 | |
5782 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); | |
5783 jcc(Assembler::equal, ok); | |
5784 STOP(msg); | |
5785 bind(ok); | |
5786 pop(rscratch1); | |
5787 } | |
5788 } | |
5789 #endif | |
5790 | |
5791 // Algorithm must match oop.inline.hpp encode_heap_oop. | |
5792 void MacroAssembler::encode_heap_oop(Register r) { | |
5793 #ifdef ASSERT | |
5794 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); | |
5795 #endif | |
5796 verify_oop(r, "broken oop in encode_heap_oop"); | |
5797 if (Universe::narrow_oop_base() == NULL) { | |
5798 if (Universe::narrow_oop_shift() != 0) { | |
5799 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5800 shrq(r, LogMinObjAlignmentInBytes); | |
5801 } | |
5802 return; | |
5803 } | |
5804 testq(r, r); | |
5805 cmovq(Assembler::equal, r, r12_heapbase); | |
5806 subq(r, r12_heapbase); | |
5807 shrq(r, LogMinObjAlignmentInBytes); | |
5808 } | |
5809 | |
5810 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
5811 #ifdef ASSERT | |
5812 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); | |
5813 if (CheckCompressedOops) { | |
5814 Label ok; | |
5815 testq(r, r); | |
5816 jcc(Assembler::notEqual, ok); | |
5817 STOP("null oop passed to encode_heap_oop_not_null"); | |
5818 bind(ok); | |
5819 } | |
5820 #endif | |
5821 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
5822 if (Universe::narrow_oop_base() != NULL) { | |
5823 subq(r, r12_heapbase); | |
5824 } | |
5825 if (Universe::narrow_oop_shift() != 0) { | |
5826 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5827 shrq(r, LogMinObjAlignmentInBytes); | |
5828 } | |
5829 } | |
5830 | |
5831 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
5832 #ifdef ASSERT | |
5833 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); | |
5834 if (CheckCompressedOops) { | |
5835 Label ok; | |
5836 testq(src, src); | |
5837 jcc(Assembler::notEqual, ok); | |
5838 STOP("null oop passed to encode_heap_oop_not_null2"); | |
5839 bind(ok); | |
5840 } | |
5841 #endif | |
5842 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); | |
5843 if (dst != src) { | |
5844 movq(dst, src); | |
5845 } | |
5846 if (Universe::narrow_oop_base() != NULL) { | |
5847 subq(dst, r12_heapbase); | |
5848 } | |
5849 if (Universe::narrow_oop_shift() != 0) { | |
5850 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5851 shrq(dst, LogMinObjAlignmentInBytes); | |
5852 } | |
5853 } | |
5854 | |
5855 void MacroAssembler::decode_heap_oop(Register r) { | |
5856 #ifdef ASSERT | |
5857 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); | |
5858 #endif | |
5859 if (Universe::narrow_oop_base() == NULL) { | |
5860 if (Universe::narrow_oop_shift() != 0) { | |
5861 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5862 shlq(r, LogMinObjAlignmentInBytes); | |
5863 } | |
5864 } else { | |
5865 Label done; | |
5866 shlq(r, LogMinObjAlignmentInBytes); | |
5867 jccb(Assembler::equal, done); | |
5868 addq(r, r12_heapbase); | |
5869 bind(done); | |
5870 } | |
5871 verify_oop(r, "broken oop in decode_heap_oop"); | |
5872 } | |
5873 | |
5874 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
5875 // Note: it will change flags | |
5876 assert (UseCompressedOops, "should only be used for compressed headers"); | |
5877 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
5878 // Cannot assert, unverified entry point counts instructions (see .ad file) | |
5879 // vtableStubs also counts instructions in pd_code_size_limit. | |
5880 // Also do not verify_oop as this is called by verify_oop. | |
5881 if (Universe::narrow_oop_shift() != 0) { | |
5882 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5883 shlq(r, LogMinObjAlignmentInBytes); | |
5884 if (Universe::narrow_oop_base() != NULL) { | |
5885 addq(r, r12_heapbase); | |
5886 } | |
5887 } else { | |
5888 assert (Universe::narrow_oop_base() == NULL, "sanity"); | |
5889 } | |
5890 } | |
5891 | |
5892 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
5893 // Note: it will change flags | |
5894 assert (UseCompressedOops, "should only be used for compressed headers"); | |
5895 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
5896 // Cannot assert, unverified entry point counts instructions (see .ad file) | |
5897 // vtableStubs also counts instructions in pd_code_size_limit. | |
5898 // Also do not verify_oop as this is called by verify_oop. | |
5899 if (Universe::narrow_oop_shift() != 0) { | |
5900 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); | |
5901 if (LogMinObjAlignmentInBytes == Address::times_8) { | |
5902 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); | |
5903 } else { | |
5904 if (dst != src) { | |
5905 movq(dst, src); | |
5906 } | |
5907 shlq(dst, LogMinObjAlignmentInBytes); | |
5908 if (Universe::narrow_oop_base() != NULL) { | |
5909 addq(dst, r12_heapbase); | |
5910 } | |
5911 } | |
5912 } else { | |
5913 assert (Universe::narrow_oop_base() == NULL, "sanity"); | |
5914 if (dst != src) { | |
5915 movq(dst, src); | |
5916 } | |
5917 } | |
5918 } | |
5919 | |
5920 void MacroAssembler::encode_klass_not_null(Register r) { | |
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12835
diff
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|
5921 if (Universe::narrow_klass_base() != NULL) { |
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coleenp
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diff
changeset
|
5922 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. |
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8024927: Nashorn performance regression with CompressedOops
coleenp
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diff
changeset
|
5923 assert(r != r12_heapbase, "Encoding a klass in r12"); |
209aa13ab8c0
8024927: Nashorn performance regression with CompressedOops
coleenp
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12835
diff
changeset
|
5924 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); |
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8024927: Nashorn performance regression with CompressedOops
coleenp
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12835
diff
changeset
|
5925 subq(r, r12_heapbase); |
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diff
changeset
|
5926 } |
7199 | 5927 if (Universe::narrow_klass_shift() != 0) { |
5928 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
5929 shrq(r, LogKlassAlignmentInBytes); | |
5930 } | |
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changeset
|
5931 if (Universe::narrow_klass_base() != NULL) { |
209aa13ab8c0
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diff
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|
5932 reinit_heapbase(); |
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diff
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|
5933 } |
7199 | 5934 } |
5935 | |
5936 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { | |
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diff
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|
5937 if (dst == src) { |
740e263c80c6
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11080
diff
changeset
|
5938 encode_klass_not_null(src); |
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diff
changeset
|
5939 } else { |
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209aa13ab8c0
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|
5940 if (Universe::narrow_klass_base() != NULL) { |
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changeset
|
5941 mov64(dst, (int64_t)Universe::narrow_klass_base()); |
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coleenp
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diff
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|
5942 negq(dst); |
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diff
changeset
|
5943 addq(dst, src); |
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diff
changeset
|
5944 } else { |
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diff
changeset
|
5945 movptr(dst, src); |
209aa13ab8c0
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12835
diff
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|
5946 } |
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changeset
|
5947 if (Universe::narrow_klass_shift() != 0) { |
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diff
changeset
|
5948 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
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11080
diff
changeset
|
5949 shrq(dst, LogKlassAlignmentInBytes); |
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diff
changeset
|
5950 } |
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diff
changeset
|
5951 } |
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diff
changeset
|
5952 } |
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diff
changeset
|
5953 |
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diff
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|
5954 // Function instr_size_for_decode_klass_not_null() counts the instructions |
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|
5955 // generated by decode_klass_not_null(register r) and reinit_heapbase(), |
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diff
changeset
|
5956 // when (Universe::heap() != NULL). Hence, if the instructions they |
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
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diff
changeset
|
5957 // generate change, then this method needs to be updated. |
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diff
changeset
|
5958 int MacroAssembler::instr_size_for_decode_klass_not_null() { |
12226
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|
5959 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); |
13000
209aa13ab8c0
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diff
changeset
|
5960 if (Universe::narrow_klass_base() != NULL) { |
209aa13ab8c0
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changeset
|
5961 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). |
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5962 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); |
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diff
changeset
|
5963 } else { |
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8024927: Nashorn performance regression with CompressedOops
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diff
changeset
|
5964 // longest load decode klass function, mov64, leaq |
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diff
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|
5965 return 16; |
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diff
changeset
|
5966 } |
12056
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diff
changeset
|
5967 } |
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diff
changeset
|
5968 |
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diff
changeset
|
5969 // !!! If the instructions that get generated here change then function |
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diff
changeset
|
5970 // instr_size_for_decode_klass_not_null() needs to get updated. |
7199 | 5971 void MacroAssembler::decode_klass_not_null(Register r) { |
5972 // Note: it will change flags | |
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|
5973 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
12056
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|
5974 assert(r != r12_heapbase, "Decoding a klass in r12"); |
7199 | 5975 // Cannot assert, unverified entry point counts instructions (see .ad file) |
5976 // vtableStubs also counts instructions in pd_code_size_limit. | |
5977 // Also do not verify_oop as this is called by verify_oop. | |
5978 if (Universe::narrow_klass_shift() != 0) { | |
5979 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); | |
5980 shlq(r, LogKlassAlignmentInBytes); | |
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|
5981 } |
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changeset
|
5982 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. |
13000
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|
5983 if (Universe::narrow_klass_base() != NULL) { |
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|
5984 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); |
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|
5985 addq(r, r12_heapbase); |
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changeset
|
5986 reinit_heapbase(); |
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|
5987 } |
7199 | 5988 } |
5989 | |
5990 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { | |
5991 // Note: it will change flags | |
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|
5992 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
12056
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|
5993 if (dst == src) { |
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changeset
|
5994 decode_klass_not_null(dst); |
7199 | 5995 } else { |
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changeset
|
5996 // Cannot assert, unverified entry point counts instructions (see .ad file) |
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|
5997 // vtableStubs also counts instructions in pd_code_size_limit. |
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5998 // Also do not verify_oop as this is called by verify_oop. |
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|
5999 mov64(dst, (int64_t)Universe::narrow_klass_base()); |
740e263c80c6
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|
6000 if (Universe::narrow_klass_shift() != 0) { |
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changeset
|
6001 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); |
740e263c80c6
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|
6002 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); |
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|
6003 leaq(dst, Address(dst, src, Address::times_8, 0)); |
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|
6004 } else { |
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|
6005 addq(dst, src); |
7199 | 6006 } |
6007 } | |
6008 } | |
6009 | |
6010 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
6011 assert (UseCompressedOops, "should only be used for compressed headers"); | |
6012 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
6013 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
6014 int oop_index = oop_recorder()->find_index(obj); | |
6015 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
6016 mov_narrow_oop(dst, oop_index, rspec); | |
6017 } | |
6018 | |
6019 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { | |
6020 assert (UseCompressedOops, "should only be used for compressed headers"); | |
6021 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
6022 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
6023 int oop_index = oop_recorder()->find_index(obj); | |
6024 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
6025 mov_narrow_oop(dst, oop_index, rspec); | |
6026 } | |
6027 | |
6028 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { | |
12226
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diff
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|
6029 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
7199 | 6030 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
6031 int klass_index = oop_recorder()->find_index(k); | |
6032 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
12056
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|
6033 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); |
7199 | 6034 } |
6035 | |
6036 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { | |
12226
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changeset
|
6037 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
7199 | 6038 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
6039 int klass_index = oop_recorder()->find_index(k); | |
6040 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
12056
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changeset
|
6041 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); |
7199 | 6042 } |
6043 | |
6044 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { | |
6045 assert (UseCompressedOops, "should only be used for compressed headers"); | |
6046 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
6047 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
6048 int oop_index = oop_recorder()->find_index(obj); | |
6049 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
6050 Assembler::cmp_narrow_oop(dst, oop_index, rspec); | |
6051 } | |
6052 | |
6053 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { | |
6054 assert (UseCompressedOops, "should only be used for compressed headers"); | |
6055 assert (Universe::heap() != NULL, "java heap should be initialized"); | |
6056 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
6057 int oop_index = oop_recorder()->find_index(obj); | |
6058 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
6059 Assembler::cmp_narrow_oop(dst, oop_index, rspec); | |
6060 } | |
6061 | |
6062 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { | |
12226
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changeset
|
6063 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
7199 | 6064 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
6065 int klass_index = oop_recorder()->find_index(k); | |
6066 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
12056
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hseigel
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diff
changeset
|
6067 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); |
7199 | 6068 } |
6069 | |
6070 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { | |
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diff
changeset
|
6071 assert (UseCompressedClassPointers, "should only be used for compressed headers"); |
7199 | 6072 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
6073 int klass_index = oop_recorder()->find_index(k); | |
6074 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
12056
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hseigel
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diff
changeset
|
6075 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); |
7199 | 6076 } |
6077 | |
6078 void MacroAssembler::reinit_heapbase() { | |
12226
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diff
changeset
|
6079 if (UseCompressedOops || UseCompressedClassPointers) { |
12056
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
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diff
changeset
|
6080 if (Universe::heap() != NULL) { |
740e263c80c6
8003424: Enable Class Data Sharing for CompressedOops
hseigel
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diff
changeset
|
6081 if (Universe::narrow_oop_base() == NULL) { |
740e263c80c6
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hseigel
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diff
changeset
|
6082 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); |
740e263c80c6
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hseigel
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diff
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|
6083 } else { |
740e263c80c6
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diff
changeset
|
6084 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); |
740e263c80c6
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hseigel
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diff
changeset
|
6085 } |
740e263c80c6
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diff
changeset
|
6086 } else { |
740e263c80c6
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diff
changeset
|
6087 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); |
740e263c80c6
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hseigel
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diff
changeset
|
6088 } |
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diff
changeset
|
6089 } |
740e263c80c6
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diff
changeset
|
6090 } |
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diff
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|
6091 |
7199 | 6092 #endif // _LP64 |
6093 | |
6094 | |
6095 // C2 compiled method's prolog code. | |
6096 void MacroAssembler::verified_entry(int framesize, bool stack_bang, bool fp_mode_24b) { | |
6097 | |
6098 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
6099 // NativeJump::patch_verified_entry will be able to patch out the entry | |
6100 // code safely. The push to verify stack depth is ok at 5 bytes, | |
6101 // the frame allocation can be either 3 or 6 bytes. So if we don't do | |
6102 // stack bang then we must use the 6 byte frame allocation even if | |
6103 // we have no frame. :-( | |
6104 | |
6105 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
6106 // Remove word for return addr | |
6107 framesize -= wordSize; | |
6108 | |
6109 // Calls to C2R adapters often do not accept exceptional returns. | |
6110 // We require that their callers must bang for them. But be careful, because | |
6111 // some VM calls (such as call site linkage) can use several kilobytes of | |
6112 // stack. But the stack safety zone should account for that. | |
6113 // See bugs 4446381, 4468289, 4497237. | |
6114 if (stack_bang) { | |
6115 generate_stack_overflow_check(framesize); | |
6116 | |
6117 // We always push rbp, so that on return to interpreter rbp, will be | |
6118 // restored correctly and we can correct the stack. | |
6119 push(rbp); | |
6120 // Remove word for ebp | |
6121 framesize -= wordSize; | |
6122 | |
6123 // Create frame | |
6124 if (framesize) { | |
6125 subptr(rsp, framesize); | |
6126 } | |
6127 } else { | |
6128 // Create frame (force generation of a 4 byte immediate value) | |
6129 subptr_imm32(rsp, framesize); | |
6130 | |
6131 // Save RBP register now. | |
6132 framesize -= wordSize; | |
6133 movptr(Address(rsp, framesize), rbp); | |
6134 } | |
6135 | |
6136 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth | |
6137 framesize -= wordSize; | |
6138 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); | |
6139 } | |
6140 | |
6141 #ifndef _LP64 | |
6142 // If method sets FPU control word do it now | |
6143 if (fp_mode_24b) { | |
6144 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
6145 } | |
6146 if (UseSSE >= 2 && VerifyFPU) { | |
6147 verify_FPU(0, "FPU stack must be clean on entry"); | |
6148 } | |
6149 #endif | |
6150 | |
6151 #ifdef ASSERT | |
6152 if (VerifyStackAtCalls) { | |
6153 Label L; | |
6154 push(rax); | |
6155 mov(rax, rsp); | |
6156 andptr(rax, StackAlignmentInBytes-1); | |
6157 cmpptr(rax, StackAlignmentInBytes-wordSize); | |
6158 pop(rax); | |
6159 jcc(Assembler::equal, L); | |
6160 STOP("Stack is not properly aligned!"); | |
6161 bind(L); | |
6162 } | |
6163 #endif | |
6164 | |
6165 } | |
6166 | |
7474
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|
6167 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) { |
00af3a3a8df4
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|
6168 // cnt - number of qwords (8-byte words). |
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|
6169 // base - start address, qword aligned. |
00af3a3a8df4
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|
6170 assert(base==rdi, "base register must be edi for rep stos"); |
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|
6171 assert(tmp==rax, "tmp register must be eax for rep stos"); |
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|
6172 assert(cnt==rcx, "cnt register must be ecx for rep stos"); |
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|
6173 |
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|
6174 xorptr(tmp, tmp); |
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|
6175 if (UseFastStosb) { |
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|
6176 shlptr(cnt,3); // convert to number of bytes |
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|
6177 rep_stosb(); |
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|
6178 } else { |
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|
6179 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM |
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|
6180 rep_stos(); |
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|
6181 } |
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|
6182 } |
7199 | 6183 |
6184 // IndexOf for constant substrings with size >= 8 chars | |
6185 // which don't need to be loaded through stack. | |
6186 void MacroAssembler::string_indexofC8(Register str1, Register str2, | |
6187 Register cnt1, Register cnt2, | |
6188 int int_cnt2, Register result, | |
6189 XMMRegister vec, Register tmp) { | |
6190 ShortBranchVerifier sbv(this); | |
6191 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | |
6192 | |
6193 // This method uses pcmpestri inxtruction with bound registers | |
6194 // inputs: | |
6195 // xmm - substring | |
6196 // rax - substring length (elements count) | |
6197 // mem - scanned string | |
6198 // rdx - string length (elements count) | |
6199 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) | |
6200 // outputs: | |
6201 // rcx - matched index in string | |
6202 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); | |
6203 | |
6204 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, | |
6205 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, | |
6206 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; | |
6207 | |
6208 // Note, inline_string_indexOf() generates checks: | |
6209 // if (substr.count > string.count) return -1; | |
6210 // if (substr.count == 0) return 0; | |
6211 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars"); | |
6212 | |
6213 // Load substring. | |
6214 movdqu(vec, Address(str2, 0)); | |
6215 movl(cnt2, int_cnt2); | |
6216 movptr(result, str1); // string addr | |
6217 | |
6218 if (int_cnt2 > 8) { | |
6219 jmpb(SCAN_TO_SUBSTR); | |
6220 | |
6221 // Reload substr for rescan, this code | |
6222 // is executed only for large substrings (> 8 chars) | |
6223 bind(RELOAD_SUBSTR); | |
6224 movdqu(vec, Address(str2, 0)); | |
6225 negptr(cnt2); // Jumped here with negative cnt2, convert to positive | |
6226 | |
6227 bind(RELOAD_STR); | |
6228 // We came here after the beginning of the substring was | |
6229 // matched but the rest of it was not so we need to search | |
6230 // again. Start from the next element after the previous match. | |
6231 | |
6232 // cnt2 is number of substring reminding elements and | |
6233 // cnt1 is number of string reminding elements when cmp failed. | |
6234 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 | |
6235 subl(cnt1, cnt2); | |
6236 addl(cnt1, int_cnt2); | |
6237 movl(cnt2, int_cnt2); // Now restore cnt2 | |
6238 | |
6239 decrementl(cnt1); // Shift to next element | |
6240 cmpl(cnt1, cnt2); | |
6241 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring | |
6242 | |
6243 addptr(result, 2); | |
6244 | |
6245 } // (int_cnt2 > 8) | |
6246 | |
6247 // Scan string for start of substr in 16-byte vectors | |
6248 bind(SCAN_TO_SUBSTR); | |
6249 pcmpestri(vec, Address(result, 0), 0x0d); | |
6250 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 | |
6251 subl(cnt1, 8); | |
6252 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string | |
6253 cmpl(cnt1, cnt2); | |
6254 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring | |
6255 addptr(result, 16); | |
6256 jmpb(SCAN_TO_SUBSTR); | |
6257 | |
6258 // Found a potential substr | |
6259 bind(FOUND_CANDIDATE); | |
6260 // Matched whole vector if first element matched (tmp(rcx) == 0). | |
6261 if (int_cnt2 == 8) { | |
6262 jccb(Assembler::overflow, RET_FOUND); // OF == 1 | |
6263 } else { // int_cnt2 > 8 | |
6264 jccb(Assembler::overflow, FOUND_SUBSTR); | |
6265 } | |
6266 // After pcmpestri tmp(rcx) contains matched element index | |
6267 // Compute start addr of substr | |
6268 lea(result, Address(result, tmp, Address::times_2)); | |
6269 | |
6270 // Make sure string is still long enough | |
6271 subl(cnt1, tmp); | |
6272 cmpl(cnt1, cnt2); | |
6273 if (int_cnt2 == 8) { | |
6274 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); | |
6275 } else { // int_cnt2 > 8 | |
6276 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); | |
6277 } | |
6278 // Left less then substring. | |
6279 | |
6280 bind(RET_NOT_FOUND); | |
6281 movl(result, -1); | |
6282 jmpb(EXIT); | |
6283 | |
6284 if (int_cnt2 > 8) { | |
6285 // This code is optimized for the case when whole substring | |
6286 // is matched if its head is matched. | |
6287 bind(MATCH_SUBSTR_HEAD); | |
6288 pcmpestri(vec, Address(result, 0), 0x0d); | |
6289 // Reload only string if does not match | |
6290 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 | |
6291 | |
6292 Label CONT_SCAN_SUBSTR; | |
6293 // Compare the rest of substring (> 8 chars). | |
6294 bind(FOUND_SUBSTR); | |
6295 // First 8 chars are already matched. | |
6296 negptr(cnt2); | |
6297 addptr(cnt2, 8); | |
6298 | |
6299 bind(SCAN_SUBSTR); | |
6300 subl(cnt1, 8); | |
6301 cmpl(cnt2, -8); // Do not read beyond substring | |
6302 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); | |
6303 // Back-up strings to avoid reading beyond substring: | |
6304 // cnt1 = cnt1 - cnt2 + 8 | |
6305 addl(cnt1, cnt2); // cnt2 is negative | |
6306 addl(cnt1, 8); | |
6307 movl(cnt2, 8); negptr(cnt2); | |
6308 bind(CONT_SCAN_SUBSTR); | |
6309 if (int_cnt2 < (int)G) { | |
6310 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2)); | |
6311 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d); | |
6312 } else { | |
6313 // calculate index in register to avoid integer overflow (int_cnt2*2) | |
6314 movl(tmp, int_cnt2); | |
6315 addptr(tmp, cnt2); | |
6316 movdqu(vec, Address(str2, tmp, Address::times_2, 0)); | |
6317 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d); | |
6318 } | |
6319 // Need to reload strings pointers if not matched whole vector | |
6320 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 | |
6321 addptr(cnt2, 8); | |
6322 jcc(Assembler::negative, SCAN_SUBSTR); | |
6323 // Fall through if found full substring | |
6324 | |
6325 } // (int_cnt2 > 8) | |
6326 | |
6327 bind(RET_FOUND); | |
6328 // Found result if we matched full small substring. | |
6329 // Compute substr offset | |
6330 subptr(result, str1); | |
6331 shrl(result, 1); // index | |
6332 bind(EXIT); | |
6333 | |
6334 } // string_indexofC8 | |
6335 | |
6336 // Small strings are loaded through stack if they cross page boundary. | |
6337 void MacroAssembler::string_indexof(Register str1, Register str2, | |
6338 Register cnt1, Register cnt2, | |
6339 int int_cnt2, Register result, | |
6340 XMMRegister vec, Register tmp) { | |
6341 ShortBranchVerifier sbv(this); | |
6342 assert(UseSSE42Intrinsics, "SSE4.2 is required"); | |
6343 // | |
6344 // int_cnt2 is length of small (< 8 chars) constant substring | |
6345 // or (-1) for non constant substring in which case its length | |
6346 // is in cnt2 register. | |
6347 // | |
6348 // Note, inline_string_indexOf() generates checks: | |
6349 // if (substr.count > string.count) return -1; | |
6350 // if (substr.count == 0) return 0; | |
6351 // | |
6352 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0"); | |
6353 | |
6354 // This method uses pcmpestri inxtruction with bound registers | |
6355 // inputs: | |
6356 // xmm - substring | |
6357 // rax - substring length (elements count) | |
6358 // mem - scanned string | |
6359 // rdx - string length (elements count) | |
6360 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) | |
6361 // outputs: | |
6362 // rcx - matched index in string | |
6363 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); | |
6364 | |
6365 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, | |
6366 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, | |
6367 FOUND_CANDIDATE; | |
6368 | |
6369 { //======================================================== | |
6370 // We don't know where these strings are located | |
6371 // and we can't read beyond them. Load them through stack. | |
6372 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; | |
6373 | |
6374 movptr(tmp, rsp); // save old SP | |
6375 | |
6376 if (int_cnt2 > 0) { // small (< 8 chars) constant substring | |
6377 if (int_cnt2 == 1) { // One char | |
6378 load_unsigned_short(result, Address(str2, 0)); | |
6379 movdl(vec, result); // move 32 bits | |
6380 } else if (int_cnt2 == 2) { // Two chars | |
6381 movdl(vec, Address(str2, 0)); // move 32 bits | |
6382 } else if (int_cnt2 == 4) { // Four chars | |
6383 movq(vec, Address(str2, 0)); // move 64 bits | |
6384 } else { // cnt2 = { 3, 5, 6, 7 } | |
6385 // Array header size is 12 bytes in 32-bit VM | |
6386 // + 6 bytes for 3 chars == 18 bytes, | |
6387 // enough space to load vec and shift. | |
6388 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); | |
6389 movdqu(vec, Address(str2, (int_cnt2*2)-16)); | |
6390 psrldq(vec, 16-(int_cnt2*2)); | |
6391 } | |
6392 } else { // not constant substring | |
6393 cmpl(cnt2, 8); | |
6394 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough | |
6395 | |
6396 // We can read beyond string if srt+16 does not cross page boundary | |
6397 // since heaps are aligned and mapped by pages. | |
6398 assert(os::vm_page_size() < (int)G, "default page should be small"); | |
6399 movl(result, str2); // We need only low 32 bits | |
6400 andl(result, (os::vm_page_size()-1)); | |
6401 cmpl(result, (os::vm_page_size()-16)); | |
6402 jccb(Assembler::belowEqual, CHECK_STR); | |
6403 | |
6404 // Move small strings to stack to allow load 16 bytes into vec. | |
6405 subptr(rsp, 16); | |
6406 int stk_offset = wordSize-2; | |
6407 push(cnt2); | |
6408 | |
6409 bind(COPY_SUBSTR); | |
6410 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2)); | |
6411 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); | |
6412 decrement(cnt2); | |
6413 jccb(Assembler::notZero, COPY_SUBSTR); | |
6414 | |
6415 pop(cnt2); | |
6416 movptr(str2, rsp); // New substring address | |
6417 } // non constant | |
6418 | |
6419 bind(CHECK_STR); | |
6420 cmpl(cnt1, 8); | |
6421 jccb(Assembler::aboveEqual, BIG_STRINGS); | |
6422 | |
6423 // Check cross page boundary. | |
6424 movl(result, str1); // We need only low 32 bits | |
6425 andl(result, (os::vm_page_size()-1)); | |
6426 cmpl(result, (os::vm_page_size()-16)); | |
6427 jccb(Assembler::belowEqual, BIG_STRINGS); | |
6428 | |
6429 subptr(rsp, 16); | |
6430 int stk_offset = -2; | |
6431 if (int_cnt2 < 0) { // not constant | |
6432 push(cnt2); | |
6433 stk_offset += wordSize; | |
6434 } | |
6435 movl(cnt2, cnt1); | |
6436 | |
6437 bind(COPY_STR); | |
6438 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2)); | |
6439 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result); | |
6440 decrement(cnt2); | |
6441 jccb(Assembler::notZero, COPY_STR); | |
6442 | |
6443 if (int_cnt2 < 0) { // not constant | |
6444 pop(cnt2); | |
6445 } | |
6446 movptr(str1, rsp); // New string address | |
6447 | |
6448 bind(BIG_STRINGS); | |
6449 // Load substring. | |
6450 if (int_cnt2 < 0) { // -1 | |
6451 movdqu(vec, Address(str2, 0)); | |
6452 push(cnt2); // substr count | |
6453 push(str2); // substr addr | |
6454 push(str1); // string addr | |
6455 } else { | |
6456 // Small (< 8 chars) constant substrings are loaded already. | |
6457 movl(cnt2, int_cnt2); | |
6458 } | |
6459 push(tmp); // original SP | |
6460 | |
6461 } // Finished loading | |
6462 | |
6463 //======================================================== | |
6464 // Start search | |
6465 // | |
6466 | |
6467 movptr(result, str1); // string addr | |
6468 | |
6469 if (int_cnt2 < 0) { // Only for non constant substring | |
6470 jmpb(SCAN_TO_SUBSTR); | |
6471 | |
6472 // SP saved at sp+0 | |
6473 // String saved at sp+1*wordSize | |
6474 // Substr saved at sp+2*wordSize | |
6475 // Substr count saved at sp+3*wordSize | |
6476 | |
6477 // Reload substr for rescan, this code | |
6478 // is executed only for large substrings (> 8 chars) | |
6479 bind(RELOAD_SUBSTR); | |
6480 movptr(str2, Address(rsp, 2*wordSize)); | |
6481 movl(cnt2, Address(rsp, 3*wordSize)); | |
6482 movdqu(vec, Address(str2, 0)); | |
6483 // We came here after the beginning of the substring was | |
6484 // matched but the rest of it was not so we need to search | |
6485 // again. Start from the next element after the previous match. | |
6486 subptr(str1, result); // Restore counter | |
6487 shrl(str1, 1); | |
6488 addl(cnt1, str1); | |
6489 decrementl(cnt1); // Shift to next element | |
6490 cmpl(cnt1, cnt2); | |
6491 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring | |
6492 | |
6493 addptr(result, 2); | |
6494 } // non constant | |
6495 | |
6496 // Scan string for start of substr in 16-byte vectors | |
6497 bind(SCAN_TO_SUBSTR); | |
6498 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); | |
6499 pcmpestri(vec, Address(result, 0), 0x0d); | |
6500 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 | |
6501 subl(cnt1, 8); | |
6502 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string | |
6503 cmpl(cnt1, cnt2); | |
6504 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring | |
6505 addptr(result, 16); | |
6506 | |
6507 bind(ADJUST_STR); | |
6508 cmpl(cnt1, 8); // Do not read beyond string | |
6509 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); | |
6510 // Back-up string to avoid reading beyond string. | |
6511 lea(result, Address(result, cnt1, Address::times_2, -16)); | |
6512 movl(cnt1, 8); | |
6513 jmpb(SCAN_TO_SUBSTR); | |
6514 | |
6515 // Found a potential substr | |
6516 bind(FOUND_CANDIDATE); | |
6517 // After pcmpestri tmp(rcx) contains matched element index | |
6518 | |
6519 // Make sure string is still long enough | |
6520 subl(cnt1, tmp); | |
6521 cmpl(cnt1, cnt2); | |
6522 jccb(Assembler::greaterEqual, FOUND_SUBSTR); | |
6523 // Left less then substring. | |
6524 | |
6525 bind(RET_NOT_FOUND); | |
6526 movl(result, -1); | |
6527 jmpb(CLEANUP); | |
6528 | |
6529 bind(FOUND_SUBSTR); | |
6530 // Compute start addr of substr | |
6531 lea(result, Address(result, tmp, Address::times_2)); | |
6532 | |
6533 if (int_cnt2 > 0) { // Constant substring | |
6534 // Repeat search for small substring (< 8 chars) | |
6535 // from new point without reloading substring. | |
6536 // Have to check that we don't read beyond string. | |
6537 cmpl(tmp, 8-int_cnt2); | |
6538 jccb(Assembler::greater, ADJUST_STR); | |
6539 // Fall through if matched whole substring. | |
6540 } else { // non constant | |
6541 assert(int_cnt2 == -1, "should be != 0"); | |
6542 | |
6543 addl(tmp, cnt2); | |
6544 // Found result if we matched whole substring. | |
6545 cmpl(tmp, 8); | |
6546 jccb(Assembler::lessEqual, RET_FOUND); | |
6547 | |
6548 // Repeat search for small substring (<= 8 chars) | |
6549 // from new point 'str1' without reloading substring. | |
6550 cmpl(cnt2, 8); | |
6551 // Have to check that we don't read beyond string. | |
6552 jccb(Assembler::lessEqual, ADJUST_STR); | |
6553 | |
6554 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; | |
6555 // Compare the rest of substring (> 8 chars). | |
6556 movptr(str1, result); | |
6557 | |
6558 cmpl(tmp, cnt2); | |
6559 // First 8 chars are already matched. | |
6560 jccb(Assembler::equal, CHECK_NEXT); | |
6561 | |
6562 bind(SCAN_SUBSTR); | |
6563 pcmpestri(vec, Address(str1, 0), 0x0d); | |
6564 // Need to reload strings pointers if not matched whole vector | |
6565 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 | |
6566 | |
6567 bind(CHECK_NEXT); | |
6568 subl(cnt2, 8); | |
6569 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring | |
6570 addptr(str1, 16); | |
6571 addptr(str2, 16); | |
6572 subl(cnt1, 8); | |
6573 cmpl(cnt2, 8); // Do not read beyond substring | |
6574 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); | |
6575 // Back-up strings to avoid reading beyond substring. | |
6576 lea(str2, Address(str2, cnt2, Address::times_2, -16)); | |
6577 lea(str1, Address(str1, cnt2, Address::times_2, -16)); | |
6578 subl(cnt1, cnt2); | |
6579 movl(cnt2, 8); | |
6580 addl(cnt1, 8); | |
6581 bind(CONT_SCAN_SUBSTR); | |
6582 movdqu(vec, Address(str2, 0)); | |
6583 jmpb(SCAN_SUBSTR); | |
6584 | |
6585 bind(RET_FOUND_LONG); | |
6586 movptr(str1, Address(rsp, wordSize)); | |
6587 } // non constant | |
6588 | |
6589 bind(RET_FOUND); | |
6590 // Compute substr offset | |
6591 subptr(result, str1); | |
6592 shrl(result, 1); // index | |
6593 | |
6594 bind(CLEANUP); | |
6595 pop(rsp); // restore SP | |
6596 | |
6597 } // string_indexof | |
6598 | |
6599 // Compare strings. | |
6600 void MacroAssembler::string_compare(Register str1, Register str2, | |
6601 Register cnt1, Register cnt2, Register result, | |
6602 XMMRegister vec1) { | |
6603 ShortBranchVerifier sbv(this); | |
6604 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; | |
6605 | |
6606 // Compute the minimum of the string lengths and the | |
6607 // difference of the string lengths (stack). | |
6608 // Do the conditional move stuff | |
6609 movl(result, cnt1); | |
6610 subl(cnt1, cnt2); | |
6611 push(cnt1); | |
6612 cmov32(Assembler::lessEqual, cnt2, result); | |
6613 | |
6614 // Is the minimum length zero? | |
6615 testl(cnt2, cnt2); | |
6616 jcc(Assembler::zero, LENGTH_DIFF_LABEL); | |
6617 | |
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6618 // Compare first characters |
7199 | 6619 load_unsigned_short(result, Address(str1, 0)); |
6620 load_unsigned_short(cnt1, Address(str2, 0)); | |
6621 subl(result, cnt1); | |
6622 jcc(Assembler::notZero, POP_LABEL); | |
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6623 cmpl(cnt2, 1); |
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6624 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
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6625 |
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6626 // Check if the strings start at the same location. |
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6627 cmpptr(str1, str2); |
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6628 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
7199 | 6629 |
6630 Address::ScaleFactor scale = Address::times_2; | |
6631 int stride = 8; | |
6632 | |
8042
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6633 if (UseAVX >= 2 && UseSSE42Intrinsics) { |
7477
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6634 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; |
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6635 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; |
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6636 Label COMPARE_TAIL_LONG; |
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6637 int pcmpmask = 0x19; |
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6638 |
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6639 // Setup to compare 16-chars (32-bytes) vectors, |
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6640 // start from first character again because it has aligned address. |
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6641 int stride2 = 16; |
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6642 int adr_stride = stride << scale; |
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6643 int adr_stride2 = stride2 << scale; |
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6644 |
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6645 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); |
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6646 // rax and rdx are used by pcmpestri as elements counters |
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6647 movl(result, cnt2); |
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6648 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count |
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6649 jcc(Assembler::zero, COMPARE_TAIL_LONG); |
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6650 |
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6651 // fast path : compare first 2 8-char vectors. |
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6652 bind(COMPARE_16_CHARS); |
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6653 movdqu(vec1, Address(str1, 0)); |
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6654 pcmpestri(vec1, Address(str2, 0), pcmpmask); |
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6655 jccb(Assembler::below, COMPARE_INDEX_CHAR); |
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6656 |
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6657 movdqu(vec1, Address(str1, adr_stride)); |
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6658 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); |
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6659 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); |
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6660 addl(cnt1, stride); |
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6661 |
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6662 // Compare the characters at index in cnt1 |
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6663 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character |
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6664 load_unsigned_short(result, Address(str1, cnt1, scale)); |
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6665 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); |
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6666 subl(result, cnt2); |
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6667 jmp(POP_LABEL); |
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6668 |
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6669 // Setup the registers to start vector comparison loop |
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6670 bind(COMPARE_WIDE_VECTORS); |
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6671 lea(str1, Address(str1, result, scale)); |
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6672 lea(str2, Address(str2, result, scale)); |
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6673 subl(result, stride2); |
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6674 subl(cnt2, stride2); |
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6675 jccb(Assembler::zero, COMPARE_WIDE_TAIL); |
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6676 negptr(result); |
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6677 |
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6678 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) |
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6679 bind(COMPARE_WIDE_VECTORS_LOOP); |
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6680 vmovdqu(vec1, Address(str1, result, scale)); |
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6681 vpxor(vec1, Address(str2, result, scale)); |
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6682 vptest(vec1, vec1); |
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6683 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); |
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6684 addptr(result, stride2); |
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6685 subl(cnt2, stride2); |
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6686 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); |
8873
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6687 // clean upper bits of YMM registers |
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6688 vzeroupper(); |
7477
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6689 |
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6690 // compare wide vectors tail |
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6691 bind(COMPARE_WIDE_TAIL); |
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6692 testptr(result, result); |
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6693 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
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6694 |
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6695 movl(result, stride2); |
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6696 movl(cnt2, result); |
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6697 negptr(result); |
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6698 jmpb(COMPARE_WIDE_VECTORS_LOOP); |
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6699 |
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6700 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. |
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6701 bind(VECTOR_NOT_EQUAL); |
8873
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6702 // clean upper bits of YMM registers |
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6703 vzeroupper(); |
7477
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6704 lea(str1, Address(str1, result, scale)); |
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6705 lea(str2, Address(str2, result, scale)); |
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6706 jmp(COMPARE_16_CHARS); |
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6707 |
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6708 // Compare tail chars, length between 1 to 15 chars |
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6709 bind(COMPARE_TAIL_LONG); |
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|
6710 movl(cnt2, result); |
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|
6711 cmpl(cnt2, stride); |
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|
6712 jccb(Assembler::less, COMPARE_SMALL_STR); |
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|
6713 |
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6714 movdqu(vec1, Address(str1, 0)); |
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6715 pcmpestri(vec1, Address(str2, 0), pcmpmask); |
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6716 jcc(Assembler::below, COMPARE_INDEX_CHAR); |
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6717 subptr(cnt2, stride); |
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6718 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
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6719 lea(str1, Address(str1, result, scale)); |
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6720 lea(str2, Address(str2, result, scale)); |
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|
6721 negptr(cnt2); |
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|
6722 jmpb(WHILE_HEAD_LABEL); |
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|
6723 |
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|
6724 bind(COMPARE_SMALL_STR); |
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|
6725 } else if (UseSSE42Intrinsics) { |
7199 | 6726 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
6727 int pcmpmask = 0x19; | |
7477
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|
6728 // Setup to compare 8-char (16-byte) vectors, |
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6729 // start from first character again because it has aligned address. |
7199 | 6730 movl(result, cnt2); |
6731 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
6732 jccb(Assembler::zero, COMPARE_TAIL); | |
6733 | |
6734 lea(str1, Address(str1, result, scale)); | |
6735 lea(str2, Address(str2, result, scale)); | |
6736 negptr(result); | |
6737 | |
6738 // pcmpestri | |
6739 // inputs: | |
6740 // vec1- substring | |
6741 // rax - negative string length (elements count) | |
6742 // mem - scaned string | |
6743 // rdx - string length (elements count) | |
6744 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
6745 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
6746 // outputs: | |
6747 // rcx - first mismatched element index | |
6748 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
6749 | |
6750 bind(COMPARE_WIDE_VECTORS); | |
6751 movdqu(vec1, Address(str1, result, scale)); | |
6752 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
6753 // After pcmpestri cnt1(rcx) contains mismatched element index | |
6754 | |
6755 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
6756 addptr(result, stride); | |
6757 subptr(cnt2, stride); | |
6758 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
6759 | |
6760 // compare wide vectors tail | |
7477
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|
6761 testptr(result, result); |
7199 | 6762 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
6763 | |
6764 movl(cnt2, stride); | |
6765 movl(result, stride); | |
6766 negptr(result); | |
6767 movdqu(vec1, Address(str1, result, scale)); | |
6768 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
6769 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
6770 | |
6771 // Mismatched characters in the vectors | |
6772 bind(VECTOR_NOT_EQUAL); | |
7477
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|
6773 addptr(cnt1, result); |
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|
6774 load_unsigned_short(result, Address(str1, cnt1, scale)); |
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|
6775 load_unsigned_short(cnt2, Address(str2, cnt1, scale)); |
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|
6776 subl(result, cnt2); |
7199 | 6777 jmpb(POP_LABEL); |
6778 | |
6779 bind(COMPARE_TAIL); // limit is zero | |
6780 movl(cnt2, result); | |
6781 // Fallthru to tail compare | |
6782 } | |
6783 // Shift str2 and str1 to the end of the arrays, negate min | |
7477
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6784 lea(str1, Address(str1, cnt2, scale)); |
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6785 lea(str2, Address(str2, cnt2, scale)); |
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|
6786 decrementl(cnt2); // first character was compared already |
7199 | 6787 negptr(cnt2); |
6788 | |
6789 // Compare the rest of the elements | |
6790 bind(WHILE_HEAD_LABEL); | |
6791 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); | |
6792 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
6793 subl(result, cnt1); | |
6794 jccb(Assembler::notZero, POP_LABEL); | |
6795 increment(cnt2); | |
6796 jccb(Assembler::notZero, WHILE_HEAD_LABEL); | |
6797 | |
6798 // Strings are equal up to min length. Return the length difference. | |
6799 bind(LENGTH_DIFF_LABEL); | |
6800 pop(result); | |
6801 jmpb(DONE_LABEL); | |
6802 | |
6803 // Discard the stored length difference | |
6804 bind(POP_LABEL); | |
6805 pop(cnt1); | |
6806 | |
6807 // That's it | |
6808 bind(DONE_LABEL); | |
6809 } | |
6810 | |
6811 // Compare char[] arrays aligned to 4 bytes or substrings. | |
6812 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, | |
6813 Register limit, Register result, Register chr, | |
6814 XMMRegister vec1, XMMRegister vec2) { | |
6815 ShortBranchVerifier sbv(this); | |
6816 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; | |
6817 | |
6818 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
6819 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
6820 | |
6821 // Check the input args | |
6822 cmpptr(ary1, ary2); | |
6823 jcc(Assembler::equal, TRUE_LABEL); | |
6824 | |
6825 if (is_array_equ) { | |
6826 // Need additional checks for arrays_equals. | |
6827 testptr(ary1, ary1); | |
6828 jcc(Assembler::zero, FALSE_LABEL); | |
6829 testptr(ary2, ary2); | |
6830 jcc(Assembler::zero, FALSE_LABEL); | |
6831 | |
6832 // Check the lengths | |
6833 movl(limit, Address(ary1, length_offset)); | |
6834 cmpl(limit, Address(ary2, length_offset)); | |
6835 jcc(Assembler::notEqual, FALSE_LABEL); | |
6836 } | |
6837 | |
6838 // count == 0 | |
6839 testl(limit, limit); | |
6840 jcc(Assembler::zero, TRUE_LABEL); | |
6841 | |
6842 if (is_array_equ) { | |
6843 // Load array address | |
6844 lea(ary1, Address(ary1, base_offset)); | |
6845 lea(ary2, Address(ary2, base_offset)); | |
6846 } | |
6847 | |
6848 shll(limit, 1); // byte count != 0 | |
6849 movl(result, limit); // copy | |
6850 | |
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6851 if (UseAVX >= 2) { |
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6852 // With AVX2, use 32-byte vector compare |
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6853 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
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|
6854 |
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6855 // Compare 32-byte vectors |
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6856 andl(result, 0x0000001e); // tail count (in bytes) |
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6857 andl(limit, 0xffffffe0); // vector count (in bytes) |
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6858 jccb(Assembler::zero, COMPARE_TAIL); |
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6859 |
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6860 lea(ary1, Address(ary1, limit, Address::times_1)); |
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6861 lea(ary2, Address(ary2, limit, Address::times_1)); |
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6862 negptr(limit); |
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|
6863 |
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6864 bind(COMPARE_WIDE_VECTORS); |
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6865 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); |
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6866 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); |
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6867 vpxor(vec1, vec2); |
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|
6868 |
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6869 vptest(vec1, vec1); |
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6870 jccb(Assembler::notZero, FALSE_LABEL); |
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6871 addptr(limit, 32); |
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6872 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
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6873 |
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|
6874 testl(result, result); |
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6875 jccb(Assembler::zero, TRUE_LABEL); |
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6876 |
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6877 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); |
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6878 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); |
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6879 vpxor(vec1, vec2); |
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|
6880 |
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6881 vptest(vec1, vec1); |
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6882 jccb(Assembler::notZero, FALSE_LABEL); |
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6883 jmpb(TRUE_LABEL); |
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|
6884 |
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6885 bind(COMPARE_TAIL); // limit is zero |
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6886 movl(limit, result); |
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6887 // Fallthru to tail compare |
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6888 } else if (UseSSE42Intrinsics) { |
7199 | 6889 // With SSE4.2, use double quad vector compare |
6890 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; | |
6891 | |
6892 // Compare 16-byte vectors | |
6893 andl(result, 0x0000000e); // tail count (in bytes) | |
6894 andl(limit, 0xfffffff0); // vector count (in bytes) | |
6895 jccb(Assembler::zero, COMPARE_TAIL); | |
6896 | |
6897 lea(ary1, Address(ary1, limit, Address::times_1)); | |
6898 lea(ary2, Address(ary2, limit, Address::times_1)); | |
6899 negptr(limit); | |
6900 | |
6901 bind(COMPARE_WIDE_VECTORS); | |
6902 movdqu(vec1, Address(ary1, limit, Address::times_1)); | |
6903 movdqu(vec2, Address(ary2, limit, Address::times_1)); | |
6904 pxor(vec1, vec2); | |
6905 | |
6906 ptest(vec1, vec1); | |
6907 jccb(Assembler::notZero, FALSE_LABEL); | |
6908 addptr(limit, 16); | |
6909 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
6910 | |
6911 testl(result, result); | |
6912 jccb(Assembler::zero, TRUE_LABEL); | |
6913 | |
6914 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
6915 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
6916 pxor(vec1, vec2); | |
6917 | |
6918 ptest(vec1, vec1); | |
6919 jccb(Assembler::notZero, FALSE_LABEL); | |
6920 jmpb(TRUE_LABEL); | |
6921 | |
6922 bind(COMPARE_TAIL); // limit is zero | |
6923 movl(limit, result); | |
6924 // Fallthru to tail compare | |
6925 } | |
6926 | |
6927 // Compare 4-byte vectors | |
6928 andl(limit, 0xfffffffc); // vector count (in bytes) | |
6929 jccb(Assembler::zero, COMPARE_CHAR); | |
6930 | |
6931 lea(ary1, Address(ary1, limit, Address::times_1)); | |
6932 lea(ary2, Address(ary2, limit, Address::times_1)); | |
6933 negptr(limit); | |
6934 | |
6935 bind(COMPARE_VECTORS); | |
6936 movl(chr, Address(ary1, limit, Address::times_1)); | |
6937 cmpl(chr, Address(ary2, limit, Address::times_1)); | |
6938 jccb(Assembler::notEqual, FALSE_LABEL); | |
6939 addptr(limit, 4); | |
6940 jcc(Assembler::notZero, COMPARE_VECTORS); | |
6941 | |
6942 // Compare trailing char (final 2 bytes), if any | |
6943 bind(COMPARE_CHAR); | |
6944 testl(result, 0x2); // tail char | |
6945 jccb(Assembler::zero, TRUE_LABEL); | |
6946 load_unsigned_short(chr, Address(ary1, 0)); | |
6947 load_unsigned_short(limit, Address(ary2, 0)); | |
6948 cmpl(chr, limit); | |
6949 jccb(Assembler::notEqual, FALSE_LABEL); | |
6950 | |
6951 bind(TRUE_LABEL); | |
6952 movl(result, 1); // return true | |
6953 jmpb(DONE); | |
6954 | |
6955 bind(FALSE_LABEL); | |
6956 xorl(result, result); // return false | |
6957 | |
6958 // That's it | |
6959 bind(DONE); | |
8873
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6960 if (UseAVX >= 2) { |
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6961 // clean upper bits of YMM registers |
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|
6962 vzeroupper(); |
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6963 } |
7199 | 6964 } |
6965 | |
6966 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
6967 Register to, Register value, Register count, | |
6968 Register rtmp, XMMRegister xtmp) { | |
6969 ShortBranchVerifier sbv(this); | |
6970 assert_different_registers(to, value, count, rtmp); | |
6971 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
6972 Label L_fill_2_bytes, L_fill_4_bytes; | |
6973 | |
6974 int shift = -1; | |
6975 switch (t) { | |
6976 case T_BYTE: | |
6977 shift = 2; | |
6978 break; | |
6979 case T_SHORT: | |
6980 shift = 1; | |
6981 break; | |
6982 case T_INT: | |
6983 shift = 0; | |
6984 break; | |
6985 default: ShouldNotReachHere(); | |
6986 } | |
6987 | |
6988 if (t == T_BYTE) { | |
6989 andl(value, 0xff); | |
6990 movl(rtmp, value); | |
6991 shll(rtmp, 8); | |
6992 orl(value, rtmp); | |
6993 } | |
6994 if (t == T_SHORT) { | |
6995 andl(value, 0xffff); | |
6996 } | |
6997 if (t == T_BYTE || t == T_SHORT) { | |
6998 movl(rtmp, value); | |
6999 shll(rtmp, 16); | |
7000 orl(value, rtmp); | |
7001 } | |
7002 | |
7003 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
7004 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
7005 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
7006 // align source address at 4 bytes address boundary | |
7007 if (t == T_BYTE) { | |
7008 // One byte misalignment happens only for byte arrays | |
7009 testptr(to, 1); | |
7010 jccb(Assembler::zero, L_skip_align1); | |
7011 movb(Address(to, 0), value); | |
7012 increment(to); | |
7013 decrement(count); | |
7014 BIND(L_skip_align1); | |
7015 } | |
7016 // Two bytes misalignment happens only for byte and short (char) arrays | |
7017 testptr(to, 2); | |
7018 jccb(Assembler::zero, L_skip_align2); | |
7019 movw(Address(to, 0), value); | |
7020 addptr(to, 2); | |
7021 subl(count, 1<<(shift-1)); | |
7022 BIND(L_skip_align2); | |
7023 } | |
7024 if (UseSSE < 2) { | |
7025 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
7026 // Fill 32-byte chunks | |
7027 subl(count, 8 << shift); | |
7028 jcc(Assembler::less, L_check_fill_8_bytes); | |
7029 align(16); | |
7030 | |
7031 BIND(L_fill_32_bytes_loop); | |
7032 | |
7033 for (int i = 0; i < 32; i += 4) { | |
7034 movl(Address(to, i), value); | |
7035 } | |
7036 | |
7037 addptr(to, 32); | |
7038 subl(count, 8 << shift); | |
7039 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
7040 BIND(L_check_fill_8_bytes); | |
7041 addl(count, 8 << shift); | |
7042 jccb(Assembler::zero, L_exit); | |
7043 jmpb(L_fill_8_bytes); | |
7044 | |
7045 // | |
7046 // length is too short, just fill qwords | |
7047 // | |
7048 BIND(L_fill_8_bytes_loop); | |
7049 movl(Address(to, 0), value); | |
7050 movl(Address(to, 4), value); | |
7051 addptr(to, 8); | |
7052 BIND(L_fill_8_bytes); | |
7053 subl(count, 1 << (shift + 1)); | |
7054 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
7055 // fall through to fill 4 bytes | |
7056 } else { | |
7057 Label L_fill_32_bytes; | |
7058 if (!UseUnalignedLoadStores) { | |
7059 // align to 8 bytes, we know we are 4 byte aligned to start | |
7060 testptr(to, 4); | |
7061 jccb(Assembler::zero, L_fill_32_bytes); | |
7062 movl(Address(to, 0), value); | |
7063 addptr(to, 4); | |
7064 subl(count, 1<<shift); | |
7065 } | |
7066 BIND(L_fill_32_bytes); | |
7067 { | |
7068 assert( UseSSE >= 2, "supported cpu only" ); | |
7069 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
7070 movdl(xtmp, value); | |
7475
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7071 if (UseAVX >= 2 && UseUnalignedLoadStores) { |
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7072 // Fill 64-byte chunks |
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7073 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; |
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7074 vpbroadcastd(xtmp, xtmp); |
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7075 |
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7076 subl(count, 16 << shift); |
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7077 jcc(Assembler::less, L_check_fill_32_bytes); |
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7078 align(16); |
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|
7079 |
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7080 BIND(L_fill_64_bytes_loop); |
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7081 vmovdqu(Address(to, 0), xtmp); |
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7082 vmovdqu(Address(to, 32), xtmp); |
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7083 addptr(to, 64); |
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7084 subl(count, 16 << shift); |
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7085 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); |
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7086 |
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7087 BIND(L_check_fill_32_bytes); |
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7088 addl(count, 8 << shift); |
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7089 jccb(Assembler::less, L_check_fill_8_bytes); |
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7090 vmovdqu(Address(to, 0), xtmp); |
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7091 addptr(to, 32); |
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|
7092 subl(count, 8 << shift); |
8873
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7093 |
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|
7094 BIND(L_check_fill_8_bytes); |
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7095 // clean upper bits of YMM registers |
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|
7096 vzeroupper(); |
7199 | 7097 } else { |
7475
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7098 // Fill 32-byte chunks |
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|
7099 pshufd(xtmp, xtmp, 0); |
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7100 |
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7101 subl(count, 8 << shift); |
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7102 jcc(Assembler::less, L_check_fill_8_bytes); |
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7103 align(16); |
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7104 |
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|
7105 BIND(L_fill_32_bytes_loop); |
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7106 |
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|
7107 if (UseUnalignedLoadStores) { |
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7108 movdqu(Address(to, 0), xtmp); |
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7109 movdqu(Address(to, 16), xtmp); |
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7110 } else { |
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7111 movq(Address(to, 0), xtmp); |
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7112 movq(Address(to, 8), xtmp); |
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7113 movq(Address(to, 16), xtmp); |
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7114 movq(Address(to, 24), xtmp); |
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7115 } |
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|
7116 |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
7117 addptr(to, 32); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
7118 subl(count, 8 << shift); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
7119 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); |
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7120 |
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7121 BIND(L_check_fill_8_bytes); |
7199 | 7122 } |
7123 addl(count, 8 << shift); | |
7124 jccb(Assembler::zero, L_exit); | |
7125 jmpb(L_fill_8_bytes); | |
7126 | |
7127 // | |
7128 // length is too short, just fill qwords | |
7129 // | |
7130 BIND(L_fill_8_bytes_loop); | |
7131 movq(Address(to, 0), xtmp); | |
7132 addptr(to, 8); | |
7133 BIND(L_fill_8_bytes); | |
7134 subl(count, 1 << (shift + 1)); | |
7135 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
7136 } | |
7137 } | |
7138 // fill trailing 4 bytes | |
7139 BIND(L_fill_4_bytes); | |
7140 testl(count, 1<<shift); | |
7141 jccb(Assembler::zero, L_fill_2_bytes); | |
7142 movl(Address(to, 0), value); | |
7143 if (t == T_BYTE || t == T_SHORT) { | |
7144 addptr(to, 4); | |
7145 BIND(L_fill_2_bytes); | |
7146 // fill trailing 2 bytes | |
7147 testl(count, 1<<(shift-1)); | |
7148 jccb(Assembler::zero, L_fill_byte); | |
7149 movw(Address(to, 0), value); | |
7150 if (t == T_BYTE) { | |
7151 addptr(to, 2); | |
7152 BIND(L_fill_byte); | |
7153 // fill trailing byte | |
7154 testl(count, 1); | |
7155 jccb(Assembler::zero, L_exit); | |
7156 movb(Address(to, 0), value); | |
7157 } else { | |
7158 BIND(L_fill_byte); | |
7159 } | |
7160 } else { | |
7161 BIND(L_fill_2_bytes); | |
7162 } | |
7163 BIND(L_exit); | |
7164 } | |
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7165 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7166 // encode char[] to byte[] in ISO_8859_1 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7167 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7168 XMMRegister tmp1Reg, XMMRegister tmp2Reg, |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7169 XMMRegister tmp3Reg, XMMRegister tmp4Reg, |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7170 Register tmp5, Register result) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7171 // rsi: src |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7172 // rdi: dst |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7173 // rdx: len |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7174 // rcx: tmp5 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7175 // rax: result |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7176 ShortBranchVerifier sbv(this); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7177 assert_different_registers(src, dst, len, tmp5, result); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7178 Label L_done, L_copy_1_char, L_copy_1_char_exit; |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7179 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7180 // set result |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7181 xorl(result, result); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7182 // check for zero length |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7183 testl(len, len); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7184 jcc(Assembler::zero, L_done); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7185 movl(result, len); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7186 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7187 // Setup pointers |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7188 lea(src, Address(src, len, Address::times_2)); // char[] |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7189 lea(dst, Address(dst, len, Address::times_1)); // byte[] |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7190 negptr(len); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7191 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7192 if (UseSSE42Intrinsics || UseAVX >= 2) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7193 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7194 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7195 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7196 if (UseAVX >= 2) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7197 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7198 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7199 movdl(tmp1Reg, tmp5); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7200 vpbroadcastd(tmp1Reg, tmp1Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7201 jmpb(L_chars_32_check); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7202 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7203 bind(L_copy_32_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7204 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7205 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7206 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7207 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7208 jccb(Assembler::notZero, L_copy_32_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7209 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7210 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7211 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7212 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7213 bind(L_chars_32_check); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7214 addptr(len, 32); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7215 jccb(Assembler::lessEqual, L_copy_32_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7216 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7217 bind(L_copy_32_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7218 subptr(len, 16); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7219 jccb(Assembler::greater, L_copy_16_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7220 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7221 } else if (UseSSE42Intrinsics) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7222 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7223 movdl(tmp1Reg, tmp5); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7224 pshufd(tmp1Reg, tmp1Reg, 0); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7225 jmpb(L_chars_16_check); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7226 } |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7227 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7228 bind(L_copy_16_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7229 if (UseAVX >= 2) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7230 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7231 vptest(tmp2Reg, tmp1Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7232 jccb(Assembler::notZero, L_copy_16_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7233 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7234 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7235 } else { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7236 if (UseAVX > 0) { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7237 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7238 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7239 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7240 } else { |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7241 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7242 por(tmp2Reg, tmp3Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7243 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7244 por(tmp2Reg, tmp4Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7245 } |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7246 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7247 jccb(Assembler::notZero, L_copy_16_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7248 packuswb(tmp3Reg, tmp4Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7249 } |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7250 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7251 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7252 bind(L_chars_16_check); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7253 addptr(len, 16); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7254 jccb(Assembler::lessEqual, L_copy_16_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7255 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7256 bind(L_copy_16_chars_exit); |
8873
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7257 if (UseAVX >= 2) { |
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7258 // clean upper bits of YMM registers |
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7259 vzeroupper(); |
e961c11b85fe
8011102: Clear AVX registers after return from JNI call
kvn
parents:
8767
diff
changeset
|
7260 } |
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7261 subptr(len, 8); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7262 jccb(Assembler::greater, L_copy_8_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7263 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7264 bind(L_copy_8_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7265 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7266 ptest(tmp3Reg, tmp1Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7267 jccb(Assembler::notZero, L_copy_8_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7268 packuswb(tmp3Reg, tmp1Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7269 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7270 addptr(len, 8); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7271 jccb(Assembler::lessEqual, L_copy_8_chars); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7272 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7273 bind(L_copy_8_chars_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7274 subptr(len, 8); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7275 jccb(Assembler::zero, L_done); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7276 } |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7277 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7278 bind(L_copy_1_char); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7279 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7280 testl(tmp5, 0xff00); // check if Unicode char |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7281 jccb(Assembler::notZero, L_copy_1_char_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7282 movb(Address(dst, len, Address::times_1, 0), tmp5); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7283 addptr(len, 1); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7284 jccb(Assembler::less, L_copy_1_char); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7285 |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7286 bind(L_copy_1_char_exit); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7287 addptr(result, len); // len is negative count of not processed elements |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7288 bind(L_done); |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7289 } |
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7477
diff
changeset
|
7290 |
11080
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7291 /** |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7292 * Emits code to update CRC-32 with a byte value according to constants in table |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7293 * |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7294 * @param [in,out]crc Register containing the crc. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7295 * @param [in]val Register containing the byte to fold into the CRC. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7296 * @param [in]table Register containing the table of crc constants. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7297 * |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7298 * uint32_t crc; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7299 * val = crc_table[(val ^ crc) & 0xFF]; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7300 * crc = val ^ (crc >> 8); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7301 * |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7302 */ |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7303 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7304 xorl(val, crc); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7305 andl(val, 0xFF); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7306 shrl(crc, 8); // unsigned shift |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7307 xorl(crc, Address(table, val, Address::times_4, 0)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7308 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7309 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7310 /** |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7311 * Fold 128-bit data chunk |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7312 */ |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7313 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7314 vpclmulhdq(xtmp, xK, xcrc); // [123:64] |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7315 vpclmulldq(xcrc, xK, xcrc); // [63:0] |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7316 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7317 pxor(xcrc, xtmp); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7318 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7319 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7320 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7321 vpclmulhdq(xtmp, xK, xcrc); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7322 vpclmulldq(xcrc, xK, xcrc); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7323 pxor(xcrc, xbuf); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7324 pxor(xcrc, xtmp); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7325 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7326 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7327 /** |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7328 * 8-bit folds to compute 32-bit CRC |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7329 * |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7330 * uint64_t xcrc; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7331 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7332 */ |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7333 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7334 movdl(tmp, xcrc); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7335 andl(tmp, 0xFF); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7336 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7337 psrldq(xcrc, 1); // unsigned shift one byte |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7338 pxor(xcrc, xtmp); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7339 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7340 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7341 /** |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7342 * uint32_t crc; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7343 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7344 */ |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7345 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7346 movl(tmp, crc); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7347 andl(tmp, 0xFF); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7348 shrl(crc, 8); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7349 xorl(crc, Address(table, tmp, Address::times_4, 0)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7350 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7351 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7352 /** |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7353 * @param crc register containing existing CRC (32-bit) |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7354 * @param buf register pointing to input byte buffer (byte*) |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7355 * @param len register containing number of bytes |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7356 * @param table register that will contain address of CRC table |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7357 * @param tmp scratch register |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7358 */ |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7359 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7360 assert_different_registers(crc, buf, len, table, tmp, rax); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7361 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7362 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7363 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7364 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7365 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7366 notl(crc); // ~crc |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7367 cmpl(len, 16); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7368 jcc(Assembler::less, L_tail); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7369 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7370 // Align buffer to 16 bytes |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7371 movl(tmp, buf); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7372 andl(tmp, 0xF); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7373 jccb(Assembler::zero, L_aligned); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7374 subl(tmp, 16); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7375 addl(len, tmp); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7376 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7377 align(4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7378 BIND(L_align_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7379 movsbl(rax, Address(buf, 0)); // load byte with sign extension |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7380 update_byte_crc32(crc, rax, table); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7381 increment(buf); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7382 incrementl(tmp); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7383 jccb(Assembler::less, L_align_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7384 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7385 BIND(L_aligned); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7386 movl(tmp, len); // save |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7387 shrl(len, 4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7388 jcc(Assembler::zero, L_tail_restore); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7389 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7390 // Fold crc into first bytes of vector |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7391 movdqa(xmm1, Address(buf, 0)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7392 movdl(rax, xmm1); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7393 xorl(crc, rax); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7394 pinsrd(xmm1, crc, 0); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7395 addptr(buf, 16); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7396 subl(len, 4); // len > 0 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7397 jcc(Assembler::less, L_fold_tail); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7398 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7399 movdqa(xmm2, Address(buf, 0)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7400 movdqa(xmm3, Address(buf, 16)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7401 movdqa(xmm4, Address(buf, 32)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7402 addptr(buf, 48); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7403 subl(len, 3); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7404 jcc(Assembler::lessEqual, L_fold_512b); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7405 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7406 // Fold total 512 bits of polynomial on each iteration, |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7407 // 128 bits per each of 4 parallel streams. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7408 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7409 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7410 align(32); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7411 BIND(L_fold_512b_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7412 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7413 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7414 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7415 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7416 addptr(buf, 64); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7417 subl(len, 4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7418 jcc(Assembler::greater, L_fold_512b_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7419 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7420 // Fold 512 bits to 128 bits. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7421 BIND(L_fold_512b); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7422 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7423 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7424 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7425 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7426 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7427 // Fold the rest of 128 bits data chunks |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7428 BIND(L_fold_tail); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7429 addl(len, 3); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7430 jccb(Assembler::lessEqual, L_fold_128b); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7431 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7432 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7433 BIND(L_fold_tail_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7434 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7435 addptr(buf, 16); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7436 decrementl(len); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7437 jccb(Assembler::greater, L_fold_tail_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7438 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7439 // Fold 128 bits in xmm1 down into 32 bits in crc register. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7440 BIND(L_fold_128b); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7441 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7442 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7443 vpand(xmm3, xmm0, xmm2, false /* vector256 */); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7444 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7445 psrldq(xmm1, 8); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7446 psrldq(xmm2, 4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7447 pxor(xmm0, xmm1); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7448 pxor(xmm0, xmm2); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7449 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7450 // 8 8-bit folds to compute 32-bit CRC. |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7451 for (int j = 0; j < 4; j++) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7452 fold_8bit_crc32(xmm0, table, xmm1, rax); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7453 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7454 movdl(crc, xmm0); // mov 32 bits to general register |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7455 for (int j = 0; j < 4; j++) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7456 fold_8bit_crc32(crc, table, rax); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7457 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7458 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7459 BIND(L_tail_restore); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7460 movl(len, tmp); // restore |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7461 BIND(L_tail); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7462 andl(len, 0xf); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7463 jccb(Assembler::zero, L_exit); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7464 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7465 // Fold the rest of bytes |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7466 align(4); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7467 BIND(L_tail_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7468 movsbl(rax, Address(buf, 0)); // load byte with sign extension |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7469 update_byte_crc32(crc, rax, table); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7470 increment(buf); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7471 decrementl(len); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7472 jccb(Assembler::greater, L_tail_loop); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7473 |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7474 BIND(L_exit); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7475 notl(crc); // ~c |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7476 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
8873
diff
changeset
|
7477 |
7199 | 7478 #undef BIND |
7479 #undef BLOCK_COMMENT | |
7480 | |
7481 | |
7482 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
7483 switch (cond) { | |
7484 // Note some conditions are synonyms for others | |
7485 case Assembler::zero: return Assembler::notZero; | |
7486 case Assembler::notZero: return Assembler::zero; | |
7487 case Assembler::less: return Assembler::greaterEqual; | |
7488 case Assembler::lessEqual: return Assembler::greater; | |
7489 case Assembler::greater: return Assembler::lessEqual; | |
7490 case Assembler::greaterEqual: return Assembler::less; | |
7491 case Assembler::below: return Assembler::aboveEqual; | |
7492 case Assembler::belowEqual: return Assembler::above; | |
7493 case Assembler::above: return Assembler::belowEqual; | |
7494 case Assembler::aboveEqual: return Assembler::below; | |
7495 case Assembler::overflow: return Assembler::noOverflow; | |
7496 case Assembler::noOverflow: return Assembler::overflow; | |
7497 case Assembler::negative: return Assembler::positive; | |
7498 case Assembler::positive: return Assembler::negative; | |
7499 case Assembler::parity: return Assembler::noParity; | |
7500 case Assembler::noParity: return Assembler::parity; | |
7501 } | |
7502 ShouldNotReachHere(); return Assembler::overflow; | |
7503 } | |
7504 | |
7505 SkipIfEqual::SkipIfEqual( | |
7506 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
7507 _masm = masm; | |
7508 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
7509 _masm->jcc(Assembler::equal, _label); | |
7510 } | |
7511 | |
7512 SkipIfEqual::~SkipIfEqual() { | |
7513 _masm->bind(_label); | |
7514 } |