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7204
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
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26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
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27
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28 #include "asm/assembler.hpp"
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29
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30 // <sys/trap.h> promises that the system will not use traps 16-31
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31 #define ST_RESERVED_FOR_USER_0 0x10
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32
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33 class BiasedLockingCounters;
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34
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35
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36 // Register aliases for parts of the system:
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37
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38 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
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39 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
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40 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
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41
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42 // g2-g4 are scratch registers called "application globals". Their
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43 // meaning is reserved to the "compilation system"--which means us!
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44 // They are are not supposed to be touched by ordinary C code, although
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45 // highly-optimized C code might steal them for temps. They are safe
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46 // across thread switches, and the ABI requires that they be safe
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47 // across function calls.
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48 //
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49 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
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50 // across func calls, and V8+ also allows g5 to be clobbered across
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51 // func calls. Also, g1 and g5 can get touched while doing shared
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52 // library loading.
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53 //
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54 // We must not touch g7 (it is the thread-self register) and g6 is
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55 // reserved for certain tools. g0, of course, is always zero.
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56 //
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57 // (Sources: SunSoft Compilers Group, thread library engineers.)
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58
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59 // %%%% The interpreter should be revisited to reduce global scratch regs.
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60
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61 // This global always holds the current JavaThread pointer:
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62
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63 REGISTER_DECLARATION(Register, G2_thread , G2);
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64 REGISTER_DECLARATION(Register, G6_heapbase , G6);
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65
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66 // The following globals are part of the Java calling convention:
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67
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68 REGISTER_DECLARATION(Register, G5_method , G5);
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69 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
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70 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
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71
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72 // The following globals are used for the new C1 & interpreter calling convention:
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73 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
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74
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75 // This local is used to preserve G2_thread in the interpreter and in stubs:
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76 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
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77
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78 // These globals are used as scratch registers in the interpreter:
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79
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80 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
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81 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
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82 REGISTER_DECLARATION(Register, G3_scratch , G3);
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83 REGISTER_DECLARATION(Register, G4_scratch , G4);
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84
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85 // These globals are used as short-lived scratch registers in the compiler:
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86
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87 REGISTER_DECLARATION(Register, Gtemp , G5);
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88
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89 // JSR 292 fixed register usages:
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90 REGISTER_DECLARATION(Register, G5_method_type , G5);
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91 REGISTER_DECLARATION(Register, G3_method_handle , G3);
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92 REGISTER_DECLARATION(Register, L7_mh_SP_save , L7);
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93
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94 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
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95 // because a single patchable "set" instruction (NativeMovConstReg,
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96 // or NativeMovConstPatching for compiler1) instruction
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97 // serves to set up either quantity, depending on whether the compiled
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98 // call site is an inline cache or is megamorphic. See the function
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99 // CompiledIC::set_to_megamorphic.
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100 //
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101 // If a inline cache targets an interpreted method, then the
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102 // G5 register will be used twice during the call. First,
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103 // the call site will be patched to load a compiledICHolder
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104 // into G5. (This is an ordered pair of ic_klass, method.)
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105 // The c2i adapter will first check the ic_klass, then load
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106 // G5_method with the method part of the pair just before
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107 // jumping into the interpreter.
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108 //
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109 // Note that G5_method is only the method-self for the interpreter,
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110 // and is logically unrelated to G5_megamorphic_method.
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111 //
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112 // Invariants on G2_thread (the JavaThread pointer):
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113 // - it should not be used for any other purpose anywhere
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114 // - it must be re-initialized by StubRoutines::call_stub()
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115 // - it must be preserved around every use of call_VM
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116
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117 // We can consider using g2/g3/g4 to cache more values than the
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118 // JavaThread, such as the card-marking base or perhaps pointers into
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119 // Eden. It's something of a waste to use them as scratch temporaries,
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120 // since they are not supposed to be volatile. (Of course, if we find
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121 // that Java doesn't benefit from application globals, then we can just
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122 // use them as ordinary temporaries.)
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123 //
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124 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
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125 // it makes sense to use them routinely for procedure linkage,
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126 // whenever the On registers are not applicable. Examples: G5_method,
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127 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
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128 // stubs. This means that compiler stubs, etc., should be kept to a
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129 // maximum of two or three G-register arguments.
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130
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131
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132 // stub frames
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133
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134 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
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135
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136 // Interpreter frames
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137
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138 #ifdef CC_INTERP
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139 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
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140 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
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141 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
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142 REGISTER_DECLARATION(Register, L2_scratch , L2);
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143 REGISTER_DECLARATION(Register, L3_scratch , L3);
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144 REGISTER_DECLARATION(Register, L4_scratch , L4);
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145 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
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146 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
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147 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
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148 REGISTER_DECLARATION(Register, O5_savedSP , O5);
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149 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
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150 // a copy SP, so in 64-bit it's a biased value. The bias
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151 // is added and removed as needed in the frame code.
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152 // Interface to signature handler
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153 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
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154 REGISTER_DECLARATION(Register, Lmethod , L6); // Method* when calling signature handler
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155
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156 #else
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157 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
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158 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
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159 REGISTER_DECLARATION(Register, Lmethod , L2);
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160 REGISTER_DECLARATION(Register, Llocals , L3);
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161 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
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162 // must match Llocals in asm interpreter
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163 REGISTER_DECLARATION(Register, Lmonitors , L4);
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164 REGISTER_DECLARATION(Register, Lbyte_code , L5);
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165 // When calling out from the interpreter we record SP so that we can remove any extra stack
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166 // space allocated during adapter transitions. This register is only live from the point
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167 // of the call until we return.
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168 REGISTER_DECLARATION(Register, Llast_SP , L5);
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169 REGISTER_DECLARATION(Register, Lscratch , L5);
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170 REGISTER_DECLARATION(Register, Lscratch2 , L6);
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171 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
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172
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173 REGISTER_DECLARATION(Register, O5_savedSP , O5);
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174 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
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175 // a copy SP, so in 64-bit it's a biased value. The bias
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176 // is added and removed as needed in the frame code.
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177 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
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178 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
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179 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
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180 #endif /* CC_INTERP */
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181
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182 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
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183 // the interpreter code. If Lscratch2 needs to be used for some
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184 // purpose than LcpoolCache should be restore after that for
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185 // the interpreter to work right
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186 // (These assignments must be compatible with L7_thread_cache; see above.)
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187
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188 // Since Lbcp points into the middle of the method object,
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189 // it is temporarily converted into a "bcx" during GC.
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190
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191 // Exception processing
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192 // These registers are passed into exception handlers.
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193 // All exception handlers require the exception object being thrown.
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194 // In addition, an nmethod's exception handler must be passed
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195 // the address of the call site within the nmethod, to allow
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196 // proper selection of the applicable catch block.
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197 // (Interpreter frames use their own bcp() for this purpose.)
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198 //
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199 // The Oissuing_pc value is not always needed. When jumping to a
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200 // handler that is known to be interpreted, the Oissuing_pc value can be
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201 // omitted. An actual catch block in compiled code receives (from its
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202 // nmethod's exception handler) the thrown exception in the Oexception,
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203 // but it doesn't need the Oissuing_pc.
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204 //
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205 // If an exception handler (either interpreted or compiled)
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206 // discovers there is no applicable catch block, it updates
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207 // the Oissuing_pc to the continuation PC of its own caller,
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208 // pops back to that caller's stack frame, and executes that
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209 // caller's exception handler. Obviously, this process will
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210 // iterate until the control stack is popped back to a method
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211 // containing an applicable catch block. A key invariant is
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212 // that the Oissuing_pc value is always a value local to
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213 // the method whose exception handler is currently executing.
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214 //
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215 // Note: The issuing PC value is __not__ a raw return address (I7 value).
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216 // It is a "return pc", the address __following__ the call.
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217 // Raw return addresses are converted to issuing PCs by frame::pc(),
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218 // or by stubs. Issuing PCs can be used directly with PC range tables.
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219 //
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220 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
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221 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
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222
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223
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224 // These must occur after the declarations above
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225 #ifndef DONT_USE_REGISTER_DEFINES
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226
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227 #define Gthread AS_REGISTER(Register, Gthread)
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228 #define Gmethod AS_REGISTER(Register, Gmethod)
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229 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
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230 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
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231 #define Gargs AS_REGISTER(Register, Gargs)
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232 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
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233 #define Gframe_size AS_REGISTER(Register, Gframe_size)
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234 #define Gtemp AS_REGISTER(Register, Gtemp)
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235
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236 #ifdef CC_INTERP
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237 #define Lstate AS_REGISTER(Register, Lstate)
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238 #define Lesp AS_REGISTER(Register, Lesp)
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239 #define L1_scratch AS_REGISTER(Register, L1_scratch)
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240 #define Lmirror AS_REGISTER(Register, Lmirror)
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241 #define L2_scratch AS_REGISTER(Register, L2_scratch)
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242 #define L3_scratch AS_REGISTER(Register, L3_scratch)
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243 #define L4_scratch AS_REGISTER(Register, L4_scratch)
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244 #define Lscratch AS_REGISTER(Register, Lscratch)
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245 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
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246 #define L7_scratch AS_REGISTER(Register, L7_scratch)
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247 #define Ostate AS_REGISTER(Register, Ostate)
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248 #else
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249 #define Lesp AS_REGISTER(Register, Lesp)
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250 #define Lbcp AS_REGISTER(Register, Lbcp)
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251 #define Lmethod AS_REGISTER(Register, Lmethod)
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252 #define Llocals AS_REGISTER(Register, Llocals)
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253 #define Lmonitors AS_REGISTER(Register, Lmonitors)
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254 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
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255 #define Lscratch AS_REGISTER(Register, Lscratch)
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256 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
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257 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
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258 #endif /* ! CC_INTERP */
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259
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260 #define Lentry_args AS_REGISTER(Register, Lentry_args)
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261 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
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262 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
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263 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
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264 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
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265 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
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266
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267 #define Oexception AS_REGISTER(Register, Oexception)
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268 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
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269
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270 #endif
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271
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272
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273 // Address is an abstraction used to represent a memory location.
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274 //
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275 // Note: A register location is represented via a Register, not
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276 // via an address for efficiency & simplicity reasons.
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277
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278 class Address VALUE_OBJ_CLASS_SPEC {
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279 private:
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280 Register _base; // Base register.
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281 RegisterOrConstant _index_or_disp; // Index register or constant displacement.
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282 RelocationHolder _rspec;
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283
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284 public:
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285 Address() : _base(noreg), _index_or_disp(noreg) {}
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286
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287 Address(Register base, RegisterOrConstant index_or_disp)
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288 : _base(base),
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289 _index_or_disp(index_or_disp) {
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290 }
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291
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292 Address(Register base, Register index)
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293 : _base(base),
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294 _index_or_disp(index) {
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295 }
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296
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297 Address(Register base, int disp)
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298 : _base(base),
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299 _index_or_disp(disp) {
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300 }
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301
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302 #ifdef ASSERT
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303 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
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304 Address(Register base, ByteSize disp)
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305 : _base(base),
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306 _index_or_disp(in_bytes(disp)) {
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307 }
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308 #endif
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309
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310 // accessors
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311 Register base() const { return _base; }
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312 Register index() const { return _index_or_disp.as_register(); }
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313 int disp() const { return _index_or_disp.as_constant(); }
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314
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315 bool has_index() const { return _index_or_disp.is_register(); }
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316 bool has_disp() const { return _index_or_disp.is_constant(); }
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317
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318 bool uses(Register reg) const { return base() == reg || (has_index() && index() == reg); }
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319
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320 const relocInfo::relocType rtype() { return _rspec.type(); }
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321 const RelocationHolder& rspec() { return _rspec; }
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322
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323 RelocationHolder rspec(int offset) const {
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324 return offset == 0 ? _rspec : _rspec.plus(offset);
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325 }
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326
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327 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
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328
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329 Address plus_disp(int plusdisp) const { // bump disp by a small amount
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330 assert(_index_or_disp.is_constant(), "must have a displacement");
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331 Address a(base(), disp() + plusdisp);
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332 return a;
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333 }
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334 bool is_same_address(Address a) const {
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335 // disregard _rspec
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336 return base() == a.base() && (has_index() ? index() == a.index() : disp() == a.disp());
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337 }
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338
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339 Address after_save() const {
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340 Address a = (*this);
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341 a._base = a._base->after_save();
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342 return a;
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343 }
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344
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345 Address after_restore() const {
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346 Address a = (*this);
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347 a._base = a._base->after_restore();
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348 return a;
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349 }
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350
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351 // Convert the raw encoding form into the form expected by the
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352 // constructor for Address.
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353 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
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354
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355 friend class Assembler;
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356 };
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357
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358
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359 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
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360 private:
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361 address _address;
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362 RelocationHolder _rspec;
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363
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364 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
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365 switch (rtype) {
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366 case relocInfo::external_word_type:
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367 return external_word_Relocation::spec(addr);
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368 case relocInfo::internal_word_type:
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369 return internal_word_Relocation::spec(addr);
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370 #ifdef _LP64
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|
371 case relocInfo::opt_virtual_call_type:
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372 return opt_virtual_call_Relocation::spec();
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|
373 case relocInfo::static_call_type:
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|
374 return static_call_Relocation::spec();
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375 case relocInfo::runtime_call_type:
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376 return runtime_call_Relocation::spec();
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377 #endif
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378 case relocInfo::none:
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|
379 return RelocationHolder();
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380 default:
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381 ShouldNotReachHere();
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382 return RelocationHolder();
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383 }
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384 }
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385
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386 protected:
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387 // creation
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388 AddressLiteral() : _address(NULL), _rspec(NULL) {}
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389
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390 public:
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391 AddressLiteral(address addr, RelocationHolder const& rspec)
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392 : _address(addr),
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393 _rspec(rspec) {}
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394
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395 // Some constructors to avoid casting at the call site.
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396 AddressLiteral(jobject obj, RelocationHolder const& rspec)
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397 : _address((address) obj),
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398 _rspec(rspec) {}
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399
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400 AddressLiteral(intptr_t value, RelocationHolder const& rspec)
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401 : _address((address) value),
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402 _rspec(rspec) {}
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403
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404 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
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405 : _address((address) addr),
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406 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
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407
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408 // Some constructors to avoid casting at the call site.
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|
409 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
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410 : _address((address) addr),
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411 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
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412
|
|
|
413 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
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414 : _address((address) addr),
|
|
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415 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
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416
|
|
|
417 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
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|
418 : _address((address) addr),
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|
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419 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
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420
|
|
|
421 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
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|
422 : _address((address) addr),
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|
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423 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
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424
|
|
|
425 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
426 : _address((address) addr),
|
|
|
427 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
428
|
|
|
429 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
430 : _address((address) addr),
|
|
|
431 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
432
|
|
|
433 #ifdef _LP64
|
|
|
434 // 32-bit complains about a multiple declaration for int*.
|
|
|
435 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
436 : _address((address) addr),
|
|
|
437 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
438 #endif
|
|
|
439
|
|
|
440 AddressLiteral(Metadata* addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
441 : _address((address) addr),
|
|
|
442 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
443
|
|
|
444 AddressLiteral(Metadata** addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
445 : _address((address) addr),
|
|
|
446 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
447
|
|
|
448 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
449 : _address((address) addr),
|
|
|
450 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
451
|
|
|
452 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
|
|
|
453 : _address((address) addr),
|
|
|
454 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
|
|
|
455
|
|
|
456 intptr_t value() const { return (intptr_t) _address; }
|
|
|
457 int low10() const;
|
|
|
458
|
|
|
459 const relocInfo::relocType rtype() const { return _rspec.type(); }
|
|
|
460 const RelocationHolder& rspec() const { return _rspec; }
|
|
|
461
|
|
|
462 RelocationHolder rspec(int offset) const {
|
|
|
463 return offset == 0 ? _rspec : _rspec.plus(offset);
|
|
|
464 }
|
|
|
465 };
|
|
|
466
|
|
|
467 // Convenience classes
|
|
|
468 class ExternalAddress: public AddressLiteral {
|
|
|
469 private:
|
|
|
470 static relocInfo::relocType reloc_for_target(address target) {
|
|
|
471 // Sometimes ExternalAddress is used for values which aren't
|
|
|
472 // exactly addresses, like the card table base.
|
|
|
473 // external_word_type can't be used for values in the first page
|
|
|
474 // so just skip the reloc in that case.
|
|
|
475 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
|
|
|
476 }
|
|
|
477
|
|
|
478 public:
|
|
|
479 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
|
|
|
480 ExternalAddress(Metadata** target) : AddressLiteral(target, reloc_for_target((address) target)) {}
|
|
|
481 };
|
|
|
482
|
|
|
483 inline Address RegisterImpl::address_in_saved_window() const {
|
|
|
484 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
|
|
|
485 }
|
|
|
486
|
|
|
487
|
|
|
488
|
|
|
489 // Argument is an abstraction used to represent an outgoing
|
|
|
490 // actual argument or an incoming formal parameter, whether
|
|
|
491 // it resides in memory or in a register, in a manner consistent
|
|
|
492 // with the SPARC Application Binary Interface, or ABI. This is
|
|
|
493 // often referred to as the native or C calling convention.
|
|
|
494
|
|
|
495 class Argument VALUE_OBJ_CLASS_SPEC {
|
|
|
496 private:
|
|
|
497 int _number;
|
|
|
498 bool _is_in;
|
|
|
499
|
|
|
500 public:
|
|
|
501 #ifdef _LP64
|
|
|
502 enum {
|
|
|
503 n_register_parameters = 6, // only 6 registers may contain integer parameters
|
|
|
504 n_float_register_parameters = 16 // Can have up to 16 floating registers
|
|
|
505 };
|
|
|
506 #else
|
|
|
507 enum {
|
|
|
508 n_register_parameters = 6 // only 6 registers may contain integer parameters
|
|
|
509 };
|
|
|
510 #endif
|
|
|
511
|
|
|
512 // creation
|
|
|
513 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
|
|
|
514
|
|
|
515 int number() const { return _number; }
|
|
|
516 bool is_in() const { return _is_in; }
|
|
|
517 bool is_out() const { return !is_in(); }
|
|
|
518
|
|
|
519 Argument successor() const { return Argument(number() + 1, is_in()); }
|
|
|
520 Argument as_in() const { return Argument(number(), true ); }
|
|
|
521 Argument as_out() const { return Argument(number(), false); }
|
|
|
522
|
|
|
523 // locating register-based arguments:
|
|
|
524 bool is_register() const { return _number < n_register_parameters; }
|
|
|
525
|
|
|
526 #ifdef _LP64
|
|
|
527 // locating Floating Point register-based arguments:
|
|
|
528 bool is_float_register() const { return _number < n_float_register_parameters; }
|
|
|
529
|
|
|
530 FloatRegister as_float_register() const {
|
|
|
531 assert(is_float_register(), "must be a register argument");
|
|
|
532 return as_FloatRegister(( number() *2 ) + 1);
|
|
|
533 }
|
|
|
534 FloatRegister as_double_register() const {
|
|
|
535 assert(is_float_register(), "must be a register argument");
|
|
|
536 return as_FloatRegister(( number() *2 ));
|
|
|
537 }
|
|
|
538 #endif
|
|
|
539
|
|
|
540 Register as_register() const {
|
|
|
541 assert(is_register(), "must be a register argument");
|
|
|
542 return is_in() ? as_iRegister(number()) : as_oRegister(number());
|
|
|
543 }
|
|
|
544
|
|
|
545 // locating memory-based arguments
|
|
|
546 Address as_address() const {
|
|
|
547 assert(!is_register(), "must be a memory argument");
|
|
|
548 return address_in_frame();
|
|
|
549 }
|
|
|
550
|
|
|
551 // When applied to a register-based argument, give the corresponding address
|
|
|
552 // into the 6-word area "into which callee may store register arguments"
|
|
|
553 // (This is a different place than the corresponding register-save area location.)
|
|
|
554 Address address_in_frame() const;
|
|
|
555
|
|
|
556 // debugging
|
|
|
557 const char* name() const;
|
|
|
558
|
|
|
559 friend class Assembler;
|
|
|
560 };
|
|
|
561
|
|
|
562
|
|
|
563 class RegistersForDebugging : public StackObj {
|
|
|
564 public:
|
|
|
565 intptr_t i[8], l[8], o[8], g[8];
|
|
|
566 float f[32];
|
|
|
567 double d[32];
|
|
|
568
|
|
|
569 void print(outputStream* s);
|
|
|
570
|
|
|
571 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
|
|
|
572 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
|
|
|
573 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
|
|
|
574 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
|
|
|
575 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
|
|
|
576 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
|
|
|
577
|
|
|
578 // gen asm code to save regs
|
|
|
579 static void save_registers(MacroAssembler* a);
|
|
|
580
|
|
|
581 // restore global registers in case C code disturbed them
|
|
|
582 static void restore_registers(MacroAssembler* a, Register r);
|
|
|
583 };
|
|
|
584
|
|
|
585
|
|
|
586 // MacroAssembler extends Assembler by a few frequently used macros.
|
|
|
587 //
|
|
|
588 // Most of the standard SPARC synthetic ops are defined here.
|
|
|
589 // Instructions for which a 'better' code sequence exists depending
|
|
|
590 // on arguments should also go in here.
|
|
|
591
|
|
|
592 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
|
|
|
593 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
|
|
|
594 #define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__)
|
|
|
595 #define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__)
|
|
|
596
|
|
|
597
|
|
|
598 class MacroAssembler : public Assembler {
|
|
|
599 // code patchers need various routines like inv_wdisp()
|
|
|
600 friend class NativeInstruction;
|
|
|
601 friend class NativeGeneralJump;
|
|
|
602 friend class Relocation;
|
|
|
603 friend class Label;
|
|
|
604
|
|
|
605 protected:
|
|
|
606 static int patched_branch(int dest_pos, int inst, int inst_pos);
|
|
|
607 static int branch_destination(int inst, int pos);
|
|
|
608
|
|
|
609 // Support for VM calls
|
|
|
610 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
|
|
|
611 // may customize this version by overriding it for its purposes (e.g., to save/restore
|
|
|
612 // additional registers when doing a VM call).
|
|
|
613 #ifdef CC_INTERP
|
|
|
614 #define VIRTUAL
|
|
|
615 #else
|
|
|
616 #define VIRTUAL virtual
|
|
|
617 #endif
|
|
|
618
|
|
|
619 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
|
|
|
620
|
|
|
621 //
|
|
|
622 // It is imperative that all calls into the VM are handled via the call_VM macros.
|
|
|
623 // They make sure that the stack linkage is setup correctly. call_VM's correspond
|
|
|
624 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
|
|
|
625 //
|
|
|
626 // This is the base routine called by the different versions of call_VM. The interpreter
|
|
|
627 // may customize this version by overriding it for its purposes (e.g., to save/restore
|
|
|
628 // additional registers when doing a VM call).
|
|
|
629 //
|
|
|
630 // A non-volatile java_thread_cache register should be specified so
|
|
|
631 // that the G2_thread value can be preserved across the call.
|
|
|
632 // (If java_thread_cache is noreg, then a slow get_thread call
|
|
|
633 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
|
|
|
634 // thread.
|
|
|
635 //
|
|
|
636 // If no last_java_sp is specified (noreg) than SP will be used instead.
|
|
|
637
|
|
|
638 virtual void call_VM_base(
|
|
|
639 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
|
|
|
640 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
|
|
|
641 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
|
|
|
642 address entry_point, // the entry point
|
|
|
643 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
|
|
|
644 bool check_exception=true // flag which indicates if exception should be checked
|
|
|
645 );
|
|
|
646
|
|
|
647 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
|
|
|
648 // The implementation is only non-empty for the InterpreterMacroAssembler,
|
|
|
649 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
|
|
|
650 virtual void check_and_handle_popframe(Register scratch_reg);
|
|
|
651 virtual void check_and_handle_earlyret(Register scratch_reg);
|
|
|
652
|
|
|
653 public:
|
|
|
654 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
|
|
|
655
|
|
|
656 // Support for NULL-checks
|
|
|
657 //
|
|
|
658 // Generates code that causes a NULL OS exception if the content of reg is NULL.
|
|
|
659 // If the accessed location is M[reg + offset] and the offset is known, provide the
|
|
|
660 // offset. No explicit code generation is needed if the offset is within a certain
|
|
|
661 // range (0 <= offset <= page_size).
|
|
|
662 //
|
|
|
663 // %%%%%% Currently not done for SPARC
|
|
|
664
|
|
|
665 void null_check(Register reg, int offset = -1);
|
|
|
666 static bool needs_explicit_null_check(intptr_t offset);
|
|
|
667
|
|
|
668 // support for delayed instructions
|
|
|
669 MacroAssembler* delayed() { Assembler::delayed(); return this; }
|
|
|
670
|
|
|
671 // branches that use right instruction for v8 vs. v9
|
|
|
672 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
673 inline void br( Condition c, bool a, Predict p, Label& L );
|
|
|
674
|
|
|
675 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
676 inline void fb( Condition c, bool a, Predict p, Label& L );
|
|
|
677
|
|
|
678 // compares register with zero (32 bit) and branches (V9 and V8 instructions)
|
|
|
679 void cmp_zero_and_br( Condition c, Register s1, Label& L, bool a = false, Predict p = pn );
|
|
|
680 // Compares a pointer register with zero and branches on (not)null.
|
|
|
681 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
|
|
|
682 void br_null ( Register s1, bool a, Predict p, Label& L );
|
|
|
683 void br_notnull( Register s1, bool a, Predict p, Label& L );
|
|
|
684
|
|
|
685 //
|
|
|
686 // Compare registers and branch with nop in delay slot or cbcond without delay slot.
|
|
|
687 //
|
|
|
688 // ATTENTION: use these instructions with caution because cbcond instruction
|
|
|
689 // has very short distance: 512 instructions (2Kbyte).
|
|
|
690
|
|
|
691 // Compare integer (32 bit) values (icc only).
|
|
|
692 void cmp_and_br_short(Register s1, Register s2, Condition c, Predict p, Label& L);
|
|
|
693 void cmp_and_br_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
|
|
|
694 // Platform depending version for pointer compare (icc on !LP64 and xcc on LP64).
|
|
|
695 void cmp_and_brx_short(Register s1, Register s2, Condition c, Predict p, Label& L);
|
|
|
696 void cmp_and_brx_short(Register s1, int simm13a, Condition c, Predict p, Label& L);
|
|
|
697
|
|
|
698 // Short branch version for compares a pointer pwith zero.
|
|
|
699 void br_null_short ( Register s1, Predict p, Label& L );
|
|
|
700 void br_notnull_short( Register s1, Predict p, Label& L );
|
|
|
701
|
|
|
702 // unconditional short branch
|
|
|
703 void ba_short(Label& L);
|
|
|
704
|
|
|
705 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
706 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
|
|
|
707
|
|
|
708 // Branch that tests xcc in LP64 and icc in !LP64
|
|
|
709 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
710 inline void brx( Condition c, bool a, Predict p, Label& L );
|
|
|
711
|
|
|
712 // unconditional branch
|
|
|
713 inline void ba( Label& L );
|
|
|
714
|
|
|
715 // Branch that tests fp condition codes
|
|
|
716 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
717 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
|
|
|
718
|
|
|
719 // get PC the best way
|
|
|
720 inline int get_pc( Register d );
|
|
|
721
|
|
|
722 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
|
|
|
723 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
|
|
|
724 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
|
|
|
725
|
|
|
726 inline void jmp( Register s1, Register s2 );
|
|
|
727 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
|
|
|
728
|
|
|
729 // Check if the call target is out of wdisp30 range (relative to the code cache)
|
|
|
730 static inline bool is_far_target(address d);
|
|
|
731 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
|
|
|
732 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
|
|
|
733 inline void callr( Register s1, Register s2 );
|
|
|
734 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
|
|
|
735
|
|
|
736 // Emits nothing on V8
|
|
|
737 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
|
|
|
738 inline void iprefetch( Label& L);
|
|
|
739
|
|
|
740 inline void tst( Register s ) { orcc( G0, s, G0 ); }
|
|
|
741
|
|
|
742 #ifdef PRODUCT
|
|
|
743 inline void ret( bool trace = TraceJumps ) { if (trace) {
|
|
|
744 mov(I7, O7); // traceable register
|
|
|
745 JMP(O7, 2 * BytesPerInstWord);
|
|
|
746 } else {
|
|
|
747 jmpl( I7, 2 * BytesPerInstWord, G0 );
|
|
|
748 }
|
|
|
749 }
|
|
|
750
|
|
|
751 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
|
|
|
752 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
|
|
|
753 #else
|
|
|
754 void ret( bool trace = TraceJumps );
|
|
|
755 void retl( bool trace = TraceJumps );
|
|
|
756 #endif /* PRODUCT */
|
|
|
757
|
|
|
758 // Required platform-specific helpers for Label::patch_instructions.
|
|
|
759 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
|
|
|
760 void pd_patch_instruction(address branch, address target);
|
|
|
761
|
|
|
762 // sethi Macro handles optimizations and relocations
|
|
|
763 private:
|
|
|
764 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable);
|
|
|
765 public:
|
|
|
766 void sethi(const AddressLiteral& addrlit, Register d);
|
|
|
767 void patchable_sethi(const AddressLiteral& addrlit, Register d);
|
|
|
768
|
|
|
769 // compute the number of instructions for a sethi/set
|
|
|
770 static int insts_for_sethi( address a, bool worst_case = false );
|
|
|
771 static int worst_case_insts_for_set();
|
|
|
772
|
|
|
773 // set may be either setsw or setuw (high 32 bits may be zero or sign)
|
|
|
774 private:
|
|
|
775 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable);
|
|
|
776 static int insts_for_internal_set(intptr_t value);
|
|
|
777 public:
|
|
|
778 void set(const AddressLiteral& addrlit, Register d);
|
|
|
779 void set(intptr_t value, Register d);
|
|
|
780 void set(address addr, Register d, RelocationHolder const& rspec);
|
|
|
781 static int insts_for_set(intptr_t value) { return insts_for_internal_set(value); }
|
|
|
782
|
|
|
783 void patchable_set(const AddressLiteral& addrlit, Register d);
|
|
|
784 void patchable_set(intptr_t value, Register d);
|
|
|
785 void set64(jlong value, Register d, Register tmp);
|
|
|
786 static int insts_for_set64(jlong value);
|
|
|
787
|
|
|
788 // sign-extend 32 to 64
|
|
|
789 inline void signx( Register s, Register d ) { sra( s, G0, d); }
|
|
|
790 inline void signx( Register d ) { sra( d, G0, d); }
|
|
|
791
|
|
|
792 inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
|
|
|
793 inline void not1( Register d ) { xnor( d, G0, d ); }
|
|
|
794
|
|
|
795 inline void neg( Register s, Register d ) { sub( G0, s, d ); }
|
|
|
796 inline void neg( Register d ) { sub( G0, d, d ); }
|
|
|
797
|
|
|
798 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
|
|
|
799 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
|
|
|
800 // Functions for isolating 64 bit atomic swaps for LP64
|
|
|
801 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
|
|
|
802 inline void cas_ptr( Register s1, Register s2, Register d) {
|
|
|
803 #ifdef _LP64
|
|
|
804 casx( s1, s2, d );
|
|
|
805 #else
|
|
|
806 cas( s1, s2, d );
|
|
|
807 #endif
|
|
|
808 }
|
|
|
809
|
|
|
810 // Functions for isolating 64 bit shifts for LP64
|
|
|
811 inline void sll_ptr( Register s1, Register s2, Register d );
|
|
|
812 inline void sll_ptr( Register s1, int imm6a, Register d );
|
|
|
813 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d );
|
|
|
814 inline void srl_ptr( Register s1, Register s2, Register d );
|
|
|
815 inline void srl_ptr( Register s1, int imm6a, Register d );
|
|
|
816
|
|
|
817 // little-endian
|
|
|
818 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
|
|
|
819 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
|
|
|
820
|
|
|
821 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
|
|
|
822 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
|
|
|
823
|
|
|
824 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
|
|
|
825 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
|
|
|
826
|
|
|
827 using Assembler::add;
|
|
|
828 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype);
|
|
|
829 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec);
|
|
|
830 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
|
|
|
831 inline void add(const Address& a, Register d, int offset = 0);
|
|
|
832
|
|
|
833 using Assembler::andn;
|
|
|
834 inline void andn( Register s1, RegisterOrConstant s2, Register d);
|
|
|
835
|
|
|
836 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
|
|
|
837 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
|
|
|
838
|
|
|
839 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
|
|
|
840 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
|
|
|
841
|
|
|
842 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
|
|
|
843 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
|
|
|
844
|
|
|
845 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
|
|
|
846 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
|
|
|
847
|
|
|
848 inline void clr( Register d ) { or3( G0, G0, d ); }
|
|
|
849
|
|
|
850 inline void clrb( Register s1, Register s2);
|
|
|
851 inline void clrh( Register s1, Register s2);
|
|
|
852 inline void clr( Register s1, Register s2);
|
|
|
853 inline void clrx( Register s1, Register s2);
|
|
|
854
|
|
|
855 inline void clrb( Register s1, int simm13a);
|
|
|
856 inline void clrh( Register s1, int simm13a);
|
|
|
857 inline void clr( Register s1, int simm13a);
|
|
|
858 inline void clrx( Register s1, int simm13a);
|
|
|
859
|
|
|
860 // copy & clear upper word
|
|
|
861 inline void clruw( Register s, Register d ) { srl( s, G0, d); }
|
|
|
862 // clear upper word
|
|
|
863 inline void clruwu( Register d ) { srl( d, G0, d); }
|
|
|
864
|
|
|
865 using Assembler::ldsb;
|
|
|
866 using Assembler::ldsh;
|
|
|
867 using Assembler::ldsw;
|
|
|
868 using Assembler::ldub;
|
|
|
869 using Assembler::lduh;
|
|
|
870 using Assembler::lduw;
|
|
|
871 using Assembler::ldx;
|
|
|
872 using Assembler::ldd;
|
|
|
873
|
|
|
874 #ifdef ASSERT
|
|
|
875 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
|
|
|
876 inline void ld(Register s1, ByteSize simm13a, Register d);
|
|
|
877 #endif
|
|
|
878
|
|
|
879 inline void ld(Register s1, Register s2, Register d);
|
|
|
880 inline void ld(Register s1, int simm13a, Register d);
|
|
|
881
|
|
|
882 inline void ldsb(const Address& a, Register d, int offset = 0);
|
|
|
883 inline void ldsh(const Address& a, Register d, int offset = 0);
|
|
|
884 inline void ldsw(const Address& a, Register d, int offset = 0);
|
|
|
885 inline void ldub(const Address& a, Register d, int offset = 0);
|
|
|
886 inline void lduh(const Address& a, Register d, int offset = 0);
|
|
|
887 inline void lduw(const Address& a, Register d, int offset = 0);
|
|
|
888 inline void ldx( const Address& a, Register d, int offset = 0);
|
|
|
889 inline void ld( const Address& a, Register d, int offset = 0);
|
|
|
890 inline void ldd( const Address& a, Register d, int offset = 0);
|
|
|
891
|
|
|
892 inline void ldub(Register s1, RegisterOrConstant s2, Register d );
|
|
|
893 inline void ldsb(Register s1, RegisterOrConstant s2, Register d );
|
|
|
894 inline void lduh(Register s1, RegisterOrConstant s2, Register d );
|
|
|
895 inline void ldsh(Register s1, RegisterOrConstant s2, Register d );
|
|
|
896 inline void lduw(Register s1, RegisterOrConstant s2, Register d );
|
|
|
897 inline void ldsw(Register s1, RegisterOrConstant s2, Register d );
|
|
|
898 inline void ldx( Register s1, RegisterOrConstant s2, Register d );
|
|
|
899 inline void ld( Register s1, RegisterOrConstant s2, Register d );
|
|
|
900 inline void ldd( Register s1, RegisterOrConstant s2, Register d );
|
|
|
901
|
|
|
902 using Assembler::ldf;
|
|
|
903 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d);
|
|
|
904 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
|
|
|
905
|
|
|
906 // membar psuedo instruction. takes into account target memory model.
|
|
|
907 inline void membar( Assembler::Membar_mask_bits const7a );
|
|
|
908
|
|
|
909 // returns if membar generates anything.
|
|
|
910 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
|
|
|
911
|
|
|
912 // mov pseudo instructions
|
|
|
913 inline void mov( Register s, Register d) {
|
|
|
914 if ( s != d ) or3( G0, s, d);
|
|
|
915 else assert_not_delayed(); // Put something useful in the delay slot!
|
|
|
916 }
|
|
|
917
|
|
|
918 inline void mov_or_nop( Register s, Register d) {
|
|
|
919 if ( s != d ) or3( G0, s, d);
|
|
|
920 else nop();
|
|
|
921 }
|
|
|
922
|
|
|
923 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
|
|
|
924
|
|
|
925 using Assembler::prefetch;
|
|
|
926 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
|
|
|
927
|
|
|
928 using Assembler::stb;
|
|
|
929 using Assembler::sth;
|
|
|
930 using Assembler::stw;
|
|
|
931 using Assembler::stx;
|
|
|
932 using Assembler::std;
|
|
|
933
|
|
|
934 #ifdef ASSERT
|
|
|
935 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
|
|
|
936 inline void st(Register d, Register s1, ByteSize simm13a);
|
|
|
937 #endif
|
|
|
938
|
|
|
939 inline void st(Register d, Register s1, Register s2);
|
|
|
940 inline void st(Register d, Register s1, int simm13a);
|
|
|
941
|
|
|
942 inline void stb(Register d, const Address& a, int offset = 0 );
|
|
|
943 inline void sth(Register d, const Address& a, int offset = 0 );
|
|
|
944 inline void stw(Register d, const Address& a, int offset = 0 );
|
|
|
945 inline void stx(Register d, const Address& a, int offset = 0 );
|
|
|
946 inline void st( Register d, const Address& a, int offset = 0 );
|
|
|
947 inline void std(Register d, const Address& a, int offset = 0 );
|
|
|
948
|
|
|
949 inline void stb(Register d, Register s1, RegisterOrConstant s2 );
|
|
|
950 inline void sth(Register d, Register s1, RegisterOrConstant s2 );
|
|
|
951 inline void stw(Register d, Register s1, RegisterOrConstant s2 );
|
|
|
952 inline void stx(Register d, Register s1, RegisterOrConstant s2 );
|
|
|
953 inline void std(Register d, Register s1, RegisterOrConstant s2 );
|
|
|
954 inline void st( Register d, Register s1, RegisterOrConstant s2 );
|
|
|
955
|
|
|
956 using Assembler::stf;
|
|
|
957 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2);
|
|
|
958 inline void stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
|
|
|
959
|
|
|
960 // Note: offset is added to s2.
|
|
|
961 using Assembler::sub;
|
|
|
962 inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0);
|
|
|
963
|
|
|
964 using Assembler::swap;
|
|
|
965 inline void swap(Address& a, Register d, int offset = 0);
|
|
|
966
|
|
|
967 // address pseudos: make these names unlike instruction names to avoid confusion
|
|
|
968 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
|
|
|
969 inline void load_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
|
|
|
970 inline void load_bool_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
|
|
|
971 inline void load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset = 0);
|
|
|
972 inline void store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
|
|
|
973 inline void store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset = 0);
|
|
|
974 inline void jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset = 0);
|
|
|
975 inline void jump_to(const AddressLiteral& addrlit, Register temp, int offset = 0);
|
|
|
976 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0);
|
|
|
977
|
|
|
978 // ring buffer traceable jumps
|
|
|
979
|
|
|
980 void jmp2( Register r1, Register r2, const char* file, int line );
|
|
|
981 void jmp ( Register r1, int offset, const char* file, int line );
|
|
|
982
|
|
|
983 void jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line);
|
|
|
984 void jump (const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line);
|
|
|
985
|
|
|
986
|
|
|
987 // argument pseudos:
|
|
|
988
|
|
|
989 inline void load_argument( Argument& a, Register d );
|
|
|
990 inline void store_argument( Register s, Argument& a );
|
|
|
991 inline void store_ptr_argument( Register s, Argument& a );
|
|
|
992 inline void store_float_argument( FloatRegister s, Argument& a );
|
|
|
993 inline void store_double_argument( FloatRegister s, Argument& a );
|
|
|
994 inline void store_long_argument( Register s, Argument& a );
|
|
|
995
|
|
|
996 // handy macros:
|
|
|
997
|
|
|
998 inline void round_to( Register r, int modulus ) {
|
|
|
999 assert_not_delayed();
|
|
|
1000 inc( r, modulus - 1 );
|
|
|
1001 and3( r, -modulus, r );
|
|
|
1002 }
|
|
|
1003
|
|
|
1004 // --------------------------------------------------
|
|
|
1005
|
|
|
1006 // Functions for isolating 64 bit loads for LP64
|
|
|
1007 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
|
|
|
1008 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
|
|
|
1009 inline void ld_ptr(Register s1, Register s2, Register d);
|
|
|
1010 inline void ld_ptr(Register s1, int simm13a, Register d);
|
|
|
1011 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d);
|
|
|
1012 inline void ld_ptr(const Address& a, Register d, int offset = 0);
|
|
|
1013 inline void st_ptr(Register d, Register s1, Register s2);
|
|
|
1014 inline void st_ptr(Register d, Register s1, int simm13a);
|
|
|
1015 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2);
|
|
|
1016 inline void st_ptr(Register d, const Address& a, int offset = 0);
|
|
|
1017
|
|
|
1018 #ifdef ASSERT
|
|
|
1019 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
|
|
|
1020 inline void ld_ptr(Register s1, ByteSize simm13a, Register d);
|
|
|
1021 inline void st_ptr(Register d, Register s1, ByteSize simm13a);
|
|
|
1022 #endif
|
|
|
1023
|
|
|
1024 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's
|
|
|
1025 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's
|
|
|
1026 inline void ld_long(Register s1, Register s2, Register d);
|
|
|
1027 inline void ld_long(Register s1, int simm13a, Register d);
|
|
|
1028 inline void ld_long(Register s1, RegisterOrConstant s2, Register d);
|
|
|
1029 inline void ld_long(const Address& a, Register d, int offset = 0);
|
|
|
1030 inline void st_long(Register d, Register s1, Register s2);
|
|
|
1031 inline void st_long(Register d, Register s1, int simm13a);
|
|
|
1032 inline void st_long(Register d, Register s1, RegisterOrConstant s2);
|
|
|
1033 inline void st_long(Register d, const Address& a, int offset = 0);
|
|
|
1034
|
|
|
1035 // Helpers for address formation.
|
|
|
1036 // - They emit only a move if s2 is a constant zero.
|
|
|
1037 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result.
|
|
|
1038 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant.
|
|
|
1039 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
|
|
|
1040 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
|
|
|
1041 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg);
|
|
|
1042
|
|
|
1043 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) {
|
|
|
1044 if (is_simm13(src.constant_or_zero()))
|
|
|
1045 return src; // register or short constant
|
|
|
1046 guarantee(temp != noreg, "constant offset overflow");
|
|
|
1047 set(src.as_constant(), temp);
|
|
|
1048 return temp;
|
|
|
1049 }
|
|
|
1050
|
|
|
1051 // --------------------------------------------------
|
|
|
1052
|
|
|
1053 public:
|
|
|
1054 // traps as per trap.h (SPARC ABI?)
|
|
|
1055
|
|
|
1056 void breakpoint_trap();
|
|
|
1057 void breakpoint_trap(Condition c, CC cc);
|
|
|
1058 void flush_windows_trap();
|
|
|
1059 void clean_windows_trap();
|
|
|
1060 void get_psr_trap();
|
|
|
1061 void set_psr_trap();
|
|
|
1062
|
|
|
1063 // V8/V9 flush_windows
|
|
|
1064 void flush_windows();
|
|
|
1065
|
|
|
1066 // Support for serializing memory accesses between threads
|
|
|
1067 void serialize_memory(Register thread, Register tmp1, Register tmp2);
|
|
|
1068
|
|
|
1069 // Stack frame creation/removal
|
|
|
1070 void enter();
|
|
|
1071 void leave();
|
|
|
1072
|
|
|
1073 // V8/V9 integer multiply
|
|
|
1074 void mult(Register s1, Register s2, Register d);
|
|
|
1075 void mult(Register s1, int simm13a, Register d);
|
|
|
1076
|
|
|
1077 // V8/V9 read and write of condition codes.
|
|
|
1078 void read_ccr(Register d);
|
|
|
1079 void write_ccr(Register s);
|
|
|
1080
|
|
|
1081 // Manipulation of C++ bools
|
|
|
1082 // These are idioms to flag the need for care with accessing bools but on
|
|
|
1083 // this platform we assume byte size
|
|
|
1084
|
|
|
1085 inline void stbool(Register d, const Address& a) { stb(d, a); }
|
|
|
1086 inline void ldbool(const Address& a, Register d) { ldub(a, d); }
|
|
|
1087 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
|
|
|
1088
|
|
|
1089 // klass oop manipulations if compressed
|
|
|
1090 void load_klass(Register src_oop, Register klass);
|
|
|
1091 void store_klass(Register klass, Register dst_oop);
|
|
|
1092 void store_klass_gap(Register s, Register dst_oop);
|
|
|
1093
|
|
|
1094 // oop manipulations
|
|
|
1095 void load_heap_oop(const Address& s, Register d);
|
|
|
1096 void load_heap_oop(Register s1, Register s2, Register d);
|
|
|
1097 void load_heap_oop(Register s1, int simm13a, Register d);
|
|
|
1098 void load_heap_oop(Register s1, RegisterOrConstant s2, Register d);
|
|
|
1099 void store_heap_oop(Register d, Register s1, Register s2);
|
|
|
1100 void store_heap_oop(Register d, Register s1, int simm13a);
|
|
|
1101 void store_heap_oop(Register d, const Address& a, int offset = 0);
|
|
|
1102
|
|
|
1103 void encode_heap_oop(Register src, Register dst);
|
|
|
1104 void encode_heap_oop(Register r) {
|
|
|
1105 encode_heap_oop(r, r);
|
|
|
1106 }
|
|
|
1107 void decode_heap_oop(Register src, Register dst);
|
|
|
1108 void decode_heap_oop(Register r) {
|
|
|
1109 decode_heap_oop(r, r);
|
|
|
1110 }
|
|
|
1111 void encode_heap_oop_not_null(Register r);
|
|
|
1112 void decode_heap_oop_not_null(Register r);
|
|
|
1113 void encode_heap_oop_not_null(Register src, Register dst);
|
|
|
1114 void decode_heap_oop_not_null(Register src, Register dst);
|
|
|
1115
|
|
|
1116 void encode_klass_not_null(Register r);
|
|
|
1117 void decode_klass_not_null(Register r);
|
|
|
1118 void encode_klass_not_null(Register src, Register dst);
|
|
|
1119 void decode_klass_not_null(Register src, Register dst);
|
|
|
1120
|
|
|
1121 // Support for managing the JavaThread pointer (i.e.; the reference to
|
|
|
1122 // thread-local information).
|
|
|
1123 void get_thread(); // load G2_thread
|
|
|
1124 void verify_thread(); // verify G2_thread contents
|
|
|
1125 void save_thread (const Register threache); // save to cache
|
|
|
1126 void restore_thread(const Register thread_cache); // restore from cache
|
|
|
1127
|
|
|
1128 // Support for last Java frame (but use call_VM instead where possible)
|
|
|
1129 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
|
|
|
1130 void reset_last_Java_frame(void);
|
|
|
1131
|
|
|
1132 // Call into the VM.
|
|
|
1133 // Passes the thread pointer (in O0) as a prepended argument.
|
|
|
1134 // Makes sure oop return values are visible to the GC.
|
|
|
1135 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
|
|
|
1136 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
|
|
|
1137 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
|
|
|
1138 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
|
|
|
1139
|
|
|
1140 // these overloadings are not presently used on SPARC:
|
|
|
1141 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
|
|
|
1142 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
|
|
|
1143 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
|
|
|
1144 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
|
|
|
1145
|
|
|
1146 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
|
|
|
1147 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
|
|
|
1148 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
|
|
|
1149 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
|
|
|
1150
|
|
|
1151 void get_vm_result (Register oop_result);
|
|
|
1152 void get_vm_result_2(Register metadata_result);
|
|
|
1153
|
|
|
1154 // vm result is currently getting hijacked to for oop preservation
|
|
|
1155 void set_vm_result(Register oop_result);
|
|
|
1156
|
|
|
1157 // Emit the CompiledIC call idiom
|
|
|
1158 void ic_call(address entry, bool emit_delay = true);
|
|
|
1159
|
|
|
1160 // if call_VM_base was called with check_exceptions=false, then call
|
|
|
1161 // check_and_forward_exception to handle exceptions when it is safe
|
|
|
1162 void check_and_forward_exception(Register scratch_reg);
|
|
|
1163
|
|
|
1164 private:
|
|
|
1165 // For V8
|
|
|
1166 void read_ccr_trap(Register ccr_save);
|
|
|
1167 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
|
|
|
1168
|
|
|
1169 #ifdef ASSERT
|
|
|
1170 // For V8 debugging. Uses V8 instruction sequence and checks
|
|
|
1171 // result with V9 insturctions rdccr and wrccr.
|
|
|
1172 // Uses Gscatch and Gscatch2
|
|
|
1173 void read_ccr_v8_assert(Register ccr_save);
|
|
|
1174 void write_ccr_v8_assert(Register ccr_save);
|
|
|
1175 #endif // ASSERT
|
|
|
1176
|
|
|
1177 public:
|
|
|
1178
|
|
|
1179 // Write to card table for - register is destroyed afterwards.
|
|
|
1180 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
|
|
|
1181
|
|
|
1182 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
|
|
|
1183
|
|
|
1184 #ifndef SERIALGC
|
|
|
1185 // General G1 pre-barrier generator.
|
|
|
1186 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
|
|
|
1187
|
|
|
1188 // General G1 post-barrier generator
|
|
|
1189 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
|
|
|
1190 #endif // SERIALGC
|
|
|
1191
|
|
|
1192 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
|
|
|
1193 void push_fTOS();
|
|
|
1194
|
|
|
1195 // pops double TOS element from CPU stack and pushes on FPU stack
|
|
|
1196 void pop_fTOS();
|
|
|
1197
|
|
|
1198 void empty_FPU_stack();
|
|
|
1199
|
|
|
1200 void push_IU_state();
|
|
|
1201 void pop_IU_state();
|
|
|
1202
|
|
|
1203 void push_FPU_state();
|
|
|
1204 void pop_FPU_state();
|
|
|
1205
|
|
|
1206 void push_CPU_state();
|
|
|
1207 void pop_CPU_state();
|
|
|
1208
|
|
|
1209 // if heap base register is used - reinit it with the correct value
|
|
|
1210 void reinit_heapbase();
|
|
|
1211
|
|
|
1212 // Debugging
|
|
|
1213 void _verify_oop(Register reg, const char * msg, const char * file, int line);
|
|
|
1214 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
|
|
|
1215
|
|
|
1216 // TODO: verify_method and klass metadata (compare against vptr?)
|
|
|
1217 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
|
|
|
1218 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
|
|
|
1219
|
|
|
1220 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
|
|
|
1221 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
|
|
|
1222 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
|
|
|
1223 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
|
|
|
1224
|
|
|
1225 // only if +VerifyOops
|
|
|
1226 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
|
|
|
1227 // only if +VerifyFPU
|
|
|
1228 void stop(const char* msg); // prints msg, dumps registers and stops execution
|
|
|
1229 void warn(const char* msg); // prints msg, but don't stop
|
|
|
1230 void untested(const char* what = "");
|
|
|
1231 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
|
|
|
1232 void should_not_reach_here() { stop("should not reach here"); }
|
|
|
1233 void print_CPU_state();
|
|
|
1234
|
|
|
1235 // oops in code
|
|
|
1236 AddressLiteral allocate_oop_address(jobject obj); // allocate_index
|
|
|
1237 AddressLiteral constant_oop_address(jobject obj); // find_index
|
|
|
1238 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address
|
|
|
1239 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address
|
|
|
1240 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address
|
|
|
1241
|
|
|
1242 // metadata in code that we have to keep track of
|
|
|
1243 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
|
|
|
1244 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
|
|
|
1245 inline void set_metadata (Metadata* obj, Register d); // uses allocate_metadata_address
|
|
|
1246 inline void set_metadata_constant (Metadata* obj, Register d); // uses constant_metadata_address
|
|
|
1247 inline void set_metadata (const AddressLiteral& obj_addr, Register d); // same as load_address
|
|
|
1248
|
|
|
1249 void set_narrow_oop( jobject obj, Register d );
|
|
|
1250 void set_narrow_klass( Klass* k, Register d );
|
|
|
1251
|
|
|
1252 // nop padding
|
|
|
1253 void align(int modulus);
|
|
|
1254
|
|
|
1255 // declare a safepoint
|
|
|
1256 void safepoint();
|
|
|
1257
|
|
|
1258 // factor out part of stop into subroutine to save space
|
|
|
1259 void stop_subroutine();
|
|
|
1260 // factor out part of verify_oop into subroutine to save space
|
|
|
1261 void verify_oop_subroutine();
|
|
|
1262
|
|
|
1263 // side-door communication with signalHandler in os_solaris.cpp
|
|
|
1264 static address _verify_oop_implicit_branch[3];
|
|
|
1265
|
|
|
1266 int total_frame_size_in_bytes(int extraWords);
|
|
|
1267
|
|
|
1268 // used when extraWords known statically
|
|
|
1269 void save_frame(int extraWords = 0);
|
|
|
1270 void save_frame_c1(int size_in_bytes);
|
|
|
1271 // make a frame, and simultaneously pass up one or two register value
|
|
|
1272 // into the new register window
|
|
|
1273 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
|
|
|
1274
|
|
|
1275 // give no. (outgoing) params, calc # of words will need on frame
|
|
|
1276 void calc_mem_param_words(Register Rparam_words, Register Rresult);
|
|
|
1277
|
|
|
1278 // used to calculate frame size dynamically
|
|
|
1279 // result is in bytes and must be negated for save inst
|
|
|
1280 void calc_frame_size(Register extraWords, Register resultReg);
|
|
|
1281
|
|
|
1282 // calc and also save
|
|
|
1283 void calc_frame_size_and_save(Register extraWords, Register resultReg);
|
|
|
1284
|
|
|
1285 static void debug(char* msg, RegistersForDebugging* outWindow);
|
|
|
1286
|
|
|
1287 // implementations of bytecodes used by both interpreter and compiler
|
|
|
1288
|
|
|
1289 void lcmp( Register Ra_hi, Register Ra_low,
|
|
|
1290 Register Rb_hi, Register Rb_low,
|
|
|
1291 Register Rresult);
|
|
|
1292
|
|
|
1293 void lneg( Register Rhi, Register Rlow );
|
|
|
1294
|
|
|
1295 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
|
|
|
1296 Register Rout_high, Register Rout_low, Register Rtemp );
|
|
|
1297
|
|
|
1298 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
|
|
|
1299 Register Rout_high, Register Rout_low, Register Rtemp );
|
|
|
1300
|
|
|
1301 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
|
|
|
1302 Register Rout_high, Register Rout_low, Register Rtemp );
|
|
|
1303
|
|
|
1304 #ifdef _LP64
|
|
|
1305 void lcmp( Register Ra, Register Rb, Register Rresult);
|
|
|
1306 #endif
|
|
|
1307
|
|
|
1308 // Load and store values by size and signed-ness
|
|
|
1309 void load_sized_value( Address src, Register dst, size_t size_in_bytes, bool is_signed);
|
|
|
1310 void store_sized_value(Register src, Address dst, size_t size_in_bytes);
|
|
|
1311
|
|
|
1312 void float_cmp( bool is_float, int unordered_result,
|
|
|
1313 FloatRegister Fa, FloatRegister Fb,
|
|
|
1314 Register Rresult);
|
|
|
1315
|
|
|
1316 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
|
|
|
1317 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
|
|
|
1318 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
|
|
|
1319 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
|
|
|
1320
|
|
|
1321 void save_all_globals_into_locals();
|
|
|
1322 void restore_globals_from_locals();
|
|
|
1323
|
|
|
1324 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
|
|
|
1325 address lock_addr=0, bool use_call_vm=false);
|
|
|
1326 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
|
|
|
1327 address lock_addr=0, bool use_call_vm=false);
|
|
|
1328 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
|
|
|
1329
|
|
|
1330 // These set the icc condition code to equal if the lock succeeded
|
|
|
1331 // and notEqual if it failed and requires a slow case
|
|
|
1332 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
|
|
|
1333 Register Rscratch,
|
|
|
1334 BiasedLockingCounters* counters = NULL,
|
|
|
1335 bool try_bias = UseBiasedLocking);
|
|
|
1336 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
|
|
|
1337 Register Rscratch,
|
|
|
1338 bool try_bias = UseBiasedLocking);
|
|
|
1339
|
|
|
1340 // Biased locking support
|
|
|
1341 // Upon entry, lock_reg must point to the lock record on the stack,
|
|
|
1342 // obj_reg must contain the target object, and mark_reg must contain
|
|
|
1343 // the target object's header.
|
|
|
1344 // Destroys mark_reg if an attempt is made to bias an anonymously
|
|
|
1345 // biased lock. In this case a failure will go either to the slow
|
|
|
1346 // case or fall through with the notEqual condition code set with
|
|
|
1347 // the expectation that the slow case in the runtime will be called.
|
|
|
1348 // In the fall-through case where the CAS-based lock is done,
|
|
|
1349 // mark_reg is not destroyed.
|
|
|
1350 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
|
|
|
1351 Label& done, Label* slow_case = NULL,
|
|
|
1352 BiasedLockingCounters* counters = NULL);
|
|
|
1353 // Upon entry, the base register of mark_addr must contain the oop.
|
|
|
1354 // Destroys temp_reg.
|
|
|
1355
|
|
|
1356 // If allow_delay_slot_filling is set to true, the next instruction
|
|
|
1357 // emitted after this one will go in an annulled delay slot if the
|
|
|
1358 // biased locking exit case failed.
|
|
|
1359 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
|
|
|
1360
|
|
|
1361 // allocation
|
|
|
1362 void eden_allocate(
|
|
|
1363 Register obj, // result: pointer to object after successful allocation
|
|
|
1364 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
|
1365 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
|
1366 Register t1, // temp register
|
|
|
1367 Register t2, // temp register
|
|
|
1368 Label& slow_case // continuation point if fast allocation fails
|
|
|
1369 );
|
|
|
1370 void tlab_allocate(
|
|
|
1371 Register obj, // result: pointer to object after successful allocation
|
|
|
1372 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
|
1373 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
|
1374 Register t1, // temp register
|
|
|
1375 Label& slow_case // continuation point if fast allocation fails
|
|
|
1376 );
|
|
|
1377 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
|
|
|
1378 void incr_allocated_bytes(RegisterOrConstant size_in_bytes,
|
|
|
1379 Register t1, Register t2);
|
|
|
1380
|
|
|
1381 // interface method calling
|
|
|
1382 void lookup_interface_method(Register recv_klass,
|
|
|
1383 Register intf_klass,
|
|
|
1384 RegisterOrConstant itable_index,
|
|
|
1385 Register method_result,
|
|
|
1386 Register temp_reg, Register temp2_reg,
|
|
|
1387 Label& no_such_interface);
|
|
|
1388
|
|
|
1389 // virtual method calling
|
|
|
1390 void lookup_virtual_method(Register recv_klass,
|
|
|
1391 RegisterOrConstant vtable_index,
|
|
|
1392 Register method_result);
|
|
|
1393
|
|
|
1394 // Test sub_klass against super_klass, with fast and slow paths.
|
|
|
1395
|
|
|
1396 // The fast path produces a tri-state answer: yes / no / maybe-slow.
|
|
|
1397 // One of the three labels can be NULL, meaning take the fall-through.
|
|
|
1398 // If super_check_offset is -1, the value is loaded up from super_klass.
|
|
|
1399 // No registers are killed, except temp_reg and temp2_reg.
|
|
|
1400 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
|
|
|
1401 void check_klass_subtype_fast_path(Register sub_klass,
|
|
|
1402 Register super_klass,
|
|
|
1403 Register temp_reg,
|
|
|
1404 Register temp2_reg,
|
|
|
1405 Label* L_success,
|
|
|
1406 Label* L_failure,
|
|
|
1407 Label* L_slow_path,
|
|
|
1408 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
|
|
|
1409
|
|
|
1410 // The rest of the type check; must be wired to a corresponding fast path.
|
|
|
1411 // It does not repeat the fast path logic, so don't use it standalone.
|
|
|
1412 // The temp_reg can be noreg, if no temps are available.
|
|
|
1413 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
|
|
|
1414 // Updates the sub's secondary super cache as necessary.
|
|
|
1415 void check_klass_subtype_slow_path(Register sub_klass,
|
|
|
1416 Register super_klass,
|
|
|
1417 Register temp_reg,
|
|
|
1418 Register temp2_reg,
|
|
|
1419 Register temp3_reg,
|
|
|
1420 Register temp4_reg,
|
|
|
1421 Label* L_success,
|
|
|
1422 Label* L_failure);
|
|
|
1423
|
|
|
1424 // Simplified, combined version, good for typical uses.
|
|
|
1425 // Falls through on failure.
|
|
|
1426 void check_klass_subtype(Register sub_klass,
|
|
|
1427 Register super_klass,
|
|
|
1428 Register temp_reg,
|
|
|
1429 Register temp2_reg,
|
|
|
1430 Label& L_success);
|
|
|
1431
|
|
|
1432 // method handles (JSR 292)
|
|
|
1433 // offset relative to Gargs of argument at tos[arg_slot].
|
|
|
1434 // (arg_slot == 0 means the last argument, not the first).
|
|
|
1435 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot,
|
|
|
1436 Register temp_reg,
|
|
|
1437 int extra_slot_offset = 0);
|
|
|
1438 // Address of Gargs and argument_offset.
|
|
|
1439 Address argument_address(RegisterOrConstant arg_slot,
|
|
|
1440 Register temp_reg = noreg,
|
|
|
1441 int extra_slot_offset = 0);
|
|
|
1442
|
|
|
1443 // Stack overflow checking
|
|
|
1444
|
|
|
1445 // Note: this clobbers G3_scratch
|
|
|
1446 void bang_stack_with_offset(int offset) {
|
|
|
1447 // stack grows down, caller passes positive offset
|
|
|
1448 assert(offset > 0, "must bang with negative offset");
|
|
|
1449 set((-offset)+STACK_BIAS, G3_scratch);
|
|
|
1450 st(G0, SP, G3_scratch);
|
|
|
1451 }
|
|
|
1452
|
|
|
1453 // Writes to stack successive pages until offset reached to check for
|
|
|
1454 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
|
|
|
1455 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
|
|
|
1456
|
|
|
1457 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset);
|
|
|
1458
|
|
|
1459 void verify_tlab();
|
|
|
1460
|
|
|
1461 Condition negate_condition(Condition cond);
|
|
|
1462
|
|
|
1463 // Helper functions for statistics gathering.
|
|
|
1464 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
|
|
|
1465 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
|
|
|
1466 // Unconditional increment.
|
|
|
1467 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2);
|
|
|
1468 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2);
|
|
|
1469
|
|
|
1470 // Compare char[] arrays aligned to 4 bytes.
|
|
|
1471 void char_arrays_equals(Register ary1, Register ary2,
|
|
|
1472 Register limit, Register result,
|
|
|
1473 Register chr1, Register chr2, Label& Ldone);
|
|
|
1474 // Use BIS for zeroing
|
|
|
1475 void bis_zeroing(Register to, Register count, Register temp, Label& Ldone);
|
|
|
1476
|
|
|
1477 #undef VIRTUAL
|
|
|
1478 };
|
|
|
1479
|
|
|
1480 /**
|
|
|
1481 * class SkipIfEqual:
|
|
|
1482 *
|
|
|
1483 * Instantiating this class will result in assembly code being output that will
|
|
|
1484 * jump around any code emitted between the creation of the instance and it's
|
|
|
1485 * automatic destruction at the end of a scope block, depending on the value of
|
|
|
1486 * the flag passed to the constructor, which will be checked at run-time.
|
|
|
1487 */
|
|
|
1488 class SkipIfEqual : public StackObj {
|
|
|
1489 private:
|
|
|
1490 MacroAssembler* _masm;
|
|
|
1491 Label _label;
|
|
|
1492
|
|
|
1493 public:
|
|
|
1494 // 'temp' is a temp register that this object can use (and trash)
|
|
|
1495 SkipIfEqual(MacroAssembler*, Register temp,
|
|
|
1496 const bool* flag_addr, Assembler::Condition condition);
|
|
|
1497 ~SkipIfEqual();
|
|
|
1498 };
|
|
|
1499
|
|
|
1500 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_HPP
|
