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7204
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef CPU_SPARC_VM_MACROASSEMBLER_SPARC_INLINE_HPP
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26 #define CPU_SPARC_VM_MACROASSEMBLER_SPARC_INLINE_HPP
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27
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28 #include "asm/assembler.inline.hpp"
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29 #include "asm/macroAssembler.hpp"
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30 #include "asm/codeBuffer.hpp"
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31 #include "code/codeCache.hpp"
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32
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33 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
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34
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35
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36 inline int AddressLiteral::low10() const {
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37 return Assembler::low10(value());
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38 }
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39
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40
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41 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
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42 jint& stub_inst = *(jint*) branch;
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43 stub_inst = patched_branch(target - branch, stub_inst, 0);
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44 }
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45
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46 // Use the right loads/stores for the platform
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47 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
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48 #ifdef _LP64
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49 Assembler::ldx(s1, s2, d);
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50 #else
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51 ld( s1, s2, d);
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52 #endif
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53 }
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54
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55 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
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56 #ifdef _LP64
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57 Assembler::ldx(s1, simm13a, d);
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58 #else
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59 ld( s1, simm13a, d);
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60 #endif
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61 }
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62
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63 #ifdef ASSERT
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64 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
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65 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {
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66 ld_ptr(s1, in_bytes(simm13a), d);
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67 }
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68 #endif
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69
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70 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {
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71 #ifdef _LP64
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72 ldx(s1, s2, d);
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73 #else
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74 ld( s1, s2, d);
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75 #endif
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76 }
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77
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78 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {
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79 #ifdef _LP64
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80 ldx(a, d, offset);
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81 #else
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82 ld( a, d, offset);
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83 #endif
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84 }
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85
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86 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
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87 #ifdef _LP64
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88 Assembler::stx(d, s1, s2);
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89 #else
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90 st( d, s1, s2);
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91 #endif
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92 }
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93
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94 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
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95 #ifdef _LP64
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96 Assembler::stx(d, s1, simm13a);
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97 #else
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98 st( d, s1, simm13a);
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99 #endif
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100 }
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101
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102 #ifdef ASSERT
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103 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
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104 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {
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105 st_ptr(d, s1, in_bytes(simm13a));
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106 }
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107 #endif
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108
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109 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {
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110 #ifdef _LP64
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111 stx(d, s1, s2);
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112 #else
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113 st( d, s1, s2);
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114 #endif
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115 }
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116
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117 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {
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118 #ifdef _LP64
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119 stx(d, a, offset);
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120 #else
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121 st( d, a, offset);
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122 #endif
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123 }
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124
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125 // Use the right loads/stores for the platform
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126 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
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127 #ifdef _LP64
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128 Assembler::ldx(s1, s2, d);
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129 #else
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130 Assembler::ldd(s1, s2, d);
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131 #endif
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132 }
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133
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134 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
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135 #ifdef _LP64
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136 Assembler::ldx(s1, simm13a, d);
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137 #else
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138 Assembler::ldd(s1, simm13a, d);
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139 #endif
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140 }
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141
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142 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {
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143 #ifdef _LP64
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144 ldx(s1, s2, d);
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145 #else
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146 ldd(s1, s2, d);
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147 #endif
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148 }
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149
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150 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {
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151 #ifdef _LP64
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152 ldx(a, d, offset);
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153 #else
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154 ldd(a, d, offset);
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155 #endif
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156 }
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157
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158 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
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159 #ifdef _LP64
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160 Assembler::stx(d, s1, s2);
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161 #else
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162 Assembler::std(d, s1, s2);
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163 #endif
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164 }
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165
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166 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
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167 #ifdef _LP64
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168 Assembler::stx(d, s1, simm13a);
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169 #else
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170 Assembler::std(d, s1, simm13a);
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171 #endif
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172 }
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173
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174 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {
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175 #ifdef _LP64
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176 stx(d, s1, s2);
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177 #else
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178 std(d, s1, s2);
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179 #endif
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180 }
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181
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182 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
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183 #ifdef _LP64
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184 stx(d, a, offset);
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185 #else
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186 std(d, a, offset);
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187 #endif
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188 }
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189
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190 // Functions for isolating 64 bit shifts for LP64
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191
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192 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
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193 #ifdef _LP64
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194 Assembler::sllx(s1, s2, d);
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195 #else
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196 Assembler::sll( s1, s2, d);
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197 #endif
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198 }
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199
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200 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
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201 #ifdef _LP64
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202 Assembler::sllx(s1, imm6a, d);
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203 #else
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204 Assembler::sll( s1, imm6a, d);
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205 #endif
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206 }
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207
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208 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
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209 #ifdef _LP64
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210 Assembler::srlx(s1, s2, d);
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211 #else
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212 Assembler::srl( s1, s2, d);
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213 #endif
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214 }
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215
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216 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
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217 #ifdef _LP64
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218 Assembler::srlx(s1, imm6a, d);
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219 #else
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220 Assembler::srl( s1, imm6a, d);
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221 #endif
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222 }
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223
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224 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {
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225 if (s2.is_register()) sll_ptr(s1, s2.as_register(), d);
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226 else sll_ptr(s1, s2.as_constant(), d);
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227 }
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228
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229 // Use the right branch for the platform
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230
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231 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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232 if (VM_Version::v9_instructions_work())
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233 Assembler::bp(c, a, icc, p, d, rt);
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234 else
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235 Assembler::br(c, a, d, rt);
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236 }
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237
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238 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
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239 br(c, a, p, target(L));
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240 }
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241
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242
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243 // Branch that tests either xcc or icc depending on the
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244 // architecture compiled (LP64 or not)
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245 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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246 #ifdef _LP64
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247 Assembler::bp(c, a, xcc, p, d, rt);
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248 #else
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249 MacroAssembler::br(c, a, p, d, rt);
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250 #endif
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251 }
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252
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253 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
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254 brx(c, a, p, target(L));
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255 }
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256
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257 inline void MacroAssembler::ba( Label& L ) {
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258 br(always, false, pt, L);
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259 }
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260
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261 // Warning: V9 only functions
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262 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
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263 Assembler::bp(c, a, cc, p, d, rt);
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264 }
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265
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266 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
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267 Assembler::bp(c, a, cc, p, L);
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268 }
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269
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270 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
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271 if (VM_Version::v9_instructions_work())
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272 fbp(c, a, fcc0, p, d, rt);
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273 else
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274 Assembler::fb(c, a, d, rt);
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275 }
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276
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277 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
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278 fb(c, a, p, target(L));
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279 }
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280
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281 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
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282 Assembler::fbp(c, a, cc, p, d, rt);
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283 }
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284
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285 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
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286 Assembler::fbp(c, a, cc, p, L);
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287 }
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288
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289 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
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290 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
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291
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292 inline bool MacroAssembler::is_far_target(address d) {
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293 if (ForceUnreachable) {
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294 // References outside the code cache should be treated as far
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295 return d < CodeCache::low_bound() || d > CodeCache::high_bound();
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296 }
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297 return !is_in_wdisp30_range(d, CodeCache::low_bound()) || !is_in_wdisp30_range(d, CodeCache::high_bound());
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298 }
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299
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300 // Call with a check to see if we need to deal with the added
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301 // expense of relocation and if we overflow the displacement
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302 // of the quick call instruction.
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303 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
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304 #ifdef _LP64
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305 intptr_t disp;
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306 // NULL is ok because it will be relocated later.
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307 // Must change NULL to a reachable address in order to
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308 // pass asserts here and in wdisp.
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309 if ( d == NULL )
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310 d = pc();
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311
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312 // Is this address within range of the call instruction?
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313 // If not, use the expensive instruction sequence
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314 if (is_far_target(d)) {
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315 relocate(rt);
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316 AddressLiteral dest(d);
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317 jumpl_to(dest, O7, O7);
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318 } else {
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319 Assembler::call(d, rt);
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320 }
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321 #else
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322 Assembler::call( d, rt );
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323 #endif
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324 }
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325
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326 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
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327 MacroAssembler::call( target(L), rt);
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328 }
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329
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330
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331
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332 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
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333 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
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334
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335 // prefetch instruction
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336 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
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337 if (VM_Version::v9_instructions_work())
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338 Assembler::bp( never, true, xcc, pt, d, rt );
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339 }
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340 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
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341
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342
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343 // clobbers o7 on V8!!
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344 // returns delta from gotten pc to addr after
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345 inline int MacroAssembler::get_pc( Register d ) {
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346 int x = offset();
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347 if (VM_Version::v9_instructions_work())
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348 rdpc(d);
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349 else {
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350 Label lbl;
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351 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
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352 if (d == O7) delayed()->nop();
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353 else delayed()->mov(O7, d);
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354 bind(lbl);
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355 }
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356 return offset() - x;
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357 }
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358
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359
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360 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
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361
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362
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363 // Loads the current PC of the following instruction as an immediate value in
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364 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
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365 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
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366 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
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367 #ifdef _LP64
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368 Unimplemented();
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369 #else
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370 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
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371 add(reg, thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
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372 #endif
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373 return thepc;
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374 }
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375
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376
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377 inline void MacroAssembler::load_contents(const AddressLiteral& addrlit, Register d, int offset) {
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378 assert_not_delayed();
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379 if (ForceUnreachable) {
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380 patchable_sethi(addrlit, d);
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381 } else {
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382 sethi(addrlit, d);
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383 }
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384 ld(d, addrlit.low10() + offset, d);
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385 }
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386
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387
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388 inline void MacroAssembler::load_bool_contents(const AddressLiteral& addrlit, Register d, int offset) {
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389 assert_not_delayed();
|
|
|
390 if (ForceUnreachable) {
|
|
|
391 patchable_sethi(addrlit, d);
|
|
|
392 } else {
|
|
|
393 sethi(addrlit, d);
|
|
|
394 }
|
|
|
395 ldub(d, addrlit.low10() + offset, d);
|
|
|
396 }
|
|
|
397
|
|
|
398
|
|
|
399 inline void MacroAssembler::load_ptr_contents(const AddressLiteral& addrlit, Register d, int offset) {
|
|
|
400 assert_not_delayed();
|
|
|
401 if (ForceUnreachable) {
|
|
|
402 patchable_sethi(addrlit, d);
|
|
|
403 } else {
|
|
|
404 sethi(addrlit, d);
|
|
|
405 }
|
|
|
406 ld_ptr(d, addrlit.low10() + offset, d);
|
|
|
407 }
|
|
|
408
|
|
|
409
|
|
|
410 inline void MacroAssembler::store_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
|
|
|
411 assert_not_delayed();
|
|
|
412 if (ForceUnreachable) {
|
|
|
413 patchable_sethi(addrlit, temp);
|
|
|
414 } else {
|
|
|
415 sethi(addrlit, temp);
|
|
|
416 }
|
|
|
417 st(s, temp, addrlit.low10() + offset);
|
|
|
418 }
|
|
|
419
|
|
|
420
|
|
|
421 inline void MacroAssembler::store_ptr_contents(Register s, const AddressLiteral& addrlit, Register temp, int offset) {
|
|
|
422 assert_not_delayed();
|
|
|
423 if (ForceUnreachable) {
|
|
|
424 patchable_sethi(addrlit, temp);
|
|
|
425 } else {
|
|
|
426 sethi(addrlit, temp);
|
|
|
427 }
|
|
|
428 st_ptr(s, temp, addrlit.low10() + offset);
|
|
|
429 }
|
|
|
430
|
|
|
431
|
|
|
432 // This code sequence is relocatable to any address, even on LP64.
|
|
|
433 inline void MacroAssembler::jumpl_to(const AddressLiteral& addrlit, Register temp, Register d, int offset) {
|
|
|
434 assert_not_delayed();
|
|
|
435 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
|
|
|
436 // variable length instruction streams.
|
|
|
437 patchable_sethi(addrlit, temp);
|
|
|
438 jmpl(temp, addrlit.low10() + offset, d);
|
|
|
439 }
|
|
|
440
|
|
|
441
|
|
|
442 inline void MacroAssembler::jump_to(const AddressLiteral& addrlit, Register temp, int offset) {
|
|
|
443 jumpl_to(addrlit, temp, G0, offset);
|
|
|
444 }
|
|
|
445
|
|
|
446
|
|
|
447 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,
|
|
|
448 int ld_offset, int jmp_offset) {
|
|
|
449 assert_not_delayed();
|
|
|
450 //sethi(al); // sethi is caller responsibility for this one
|
|
|
451 ld_ptr(a, temp, ld_offset);
|
|
|
452 jmp(temp, jmp_offset);
|
|
|
453 }
|
|
|
454
|
|
|
455
|
|
|
456 inline void MacroAssembler::set_metadata(Metadata* obj, Register d) {
|
|
|
457 set_metadata(allocate_metadata_address(obj), d);
|
|
|
458 }
|
|
|
459
|
|
|
460 inline void MacroAssembler::set_metadata_constant(Metadata* obj, Register d) {
|
|
|
461 set_metadata(constant_metadata_address(obj), d);
|
|
|
462 }
|
|
|
463
|
|
|
464 inline void MacroAssembler::set_metadata(const AddressLiteral& obj_addr, Register d) {
|
|
|
465 assert(obj_addr.rspec().type() == relocInfo::metadata_type, "must be a metadata reloc");
|
|
|
466 set(obj_addr, d);
|
|
|
467 }
|
|
|
468
|
|
|
469 inline void MacroAssembler::set_oop(jobject obj, Register d) {
|
|
|
470 set_oop(allocate_oop_address(obj), d);
|
|
|
471 }
|
|
|
472
|
|
|
473
|
|
|
474 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
|
|
|
475 set_oop(constant_oop_address(obj), d);
|
|
|
476 }
|
|
|
477
|
|
|
478
|
|
|
479 inline void MacroAssembler::set_oop(const AddressLiteral& obj_addr, Register d) {
|
|
|
480 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
|
|
|
481 set(obj_addr, d);
|
|
|
482 }
|
|
|
483
|
|
|
484
|
|
|
485 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
|
|
|
486 if (a.is_register())
|
|
|
487 mov(a.as_register(), d);
|
|
|
488 else
|
|
|
489 ld (a.as_address(), d);
|
|
|
490 }
|
|
|
491
|
|
|
492 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
|
|
|
493 if (a.is_register())
|
|
|
494 mov(s, a.as_register());
|
|
|
495 else
|
|
|
496 st_ptr (s, a.as_address()); // ABI says everything is right justified.
|
|
|
497 }
|
|
|
498
|
|
|
499 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
|
|
|
500 if (a.is_register())
|
|
|
501 mov(s, a.as_register());
|
|
|
502 else
|
|
|
503 st_ptr (s, a.as_address());
|
|
|
504 }
|
|
|
505
|
|
|
506
|
|
|
507 #ifdef _LP64
|
|
|
508 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
|
|
|
509 if (a.is_float_register())
|
|
|
510 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
|
|
|
511 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
|
|
|
512 else
|
|
|
513 // Floats are stored in the high half of the stack entry
|
|
|
514 // The low half is undefined per the ABI.
|
|
|
515 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
|
|
|
516 }
|
|
|
517
|
|
|
518 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
|
|
|
519 if (a.is_float_register())
|
|
|
520 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
|
|
|
521 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
|
|
|
522 else
|
|
|
523 stf(FloatRegisterImpl::D, s, a.as_address());
|
|
|
524 }
|
|
|
525
|
|
|
526 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
|
|
|
527 if (a.is_register())
|
|
|
528 mov(s, a.as_register());
|
|
|
529 else
|
|
|
530 stx(s, a.as_address());
|
|
|
531 }
|
|
|
532 #endif
|
|
|
533
|
|
|
534 inline void MacroAssembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype) {
|
|
|
535 relocate(rtype);
|
|
|
536 add(s1, simm13a, d);
|
|
|
537 }
|
|
|
538 inline void MacroAssembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec) {
|
|
|
539 relocate(rspec);
|
|
|
540 add(s1, simm13a, d);
|
|
|
541 }
|
|
|
542
|
|
|
543 // form effective addresses this way:
|
|
|
544 inline void MacroAssembler::add(const Address& a, Register d, int offset) {
|
|
|
545 if (a.has_index()) add(a.base(), a.index(), d);
|
|
|
546 else { add(a.base(), a.disp() + offset, d, a.rspec(offset)); offset = 0; }
|
|
|
547 if (offset != 0) add(d, offset, d);
|
|
|
548 }
|
|
|
549 inline void MacroAssembler::add(Register s1, RegisterOrConstant s2, Register d, int offset) {
|
|
|
550 if (s2.is_register()) add(s1, s2.as_register(), d);
|
|
|
551 else { add(s1, s2.as_constant() + offset, d); offset = 0; }
|
|
|
552 if (offset != 0) add(d, offset, d);
|
|
|
553 }
|
|
|
554
|
|
|
555 inline void MacroAssembler::andn(Register s1, RegisterOrConstant s2, Register d) {
|
|
|
556 if (s2.is_register()) andn(s1, s2.as_register(), d);
|
|
|
557 else andn(s1, s2.as_constant(), d);
|
|
|
558 }
|
|
|
559
|
|
|
560 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
|
|
|
561 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
|
|
|
562 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
|
|
|
563 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
|
|
|
564
|
|
|
565 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
|
|
|
566 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
|
|
|
567 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
|
|
|
568 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
|
|
|
569
|
|
|
570 #ifdef _LP64
|
|
|
571 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
|
|
|
572 inline void MacroAssembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
|
|
|
573 inline void MacroAssembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
|
|
|
574 #else
|
|
|
575 inline void MacroAssembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
|
|
|
576 inline void MacroAssembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
|
|
|
577 #endif
|
|
|
578
|
|
|
579 #ifdef ASSERT
|
|
|
580 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
|
|
|
581 # ifdef _LP64
|
|
|
582 inline void MacroAssembler::ld(Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }
|
|
|
583 # else
|
|
|
584 inline void MacroAssembler::ld(Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }
|
|
|
585 # endif
|
|
|
586 #endif
|
|
|
587
|
|
|
588 inline void MacroAssembler::ld( const Address& a, Register d, int offset) {
|
|
|
589 if (a.has_index()) { assert(offset == 0, ""); ld( a.base(), a.index(), d); }
|
|
|
590 else { ld( a.base(), a.disp() + offset, d); }
|
|
|
591 }
|
|
|
592
|
|
|
593 inline void MacroAssembler::ldsb(const Address& a, Register d, int offset) {
|
|
|
594 if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(), d); }
|
|
|
595 else { ldsb(a.base(), a.disp() + offset, d); }
|
|
|
596 }
|
|
|
597 inline void MacroAssembler::ldsh(const Address& a, Register d, int offset) {
|
|
|
598 if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(), d); }
|
|
|
599 else { ldsh(a.base(), a.disp() + offset, d); }
|
|
|
600 }
|
|
|
601 inline void MacroAssembler::ldsw(const Address& a, Register d, int offset) {
|
|
|
602 if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(), d); }
|
|
|
603 else { ldsw(a.base(), a.disp() + offset, d); }
|
|
|
604 }
|
|
|
605 inline void MacroAssembler::ldub(const Address& a, Register d, int offset) {
|
|
|
606 if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(), d); }
|
|
|
607 else { ldub(a.base(), a.disp() + offset, d); }
|
|
|
608 }
|
|
|
609 inline void MacroAssembler::lduh(const Address& a, Register d, int offset) {
|
|
|
610 if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(), d); }
|
|
|
611 else { lduh(a.base(), a.disp() + offset, d); }
|
|
|
612 }
|
|
|
613 inline void MacroAssembler::lduw(const Address& a, Register d, int offset) {
|
|
|
614 if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(), d); }
|
|
|
615 else { lduw(a.base(), a.disp() + offset, d); }
|
|
|
616 }
|
|
|
617 inline void MacroAssembler::ldd( const Address& a, Register d, int offset) {
|
|
|
618 if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(), d); }
|
|
|
619 else { ldd( a.base(), a.disp() + offset, d); }
|
|
|
620 }
|
|
|
621 inline void MacroAssembler::ldx( const Address& a, Register d, int offset) {
|
|
|
622 if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(), d); }
|
|
|
623 else { ldx( a.base(), a.disp() + offset, d); }
|
|
|
624 }
|
|
|
625
|
|
|
626 inline void MacroAssembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }
|
|
|
627 inline void MacroAssembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }
|
|
|
628 inline void MacroAssembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }
|
|
|
629 inline void MacroAssembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }
|
|
|
630 inline void MacroAssembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }
|
|
|
631 inline void MacroAssembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }
|
|
|
632 inline void MacroAssembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }
|
|
|
633 inline void MacroAssembler::ld( Register s1, RegisterOrConstant s2, Register d) { ld( Address(s1, s2), d); }
|
|
|
634 inline void MacroAssembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }
|
|
|
635
|
|
|
636 inline void MacroAssembler::ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d) {
|
|
|
637 if (s2.is_register()) ldf(w, s1, s2.as_register(), d);
|
|
|
638 else ldf(w, s1, s2.as_constant(), d);
|
|
|
639 }
|
|
|
640
|
|
|
641 inline void MacroAssembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) {
|
|
|
642 relocate(a.rspec(offset));
|
|
|
643 ldf(w, a.base(), a.disp() + offset, d);
|
|
|
644 }
|
|
|
645
|
|
|
646 // returns if membar generates anything, obviously this code should mirror
|
|
|
647 // membar below.
|
|
|
648 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
|
|
|
649 if( !os::is_MP() ) return false; // Not needed on single CPU
|
|
|
650 if( VM_Version::v9_instructions_work() ) {
|
|
|
651 const Membar_mask_bits effective_mask =
|
|
|
652 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
|
|
|
653 return (effective_mask != 0);
|
|
|
654 } else {
|
|
|
655 return true;
|
|
|
656 }
|
|
|
657 }
|
|
|
658
|
|
|
659 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
|
|
|
660 // Uniprocessors do not need memory barriers
|
|
|
661 if (!os::is_MP()) return;
|
|
|
662 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
|
|
|
663 // 8.4.4.3, a.31 and a.50.
|
|
|
664 if( VM_Version::v9_instructions_work() ) {
|
|
|
665 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
|
|
|
666 // of the mmask subfield of const7a that does anything that isn't done
|
|
|
667 // implicitly is StoreLoad.
|
|
|
668 const Membar_mask_bits effective_mask =
|
|
|
669 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
|
|
|
670 if ( effective_mask != 0 ) {
|
|
|
671 Assembler::membar( effective_mask );
|
|
|
672 }
|
|
|
673 } else {
|
|
|
674 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
|
|
|
675 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
|
|
|
676 // which guarantees that all stores behave as if an stbar were issued just after
|
|
|
677 // each one of them. On these machines, stbar ought to be a nop. There doesn't
|
|
|
678 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
|
|
|
679 // it can't be specified by stbar, nor have I come up with a way to simulate it.
|
|
|
680 //
|
|
|
681 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
|
|
|
682 // space. Put one here to be on the safe side.
|
|
|
683 Assembler::ldstub(SP, 0, G0);
|
|
|
684 }
|
|
|
685 }
|
|
|
686
|
|
|
687 inline void MacroAssembler::prefetch(const Address& a, PrefetchFcn f, int offset) {
|
|
|
688 relocate(a.rspec(offset));
|
|
|
689 assert(!a.has_index(), "");
|
|
|
690 prefetch(a.base(), a.disp() + offset, f);
|
|
|
691 }
|
|
|
692
|
|
|
693 inline void MacroAssembler::st(Register d, Register s1, Register s2) { stw(d, s1, s2); }
|
|
|
694 inline void MacroAssembler::st(Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
|
|
|
695
|
|
|
696 #ifdef ASSERT
|
|
|
697 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
|
|
|
698 inline void MacroAssembler::st(Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }
|
|
|
699 #endif
|
|
|
700
|
|
|
701 inline void MacroAssembler::st(Register d, const Address& a, int offset) {
|
|
|
702 if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index() ); }
|
|
|
703 else { st( d, a.base(), a.disp() + offset); }
|
|
|
704 }
|
|
|
705
|
|
|
706 inline void MacroAssembler::stb(Register d, const Address& a, int offset) {
|
|
|
707 if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index() ); }
|
|
|
708 else { stb(d, a.base(), a.disp() + offset); }
|
|
|
709 }
|
|
|
710 inline void MacroAssembler::sth(Register d, const Address& a, int offset) {
|
|
|
711 if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index() ); }
|
|
|
712 else { sth(d, a.base(), a.disp() + offset); }
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713 }
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714 inline void MacroAssembler::stw(Register d, const Address& a, int offset) {
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715 if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index() ); }
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716 else { stw(d, a.base(), a.disp() + offset); }
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717 }
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718 inline void MacroAssembler::std(Register d, const Address& a, int offset) {
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719 if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index() ); }
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720 else { std(d, a.base(), a.disp() + offset); }
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721 }
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722 inline void MacroAssembler::stx(Register d, const Address& a, int offset) {
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723 if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index() ); }
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724 else { stx(d, a.base(), a.disp() + offset); }
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725 }
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726
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727 inline void MacroAssembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }
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728 inline void MacroAssembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }
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729 inline void MacroAssembler::stw(Register d, Register s1, RegisterOrConstant s2) { stw(d, Address(s1, s2)); }
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730 inline void MacroAssembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }
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731 inline void MacroAssembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }
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732 inline void MacroAssembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }
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733
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734 inline void MacroAssembler::stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2) {
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735 if (s2.is_register()) stf(w, d, s1, s2.as_register());
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736 else stf(w, d, s1, s2.as_constant());
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737 }
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738
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739 inline void MacroAssembler::stf(FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) {
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740 relocate(a.rspec(offset));
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741 if (a.has_index()) { assert(offset == 0, ""); stf(w, d, a.base(), a.index() ); }
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742 else { stf(w, d, a.base(), a.disp() + offset); }
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743 }
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744
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745 inline void MacroAssembler::sub(Register s1, RegisterOrConstant s2, Register d, int offset) {
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746 if (s2.is_register()) sub(s1, s2.as_register(), d);
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747 else { sub(s1, s2.as_constant() + offset, d); offset = 0; }
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748 if (offset != 0) sub(d, offset, d);
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749 }
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750
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751 inline void MacroAssembler::swap(Address& a, Register d, int offset) {
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752 relocate(a.rspec(offset));
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753 if (a.has_index()) { assert(offset == 0, ""); swap(a.base(), a.index(), d ); }
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754 else { swap(a.base(), a.disp() + offset, d); }
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755 }
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756
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757 #endif // CPU_SPARC_VM_MACROASSEMBLER_SPARC_INLINE_HPP
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