Mercurial > hg > truffle
annotate graal/GraalCompiler/src/com/sun/c1x/target/amd64/AMD64MacroAssembler.java @ 2613:2523de4d378e
merge
author | Lukas Stadler <lukas.stadler@jku.at> |
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date | Mon, 09 May 2011 10:53:30 +0200 |
parents | 16b9a8b5ad39 |
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rev | line source |
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1 /* |
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2 * Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.sun.c1x.target.amd64; |
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24 |
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25 import com.sun.c1x.*; |
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26 import com.sun.c1x.asm.*; |
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27 import com.sun.c1x.globalstub.*; |
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28 import com.sun.c1x.lir.*; |
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29 import com.sun.c1x.util.*; |
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30 import com.sun.cri.ci.*; |
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31 import com.sun.cri.ri.*; |
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32 import com.sun.cri.xir.*; |
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33 |
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34 /** |
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35 * This class implements the AMD64-specific portion of the macro assembler. |
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36 * |
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37 * @author Thomas Wuerthinger |
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38 * @author Ben L. Titzer |
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39 */ |
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40 public class AMD64MacroAssembler extends AMD64Assembler { |
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41 |
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42 private final CiRegister rscratch1; |
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43 |
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44 public static class WithCompiler extends AMD64MacroAssembler { |
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45 |
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46 private final C1XCompiler compiler; |
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47 |
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48 public WithCompiler(C1XCompiler compiler, RiRegisterConfig registerConfig) { |
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49 super(compiler.target, registerConfig); |
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50 this.compiler = compiler; |
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51 } |
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52 |
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53 @Override |
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54 public GlobalStub lookupGlobalStub(XirTemplate template) { |
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55 return compiler.lookupGlobalStub(template); |
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56 } |
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57 } |
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58 |
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59 public AMD64MacroAssembler(CiTarget target, RiRegisterConfig registerConfig) { |
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60 super(target, registerConfig); |
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61 this.rscratch1 = registerConfig.getScratchRegister(); |
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62 } |
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63 |
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64 /** |
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65 * Must be overridden if compiling code that makes calls to global stubs. |
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66 */ |
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67 public GlobalStub lookupGlobalStub(XirTemplate template) { |
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68 throw new IllegalArgumentException("This assembler does not support compiling calls to global stubs"); |
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69 } |
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70 |
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71 public final int callGlobalStub(XirTemplate stub, LIRDebugInfo info, CiRegister result, CiValue... args) { |
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72 assert args.length == stub.parameters.length; |
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73 return callGlobalStubHelper(lookupGlobalStub(stub), stub.resultOperand.kind, info, result, args); |
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74 } |
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75 |
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76 public final int callGlobalStub(GlobalStub stub, LIRDebugInfo info, CiRegister result, CiValue... args) { |
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77 assert args.length == stub.argOffsets.length; |
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78 return callGlobalStubHelper(stub, stub.resultKind, info, result, args); |
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79 } |
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80 |
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81 private int callGlobalStubHelper(GlobalStub stub, CiKind resultKind, LIRDebugInfo info, CiRegister result, CiValue... args) { |
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82 for (int i = 0; i < args.length; i++) { |
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83 storeParameter(args[i], stub.argOffsets[i]); |
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84 } |
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85 |
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86 int pos = directCall(stub.stubObject, info); |
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87 |
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88 if (result != CiRegister.None) { |
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89 loadResult(result, stub.resultOffset, resultKind); |
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90 } |
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91 |
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92 // Clear out parameters |
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93 if (C1XOptions.GenAssertionCode) { |
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94 for (int i = 0; i < args.length; i++) { |
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95 movptr(new CiAddress(CiKind.Word, AMD64.RSP, stub.argOffsets[i]), 0); |
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96 } |
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97 } |
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98 return pos; |
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99 } |
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100 |
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101 private void loadResult(CiRegister r, int offset, CiKind kind) { |
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102 if (kind == CiKind.Int || kind == CiKind.Boolean) { |
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103 movl(r, new CiAddress(CiKind.Int, AMD64.RSP, offset)); |
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104 } else if (kind == CiKind.Float) { |
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105 movss(r, new CiAddress(CiKind.Float, AMD64.RSP, offset)); |
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106 } else if (kind == CiKind.Double) { |
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107 movsd(r, new CiAddress(CiKind.Double, AMD64.RSP, offset)); |
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108 } else { |
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109 movq(r, new CiAddress(CiKind.Word, AMD64.RSP, offset)); |
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110 } |
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111 } |
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112 |
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113 private void storeParameter(CiValue registerOrConstant, int offset) { |
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114 CiKind k = registerOrConstant.kind; |
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115 if (registerOrConstant.isConstant()) { |
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116 CiConstant c = (CiConstant) registerOrConstant; |
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117 if (c.kind == CiKind.Object) { |
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118 movoop(new CiAddress(CiKind.Word, AMD64.RSP, offset), c); |
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119 } else { |
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120 movptr(new CiAddress(CiKind.Word, AMD64.RSP, offset), c.asInt()); |
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121 } |
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122 } else if (registerOrConstant.isRegister()) { |
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123 if (k.isFloat()) { |
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124 movss(new CiAddress(CiKind.Float, AMD64.RSP, offset), registerOrConstant.asRegister()); |
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125 } else if (k.isDouble()) { |
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126 movsd(new CiAddress(CiKind.Double, AMD64.RSP, offset), registerOrConstant.asRegister()); |
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127 } else { |
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128 movq(new CiAddress(CiKind.Word, AMD64.RSP, offset), registerOrConstant.asRegister()); |
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129 } |
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130 } else { |
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131 Util.shouldNotReachHere(); |
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132 } |
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133 } |
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134 |
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135 void movoop(CiRegister dst, CiConstant obj) { |
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136 assert obj.kind == CiKind.Object; |
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137 if (obj.isNull()) { |
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138 xorq(dst, dst); |
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139 } else { |
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140 if (target.inlineObjects) { |
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141 recordDataReferenceInCode(obj); |
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142 movq(dst, 0xDEADDEADDEADDEADL); |
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143 } else { |
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144 movq(dst, recordDataReferenceInCode(obj)); |
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145 } |
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146 } |
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147 } |
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148 |
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149 void movoop(CiAddress dst, CiConstant obj) { |
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150 movoop(rscratch1, obj); |
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151 movq(dst, rscratch1); |
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152 } |
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153 |
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154 void mov64(CiAddress dst, long src) { |
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155 movq(rscratch1, src); |
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156 movq(dst, rscratch1); |
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157 } |
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158 |
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159 void pushptr(CiAddress src) { |
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160 pushq(src); |
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161 } |
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162 |
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163 void popptr(CiAddress src) { |
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164 popq(src); |
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165 } |
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166 |
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167 void xorptr(CiRegister dst, CiRegister src) { |
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168 xorq(dst, src); |
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169 } |
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170 |
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171 void xorptr(CiRegister dst, CiAddress src) { |
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172 xorq(dst, src); |
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173 } |
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174 |
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175 // 64 bit versions |
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176 |
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177 int correctedIdivq(CiRegister reg) { |
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178 // Full implementation of Java ldiv and lrem; checks for special |
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179 // case as described in JVM spec. : p.243 & p.271. The function |
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180 // returns the (pc) offset of the idivl instruction - may be needed |
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181 // for implicit exceptions. |
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182 // |
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183 // normal case special case |
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184 // |
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185 // input : X86Register.rax: dividend minLong |
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186 // reg: divisor (may not be eax/edx) -1 |
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187 // |
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188 // output: X86Register.rax: quotient (= X86Register.rax idiv reg) minLong |
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189 // X86Register.rdx: remainder (= X86Register.rax irem reg) 0 |
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190 assert reg != AMD64.rax && reg != AMD64.rdx : "reg cannot be X86Register.rax or X86Register.rdx register"; |
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191 final long minLong = 0x8000000000000000L; |
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192 Label normalCase = new Label(); |
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193 Label specialCase = new Label(); |
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194 |
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195 // check for special case |
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196 cmpq(AMD64.rax, recordDataReferenceInCode(CiConstant.forLong(minLong))); |
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197 jcc(AMD64Assembler.ConditionFlag.notEqual, normalCase); |
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198 xorl(AMD64.rdx, AMD64.rdx); // prepare X86Register.rdx for possible special case (where |
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199 // remainder = 0) |
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200 cmpq(reg, -1); |
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201 jcc(AMD64Assembler.ConditionFlag.equal, specialCase); |
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202 |
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203 // handle normal case |
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204 bind(normalCase); |
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205 cdqq(); |
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206 int idivqOffset = codeBuffer.position(); |
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207 idivq(reg); |
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208 |
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209 // normal and special case exit |
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210 bind(specialCase); |
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211 |
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212 return idivqOffset; |
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213 } |
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214 |
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215 void decrementq(CiRegister reg, int value) { |
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216 if (value == Integer.MIN_VALUE) { |
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217 subq(reg, value); |
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218 return; |
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219 } |
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220 if (value < 0) { |
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221 incrementq(reg, -value); |
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222 return; |
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223 } |
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224 if (value == 0) { |
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225 return; |
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226 } |
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227 if (value == 1 && C1XOptions.UseIncDec) { |
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228 decq(reg); |
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229 } else { |
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230 subq(reg, value); |
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231 } |
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232 } |
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233 |
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234 void incrementq(CiRegister reg, int value) { |
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235 if (value == Integer.MIN_VALUE) { |
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236 addq(reg, value); |
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237 return; |
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238 } |
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239 if (value < 0) { |
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240 decrementq(reg, -value); |
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241 return; |
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242 } |
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243 if (value == 0) { |
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244 return; |
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245 } |
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246 if (value == 1 && C1XOptions.UseIncDec) { |
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247 incq(reg); |
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248 } else { |
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249 addq(reg, value); |
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250 } |
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251 } |
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252 |
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253 // These are mostly for initializing null |
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254 void movptr(CiAddress dst, int src) { |
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255 movslq(dst, src); |
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256 } |
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257 |
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258 void stop(String msg) { |
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259 if (C1XOptions.GenAssertionCode) { |
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260 // TODO: pass a pointer to the message |
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261 directCall(CiRuntimeCall.Debug, null); |
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262 hlt(); |
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263 } |
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264 } |
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265 |
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266 public final void cmp32(CiRegister src1, int imm) { |
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267 cmpl(src1, imm); |
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268 } |
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269 |
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270 public final void cmp32(CiRegister src1, CiAddress src2) { |
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271 cmpl(src1, src2); |
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272 } |
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273 |
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274 void cmpsd2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) { |
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275 assert opr1.isFpu() && opr2.isFpu(); |
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276 ucomisd(opr1, opr2); |
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277 |
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278 Label l = new Label(); |
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279 if (unorderedIsLess) { |
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280 movl(dst, -1); |
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281 jcc(AMD64Assembler.ConditionFlag.parity, l); |
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282 jcc(AMD64Assembler.ConditionFlag.below, l); |
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283 movl(dst, 0); |
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284 jcc(AMD64Assembler.ConditionFlag.equal, l); |
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285 incrementl(dst, 1); |
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286 } else { // unordered is greater |
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287 movl(dst, 1); |
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288 jcc(AMD64Assembler.ConditionFlag.parity, l); |
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289 jcc(AMD64Assembler.ConditionFlag.above, l); |
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290 movl(dst, 0); |
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291 jcc(AMD64Assembler.ConditionFlag.equal, l); |
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292 decrementl(dst, 1); |
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293 } |
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294 bind(l); |
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295 } |
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296 |
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297 void cmpss2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) { |
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298 assert opr1.isFpu(); |
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299 assert opr2.isFpu(); |
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300 ucomiss(opr1, opr2); |
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301 |
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302 Label l = new Label(); |
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303 if (unorderedIsLess) { |
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304 movl(dst, -1); |
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305 jcc(AMD64Assembler.ConditionFlag.parity, l); |
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306 jcc(AMD64Assembler.ConditionFlag.below, l); |
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307 movl(dst, 0); |
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308 jcc(AMD64Assembler.ConditionFlag.equal, l); |
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309 incrementl(dst, 1); |
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310 } else { // unordered is greater |
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311 movl(dst, 1); |
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312 jcc(AMD64Assembler.ConditionFlag.parity, l); |
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313 jcc(AMD64Assembler.ConditionFlag.above, l); |
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314 movl(dst, 0); |
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315 jcc(AMD64Assembler.ConditionFlag.equal, l); |
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316 decrementl(dst, 1); |
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317 } |
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318 bind(l); |
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319 } |
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320 |
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321 void cmpptr(CiRegister src1, CiRegister src2) { |
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322 cmpq(src1, src2); |
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323 } |
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324 |
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325 void cmpptr(CiRegister src1, CiAddress src2) { |
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326 cmpq(src1, src2); |
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327 } |
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328 |
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329 void cmpptr(CiRegister src1, int src2) { |
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330 cmpq(src1, src2); |
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331 } |
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332 |
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333 void cmpptr(CiAddress src1, int src2) { |
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334 cmpq(src1, src2); |
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335 } |
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336 |
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337 void decrementl(CiRegister reg, int value) { |
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338 if (value == Integer.MIN_VALUE) { |
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339 subl(reg, value); |
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340 return; |
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341 } |
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342 if (value < 0) { |
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343 incrementl(reg, -value); |
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344 return; |
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345 } |
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346 if (value == 0) { |
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347 return; |
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348 } |
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349 if (value == 1 && C1XOptions.UseIncDec) { |
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350 decl(reg); |
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351 } else { |
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352 subl(reg, value); |
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353 } |
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354 } |
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355 |
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356 void decrementl(CiAddress dst, int value) { |
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357 if (value == Integer.MIN_VALUE) { |
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358 subl(dst, value); |
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359 return; |
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360 } |
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361 if (value < 0) { |
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|
362 incrementl(dst, -value); |
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363 return; |
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364 } |
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365 if (value == 0) { |
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366 return; |
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367 } |
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368 if (value == 1 && C1XOptions.UseIncDec) { |
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369 decl(dst); |
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370 } else { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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371 subl(dst, value); |
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372 } |
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|
373 } |
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374 |
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375 void incrementl(CiRegister reg, int value) { |
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376 if (value == Integer.MIN_VALUE) { |
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377 addl(reg, value); |
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378 return; |
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379 } |
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380 if (value < 0) { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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381 decrementl(reg, -value); |
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382 return; |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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383 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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384 if (value == 0) { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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385 return; |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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386 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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387 if (value == 1 && C1XOptions.UseIncDec) { |
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388 incl(reg); |
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parents:
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389 } else { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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390 addl(reg, value); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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391 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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392 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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393 |
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394 void incrementl(CiAddress dst, int value) { |
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395 if (value == Integer.MIN_VALUE) { |
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396 addl(dst, value); |
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397 return; |
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398 } |
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399 if (value < 0) { |
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400 decrementl(dst, -value); |
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401 return; |
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402 } |
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403 if (value == 0) { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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404 return; |
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405 } |
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406 if (value == 1 && C1XOptions.UseIncDec) { |
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407 incl(dst); |
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408 } else { |
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409 addl(dst, value); |
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410 } |
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411 } |
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412 |
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413 void signExtendByte(CiRegister reg) { |
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414 if (reg.isByte()) { |
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415 movsxb(reg, reg); // movsxb |
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416 } else { |
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417 shll(reg, 24); |
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418 sarl(reg, 24); |
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419 } |
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420 } |
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421 |
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422 void signExtendShort(CiRegister reg) { |
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423 movsxw(reg, reg); // movsxw |
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424 } |
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425 |
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426 // Support optimal SSE move instructions. |
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427 void movflt(CiRegister dst, CiRegister src) { |
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428 assert dst.isFpu() && src.isFpu(); |
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429 if (C1XOptions.UseXmmRegToRegMoveAll) { |
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430 movaps(dst, src); |
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431 } else { |
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432 movss(dst, src); |
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433 } |
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434 } |
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435 |
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436 void movflt(CiRegister dst, CiAddress src) { |
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437 assert dst.isFpu(); |
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438 movss(dst, src); |
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439 } |
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440 |
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441 void movflt(CiAddress dst, CiRegister src) { |
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442 assert src.isFpu(); |
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443 movss(dst, src); |
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444 } |
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445 |
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446 void movdbl(CiRegister dst, CiRegister src) { |
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447 assert dst.isFpu() && src.isFpu(); |
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448 if (C1XOptions.UseXmmRegToRegMoveAll) { |
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449 movapd(dst, src); |
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450 } else { |
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451 movsd(dst, src); |
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452 } |
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diff
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|
453 } |
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|
454 |
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455 void movdbl(CiRegister dst, CiAddress src) { |
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456 assert dst.isFpu(); |
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457 if (C1XOptions.UseXmmLoadAndClearUpper) { |
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458 movsd(dst, src); |
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diff
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459 } else { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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|
460 movlpd(dst, src); |
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parents:
diff
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461 } |
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parents:
diff
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|
462 } |
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diff
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|
463 |
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464 void xchgptr(CiRegister src1, CiRegister src2) { |
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465 xchgq(src1, src2); |
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466 } |
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|
467 |
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468 public void shouldNotReachHere() { |
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469 stop("should not reach here"); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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470 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
471 |
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472 public void enter(short imm16, byte imm8) { |
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473 emitByte(0xC8); |
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diff
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474 // appended: |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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475 emitByte(imm16 & 0xff); |
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parents:
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476 imm16 >>= 8; |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
477 emitByte(imm16 & 0xff); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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478 emitByte(imm8); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
479 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
480 |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
481 /** |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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482 * Emit code to save a given set of callee save registers to the |
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483 * {@linkplain CiCalleeSaveArea CSA} within the frame. |
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484 * @param csa the description of the CSA |
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485 * @param frameToCSA offset from the frame pointer to the CSA |
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486 */ |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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487 public void save(CiCalleeSaveArea csa, int frameToCSA) { |
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parents:
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488 CiRegisterValue frame = frameRegister.asValue(); |
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parents:
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489 for (CiRegister r : csa.registers) { |
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490 int offset = csa.offsetOf(r); |
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491 movq(new CiAddress(CiKind.Word, frame, frameToCSA + offset), r); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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492 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
493 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
494 |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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495 public void restore(CiCalleeSaveArea csa, int frameToCSA) { |
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parents:
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496 CiRegisterValue frame = frameRegister.asValue(); |
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parents:
diff
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497 for (CiRegister r : csa.registers) { |
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parents:
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498 int offset = csa.offsetOf(r); |
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parents:
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499 movq(r, new CiAddress(CiKind.Word, frame, frameToCSA + offset)); |
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parents:
diff
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|
500 } |
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parents:
diff
changeset
|
501 } |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
502 |
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parents:
diff
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|
503 public void int3() { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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504 emitByte(0xCC); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
505 } |
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parents:
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|
506 } |