Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vmreg_sparc.inline.hpp @ 4591:33f181ad79d5
changed DynamicSizeBasedInliningPolicy to use log(probability) for frequently executed loops, added check for SmallCompiledCodeSize to WeightBasedInliningPolicy.
author | Christian Haeubl <christian.haeubl@oracle.com> |
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date | Mon, 13 Feb 2012 18:40:54 -0800 |
parents | f95d63e2154a |
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rev | line source |
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0 | 1 /* |
1972 | 2 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP |
26 #define CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP | |
27 | |
0 | 28 inline VMReg RegisterImpl::as_VMReg() { |
29 if( this==noreg ) return VMRegImpl::Bad(); | |
30 return VMRegImpl::as_VMReg(encoding() << 1 ); | |
31 } | |
32 | |
33 inline VMReg FloatRegisterImpl::as_VMReg() { return VMRegImpl::as_VMReg( ConcreteRegisterImpl::max_gpr + encoding() ); } | |
34 | |
35 | |
36 inline bool VMRegImpl::is_Register() { return value() >= 0 && value() < ConcreteRegisterImpl::max_gpr; } | |
37 inline bool VMRegImpl::is_FloatRegister() { return value() >= ConcreteRegisterImpl::max_gpr && | |
38 value() < ConcreteRegisterImpl::max_fpr; } | |
39 inline Register VMRegImpl::as_Register() { | |
40 | |
41 assert( is_Register() && is_even(value()), "even-aligned GPR name" ); | |
42 // Yuk | |
43 return ::as_Register(value()>>1); | |
44 } | |
45 | |
46 inline FloatRegister VMRegImpl::as_FloatRegister() { | |
47 assert( is_FloatRegister(), "must be" ); | |
48 // Yuk | |
49 return ::as_FloatRegister( value() - ConcreteRegisterImpl::max_gpr ); | |
50 } | |
51 | |
52 inline bool VMRegImpl::is_concrete() { | |
53 assert(is_reg(), "must be"); | |
54 int v = value(); | |
55 if ( v < ConcreteRegisterImpl::max_gpr ) { | |
56 return is_even(v); | |
57 } | |
58 // F0..F31 | |
59 if ( v <= ConcreteRegisterImpl::max_gpr + 31) return true; | |
60 if ( v < ConcreteRegisterImpl::max_fpr) { | |
61 return is_even(v); | |
62 } | |
63 assert(false, "what register?"); | |
64 return false; | |
65 } | |
1972 | 66 |
67 #endif // CPU_SPARC_VM_VMREG_SPARC_INLINE_HPP |